d1_pac/gpadc/
gp_datah_intc.rs

1#[doc = "Register `gp_datah_intc` reader"]
2pub type R = crate::R<GP_DATAH_INTC_SPEC>;
3#[doc = "Register `gp_datah_intc` writer"]
4pub type W = crate::W<GP_DATAH_INTC_SPEC>;
5#[doc = "Field `ch_hig_irq_en[0-1]` reader - Channel Voltage High Available Interrupt Enable"]
6pub type CH_HIG_IRQ_EN_R = crate::BitReader<CH_HIG_IRQ_EN_A>;
7#[doc = "Channel Voltage High Available Interrupt Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CH_HIG_IRQ_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<CH_HIG_IRQ_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: CH_HIG_IRQ_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CH_HIG_IRQ_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CH_HIG_IRQ_EN_A {
25        match self.bits {
26            false => CH_HIG_IRQ_EN_A::DISABLE,
27            true => CH_HIG_IRQ_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == CH_HIG_IRQ_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == CH_HIG_IRQ_EN_A::ENABLE
39    }
40}
41#[doc = "Field `ch_hig_irq_en[0-1]` writer - Channel Voltage High Available Interrupt Enable"]
42pub type CH_HIG_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, CH_HIG_IRQ_EN_A>;
43impl<'a, REG> CH_HIG_IRQ_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(CH_HIG_IRQ_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(CH_HIG_IRQ_EN_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "Channel Voltage High Available Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `ch0_hig_irq_en` field"]
60    #[inline(always)]
61    pub fn ch_hig_irq_en(&self, n: u8) -> CH_HIG_IRQ_EN_R {
62        #[allow(clippy::no_effect)]
63        [(); 2][n as usize];
64        CH_HIG_IRQ_EN_R::new(((self.bits >> n) & 1) != 0)
65    }
66    #[doc = "Bit 0 - Channel Voltage High Available Interrupt Enable"]
67    #[inline(always)]
68    pub fn ch0_hig_irq_en(&self) -> CH_HIG_IRQ_EN_R {
69        CH_HIG_IRQ_EN_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Channel Voltage High Available Interrupt Enable"]
72    #[inline(always)]
73    pub fn ch1_hig_irq_en(&self) -> CH_HIG_IRQ_EN_R {
74        CH_HIG_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
75    }
76}
77impl W {
78    #[doc = "Channel Voltage High Available Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `ch0_hig_irq_en` field"]
79    #[inline(always)]
80    #[must_use]
81    pub fn ch_hig_irq_en(&mut self, n: u8) -> CH_HIG_IRQ_EN_W<GP_DATAH_INTC_SPEC> {
82        #[allow(clippy::no_effect)]
83        [(); 2][n as usize];
84        CH_HIG_IRQ_EN_W::new(self, n)
85    }
86    #[doc = "Bit 0 - Channel Voltage High Available Interrupt Enable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn ch0_hig_irq_en(&mut self) -> CH_HIG_IRQ_EN_W<GP_DATAH_INTC_SPEC> {
90        CH_HIG_IRQ_EN_W::new(self, 0)
91    }
92    #[doc = "Bit 1 - Channel Voltage High Available Interrupt Enable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn ch1_hig_irq_en(&mut self) -> CH_HIG_IRQ_EN_W<GP_DATAH_INTC_SPEC> {
96        CH_HIG_IRQ_EN_W::new(self, 1)
97    }
98    #[doc = r" Writes raw bits to the register."]
99    #[doc = r""]
100    #[doc = r" # Safety"]
101    #[doc = r""]
102    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.bits = bits;
106        self
107    }
108}
109#[doc = "GPADC Data High Interrupt Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gp_datah_intc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gp_datah_intc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
110pub struct GP_DATAH_INTC_SPEC;
111impl crate::RegisterSpec for GP_DATAH_INTC_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [`gp_datah_intc::R`](R) reader structure"]
115impl crate::Readable for GP_DATAH_INTC_SPEC {}
116#[doc = "`write(|w| ..)` method takes [`gp_datah_intc::W`](W) writer structure"]
117impl crate::Writable for GP_DATAH_INTC_SPEC {
118    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
119    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120}
121#[doc = "`reset()` method sets gp_datah_intc to value 0"]
122impl crate::Resettable for GP_DATAH_INTC_SPEC {
123    const RESET_VALUE: Self::Ux = 0;
124}
d1_pac/gpadc/gp_datah_intc.rs

d1_pac/gpadc/
gp_datah_intc.rs
