d1_pac/emac/
emac_tx_flow_ctl.rs

1#[doc = "Register `emac_tx_flow_ctl` reader"]
2pub type R = crate::R<EMAC_TX_FLOW_CTL_SPEC>;
3#[doc = "Register `emac_tx_flow_ctl` writer"]
4pub type W = crate::W<EMAC_TX_FLOW_CTL_SPEC>;
5#[doc = "Field `tx_flow_ctl_en` reader - TX Flow Control Enable"]
6pub type TX_FLOW_CTL_EN_R = crate::BitReader<TX_FLOW_CTL_EN_A>;
7#[doc = "TX Flow Control Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TX_FLOW_CTL_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<TX_FLOW_CTL_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TX_FLOW_CTL_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TX_FLOW_CTL_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TX_FLOW_CTL_EN_A {
25        match self.bits {
26            false => TX_FLOW_CTL_EN_A::DISABLE,
27            true => TX_FLOW_CTL_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TX_FLOW_CTL_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TX_FLOW_CTL_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tx_flow_ctl_en` writer - TX Flow Control Enable"]
42pub type TX_FLOW_CTL_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_FLOW_CTL_EN_A>;
43impl<'a, REG> TX_FLOW_CTL_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TX_FLOW_CTL_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TX_FLOW_CTL_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `zqp_frm_en` reader - "]
59pub type ZQP_FRM_EN_R = crate::BitReader<ZQP_FRM_EN_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ZQP_FRM_EN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<ZQP_FRM_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: ZQP_FRM_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl ZQP_FRM_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> ZQP_FRM_EN_A {
78        match self.bits {
79            false => ZQP_FRM_EN_A::DISABLE,
80            true => ZQP_FRM_EN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == ZQP_FRM_EN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == ZQP_FRM_EN_A::ENABLE
92    }
93}
94#[doc = "Field `zqp_frm_en` writer - "]
95pub type ZQP_FRM_EN_W<'a, REG> = crate::BitWriter<'a, REG, ZQP_FRM_EN_A>;
96impl<'a, REG> ZQP_FRM_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(ZQP_FRM_EN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(ZQP_FRM_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `pause_time` reader - "]
112pub type PAUSE_TIME_R = crate::FieldReader<u16>;
113#[doc = "Field `pause_time` writer - "]
114pub type PAUSE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
115#[doc = "Field `tx_pause_frm_slot` reader - "]
116pub type TX_PAUSE_FRM_SLOT_R = crate::FieldReader;
117#[doc = "Field `tx_pause_frm_slot` writer - "]
118pub type TX_PAUSE_FRM_SLOT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
119#[doc = "Field `tx_flow_ctl_sta` reader - "]
120pub type TX_FLOW_CTL_STA_R = crate::BitReader;
121#[doc = "Field `tx_flow_ctl_sta` writer - "]
122pub type TX_FLOW_CTL_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
123impl R {
124    #[doc = "Bit 0 - TX Flow Control Enable"]
125    #[inline(always)]
126    pub fn tx_flow_ctl_en(&self) -> TX_FLOW_CTL_EN_R {
127        TX_FLOW_CTL_EN_R::new((self.bits & 1) != 0)
128    }
129    #[doc = "Bit 1"]
130    #[inline(always)]
131    pub fn zqp_frm_en(&self) -> ZQP_FRM_EN_R {
132        ZQP_FRM_EN_R::new(((self.bits >> 1) & 1) != 0)
133    }
134    #[doc = "Bits 4:19"]
135    #[inline(always)]
136    pub fn pause_time(&self) -> PAUSE_TIME_R {
137        PAUSE_TIME_R::new(((self.bits >> 4) & 0xffff) as u16)
138    }
139    #[doc = "Bits 20:21"]
140    #[inline(always)]
141    pub fn tx_pause_frm_slot(&self) -> TX_PAUSE_FRM_SLOT_R {
142        TX_PAUSE_FRM_SLOT_R::new(((self.bits >> 20) & 3) as u8)
143    }
144    #[doc = "Bit 31"]
145    #[inline(always)]
146    pub fn tx_flow_ctl_sta(&self) -> TX_FLOW_CTL_STA_R {
147        TX_FLOW_CTL_STA_R::new(((self.bits >> 31) & 1) != 0)
148    }
149}
150impl W {
151    #[doc = "Bit 0 - TX Flow Control Enable"]
152    #[inline(always)]
153    #[must_use]
154    pub fn tx_flow_ctl_en(&mut self) -> TX_FLOW_CTL_EN_W<EMAC_TX_FLOW_CTL_SPEC> {
155        TX_FLOW_CTL_EN_W::new(self, 0)
156    }
157    #[doc = "Bit 1"]
158    #[inline(always)]
159    #[must_use]
160    pub fn zqp_frm_en(&mut self) -> ZQP_FRM_EN_W<EMAC_TX_FLOW_CTL_SPEC> {
161        ZQP_FRM_EN_W::new(self, 1)
162    }
163    #[doc = "Bits 4:19"]
164    #[inline(always)]
165    #[must_use]
166    pub fn pause_time(&mut self) -> PAUSE_TIME_W<EMAC_TX_FLOW_CTL_SPEC> {
167        PAUSE_TIME_W::new(self, 4)
168    }
169    #[doc = "Bits 20:21"]
170    #[inline(always)]
171    #[must_use]
172    pub fn tx_pause_frm_slot(&mut self) -> TX_PAUSE_FRM_SLOT_W<EMAC_TX_FLOW_CTL_SPEC> {
173        TX_PAUSE_FRM_SLOT_W::new(self, 20)
174    }
175    #[doc = "Bit 31"]
176    #[inline(always)]
177    #[must_use]
178    pub fn tx_flow_ctl_sta(&mut self) -> TX_FLOW_CTL_STA_W<EMAC_TX_FLOW_CTL_SPEC> {
179        TX_FLOW_CTL_STA_W::new(self, 31)
180    }
181    #[doc = r" Writes raw bits to the register."]
182    #[doc = r""]
183    #[doc = r" # Safety"]
184    #[doc = r""]
185    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
186    #[inline(always)]
187    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
188        self.bits = bits;
189        self
190    }
191}
192#[doc = "EMAC Transmit Flow Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_tx_flow_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_tx_flow_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
193pub struct EMAC_TX_FLOW_CTL_SPEC;
194impl crate::RegisterSpec for EMAC_TX_FLOW_CTL_SPEC {
195    type Ux = u32;
196}
197#[doc = "`read()` method returns [`emac_tx_flow_ctl::R`](R) reader structure"]
198impl crate::Readable for EMAC_TX_FLOW_CTL_SPEC {}
199#[doc = "`write(|w| ..)` method takes [`emac_tx_flow_ctl::W`](W) writer structure"]
200impl crate::Writable for EMAC_TX_FLOW_CTL_SPEC {
201    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
202    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
203}
204#[doc = "`reset()` method sets emac_tx_flow_ctl to value 0"]
205impl crate::Resettable for EMAC_TX_FLOW_CTL_SPEC {
206    const RESET_VALUE: Self::Ux = 0;
207}
d1_pac/emac/emac_tx_flow_ctl.rs

d1_pac/emac/
emac_tx_flow_ctl.rs
