d1_pac/emac/
emac_int_sta.rs

1#[doc = "Register `emac_int_sta` reader"]
2pub type R = crate::R<EMAC_INT_STA_SPEC>;
3#[doc = "Register `emac_int_sta` writer"]
4pub type W = crate::W<EMAC_INT_STA_SPEC>;
5#[doc = "Field `tx_p` reader - Frame Transmission Interrupt Pending"]
6pub type TX_P_R = crate::BitReader<TX_P_A>;
7#[doc = "Frame Transmission Interrupt Pending\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TX_P_A {
10    #[doc = "0: `0`"]
11    NO_PENDING = 0,
12    #[doc = "1: `1`"]
13    PENDING = 1,
14}
15impl From<TX_P_A> for bool {
16    #[inline(always)]
17    fn from(variant: TX_P_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TX_P_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TX_P_A {
25        match self.bits {
26            false => TX_P_A::NO_PENDING,
27            true => TX_P_A::PENDING,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_pending(&self) -> bool {
33        *self == TX_P_A::NO_PENDING
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == TX_P_A::PENDING
39    }
40}
41#[doc = "Field `tx_p` writer - Frame Transmission Interrupt Pending"]
42pub type TX_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_P_A>;
43impl<'a, REG> TX_P_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_pending(self) -> &'a mut crate::W<REG> {
50        self.variant(TX_P_A::NO_PENDING)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(TX_P_A::PENDING)
56    }
57}
58#[doc = "Field `tx_dma_stopped_p` reader - Transmission DMA Stopped Interrupt Pending"]
59pub type TX_DMA_STOPPED_P_R = crate::BitReader<TX_DMA_STOPPED_P_A>;
60#[doc = "Transmission DMA Stopped Interrupt Pending\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TX_DMA_STOPPED_P_A {
63    #[doc = "0: `0`"]
64    NO_PENDING = 0,
65    #[doc = "1: `1`"]
66    PENDING = 1,
67}
68impl From<TX_DMA_STOPPED_P_A> for bool {
69    #[inline(always)]
70    fn from(variant: TX_DMA_STOPPED_P_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TX_DMA_STOPPED_P_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TX_DMA_STOPPED_P_A {
78        match self.bits {
79            false => TX_DMA_STOPPED_P_A::NO_PENDING,
80            true => TX_DMA_STOPPED_P_A::PENDING,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_no_pending(&self) -> bool {
86        *self == TX_DMA_STOPPED_P_A::NO_PENDING
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_pending(&self) -> bool {
91        *self == TX_DMA_STOPPED_P_A::PENDING
92    }
93}
94#[doc = "Field `tx_dma_stopped_p` writer - Transmission DMA Stopped Interrupt Pending"]
95pub type TX_DMA_STOPPED_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_DMA_STOPPED_P_A>;
96impl<'a, REG> TX_DMA_STOPPED_P_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn no_pending(self) -> &'a mut crate::W<REG> {
103        self.variant(TX_DMA_STOPPED_P_A::NO_PENDING)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn pending(self) -> &'a mut crate::W<REG> {
108        self.variant(TX_DMA_STOPPED_P_A::PENDING)
109    }
110}
111#[doc = "Field `tx_buf_ua_p` reader - TX Buffer UA Interrupt Pending"]
112pub type TX_BUF_UA_P_R = crate::BitReader<TX_BUF_UA_P_A>;
113#[doc = "TX Buffer UA Interrupt Pending\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TX_BUF_UA_P_A {
116    #[doc = "0: `0`"]
117    NO_PENDING = 0,
118    #[doc = "1: `1`"]
119    PENDING = 1,
120}
121impl From<TX_BUF_UA_P_A> for bool {
122    #[inline(always)]
123    fn from(variant: TX_BUF_UA_P_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TX_BUF_UA_P_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TX_BUF_UA_P_A {
131        match self.bits {
132            false => TX_BUF_UA_P_A::NO_PENDING,
133            true => TX_BUF_UA_P_A::PENDING,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_no_pending(&self) -> bool {
139        *self == TX_BUF_UA_P_A::NO_PENDING
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_pending(&self) -> bool {
144        *self == TX_BUF_UA_P_A::PENDING
145    }
146}
147#[doc = "Field `tx_buf_ua_p` writer - TX Buffer UA Interrupt Pending"]
148pub type TX_BUF_UA_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_BUF_UA_P_A>;
149impl<'a, REG> TX_BUF_UA_P_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn no_pending(self) -> &'a mut crate::W<REG> {
156        self.variant(TX_BUF_UA_P_A::NO_PENDING)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn pending(self) -> &'a mut crate::W<REG> {
161        self.variant(TX_BUF_UA_P_A::PENDING)
162    }
163}
164#[doc = "Field `tx_timeout_p` reader - Transmitter Timeout Interrupt Pending"]
165pub type TX_TIMEOUT_P_R = crate::BitReader<TX_TIMEOUT_P_A>;
166#[doc = "Transmitter Timeout Interrupt Pending\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum TX_TIMEOUT_P_A {
169    #[doc = "0: `0`"]
170    NO_PENDING = 0,
171    #[doc = "1: `1`"]
172    PENDING = 1,
173}
174impl From<TX_TIMEOUT_P_A> for bool {
175    #[inline(always)]
176    fn from(variant: TX_TIMEOUT_P_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl TX_TIMEOUT_P_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> TX_TIMEOUT_P_A {
184        match self.bits {
185            false => TX_TIMEOUT_P_A::NO_PENDING,
186            true => TX_TIMEOUT_P_A::PENDING,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_no_pending(&self) -> bool {
192        *self == TX_TIMEOUT_P_A::NO_PENDING
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_pending(&self) -> bool {
197        *self == TX_TIMEOUT_P_A::PENDING
198    }
199}
200#[doc = "Field `tx_timeout_p` writer - Transmitter Timeout Interrupt Pending"]
201pub type TX_TIMEOUT_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_TIMEOUT_P_A>;
202impl<'a, REG> TX_TIMEOUT_P_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn no_pending(self) -> &'a mut crate::W<REG> {
209        self.variant(TX_TIMEOUT_P_A::NO_PENDING)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn pending(self) -> &'a mut crate::W<REG> {
214        self.variant(TX_TIMEOUT_P_A::PENDING)
215    }
216}
217#[doc = "Field `tx_underflow_p` reader - TX FIFO Underflow Interrupt Pending"]
218pub type TX_UNDERFLOW_P_R = crate::BitReader<TX_UNDERFLOW_P_A>;
219#[doc = "TX FIFO Underflow Interrupt Pending\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum TX_UNDERFLOW_P_A {
222    #[doc = "0: `0`"]
223    NO_PENDING = 0,
224    #[doc = "1: `1`"]
225    PENDING = 1,
226}
227impl From<TX_UNDERFLOW_P_A> for bool {
228    #[inline(always)]
229    fn from(variant: TX_UNDERFLOW_P_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl TX_UNDERFLOW_P_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> TX_UNDERFLOW_P_A {
237        match self.bits {
238            false => TX_UNDERFLOW_P_A::NO_PENDING,
239            true => TX_UNDERFLOW_P_A::PENDING,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_no_pending(&self) -> bool {
245        *self == TX_UNDERFLOW_P_A::NO_PENDING
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_pending(&self) -> bool {
250        *self == TX_UNDERFLOW_P_A::PENDING
251    }
252}
253#[doc = "Field `tx_underflow_p` writer - TX FIFO Underflow Interrupt Pending"]
254pub type TX_UNDERFLOW_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_UNDERFLOW_P_A>;
255impl<'a, REG> TX_UNDERFLOW_P_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn no_pending(self) -> &'a mut crate::W<REG> {
262        self.variant(TX_UNDERFLOW_P_A::NO_PENDING)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn pending(self) -> &'a mut crate::W<REG> {
267        self.variant(TX_UNDERFLOW_P_A::PENDING)
268    }
269}
270#[doc = "Field `tx_early_p` reader - Total interrupt pending which the frame is transmitted to FIFO"]
271pub type TX_EARLY_P_R = crate::BitReader<TX_EARLY_P_A>;
272#[doc = "Total interrupt pending which the frame is transmitted to FIFO\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum TX_EARLY_P_A {
275    #[doc = "0: `0`"]
276    NO_PENDING = 0,
277    #[doc = "1: `1`"]
278    PENDING = 1,
279}
280impl From<TX_EARLY_P_A> for bool {
281    #[inline(always)]
282    fn from(variant: TX_EARLY_P_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl TX_EARLY_P_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> TX_EARLY_P_A {
290        match self.bits {
291            false => TX_EARLY_P_A::NO_PENDING,
292            true => TX_EARLY_P_A::PENDING,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_no_pending(&self) -> bool {
298        *self == TX_EARLY_P_A::NO_PENDING
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_pending(&self) -> bool {
303        *self == TX_EARLY_P_A::PENDING
304    }
305}
306#[doc = "Field `tx_early_p` writer - Total interrupt pending which the frame is transmitted to FIFO"]
307pub type TX_EARLY_P_W<'a, REG> = crate::BitWriter1C<'a, REG, TX_EARLY_P_A>;
308impl<'a, REG> TX_EARLY_P_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn no_pending(self) -> &'a mut crate::W<REG> {
315        self.variant(TX_EARLY_P_A::NO_PENDING)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn pending(self) -> &'a mut crate::W<REG> {
320        self.variant(TX_EARLY_P_A::PENDING)
321    }
322}
323#[doc = "Field `rx_p` reader - Frame RX Completed Interrupt Pending"]
324pub type RX_P_R = crate::BitReader<RX_P_A>;
325#[doc = "Frame RX Completed Interrupt Pending\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum RX_P_A {
328    #[doc = "0: `0`"]
329    NO_PENDING = 0,
330    #[doc = "1: `1`"]
331    PENDING = 1,
332}
333impl From<RX_P_A> for bool {
334    #[inline(always)]
335    fn from(variant: RX_P_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl RX_P_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> RX_P_A {
343        match self.bits {
344            false => RX_P_A::NO_PENDING,
345            true => RX_P_A::PENDING,
346        }
347    }
348    #[doc = "`0`"]
349    #[inline(always)]
350    pub fn is_no_pending(&self) -> bool {
351        *self == RX_P_A::NO_PENDING
352    }
353    #[doc = "`1`"]
354    #[inline(always)]
355    pub fn is_pending(&self) -> bool {
356        *self == RX_P_A::PENDING
357    }
358}
359#[doc = "Field `rx_p` writer - Frame RX Completed Interrupt Pending"]
360pub type RX_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RX_P_A>;
361impl<'a, REG> RX_P_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "`0`"]
366    #[inline(always)]
367    pub fn no_pending(self) -> &'a mut crate::W<REG> {
368        self.variant(RX_P_A::NO_PENDING)
369    }
370    #[doc = "`1`"]
371    #[inline(always)]
372    pub fn pending(self) -> &'a mut crate::W<REG> {
373        self.variant(RX_P_A::PENDING)
374    }
375}
376#[doc = "Field `rx_buf_ua_p` reader - RX Buffer UA Interrupt Pending"]
377pub type RX_BUF_UA_P_R = crate::BitReader<RX_BUF_UA_P_A>;
378#[doc = "RX Buffer UA Interrupt Pending\n\nValue on reset: 0"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380pub enum RX_BUF_UA_P_A {
381    #[doc = "0: `0`"]
382    NO_PENDING = 0,
383    #[doc = "1: `1`"]
384    PENDING = 1,
385}
386impl From<RX_BUF_UA_P_A> for bool {
387    #[inline(always)]
388    fn from(variant: RX_BUF_UA_P_A) -> Self {
389        variant as u8 != 0
390    }
391}
392impl RX_BUF_UA_P_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> RX_BUF_UA_P_A {
396        match self.bits {
397            false => RX_BUF_UA_P_A::NO_PENDING,
398            true => RX_BUF_UA_P_A::PENDING,
399        }
400    }
401    #[doc = "`0`"]
402    #[inline(always)]
403    pub fn is_no_pending(&self) -> bool {
404        *self == RX_BUF_UA_P_A::NO_PENDING
405    }
406    #[doc = "`1`"]
407    #[inline(always)]
408    pub fn is_pending(&self) -> bool {
409        *self == RX_BUF_UA_P_A::PENDING
410    }
411}
412#[doc = "Field `rx_buf_ua_p` writer - RX Buffer UA Interrupt Pending"]
413pub type RX_BUF_UA_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RX_BUF_UA_P_A>;
414impl<'a, REG> RX_BUF_UA_P_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "`0`"]
419    #[inline(always)]
420    pub fn no_pending(self) -> &'a mut crate::W<REG> {
421        self.variant(RX_BUF_UA_P_A::NO_PENDING)
422    }
423    #[doc = "`1`"]
424    #[inline(always)]
425    pub fn pending(self) -> &'a mut crate::W<REG> {
426        self.variant(RX_BUF_UA_P_A::PENDING)
427    }
428}
429#[doc = "Field `rx_dma_stopped_p` reader - When this bit asserted, the RX DMA FSM is stopped."]
430pub type RX_DMA_STOPPED_P_R = crate::BitReader;
431#[doc = "Field `rx_dma_stopped_p` writer - When this bit asserted, the RX DMA FSM is stopped."]
432pub type RX_DMA_STOPPED_P_W<'a, REG> = crate::BitWriter1C<'a, REG>;
433#[doc = "Field `rx_timeout_p` reader - RX Timeout Interrupt Pending"]
434pub type RX_TIMEOUT_P_R = crate::BitReader<RX_TIMEOUT_P_A>;
435#[doc = "RX Timeout Interrupt Pending\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq, Eq)]
437pub enum RX_TIMEOUT_P_A {
438    #[doc = "0: `0`"]
439    NO_PENDING = 0,
440    #[doc = "1: `1`"]
441    PENDING = 1,
442}
443impl From<RX_TIMEOUT_P_A> for bool {
444    #[inline(always)]
445    fn from(variant: RX_TIMEOUT_P_A) -> Self {
446        variant as u8 != 0
447    }
448}
449impl RX_TIMEOUT_P_R {
450    #[doc = "Get enumerated values variant"]
451    #[inline(always)]
452    pub const fn variant(&self) -> RX_TIMEOUT_P_A {
453        match self.bits {
454            false => RX_TIMEOUT_P_A::NO_PENDING,
455            true => RX_TIMEOUT_P_A::PENDING,
456        }
457    }
458    #[doc = "`0`"]
459    #[inline(always)]
460    pub fn is_no_pending(&self) -> bool {
461        *self == RX_TIMEOUT_P_A::NO_PENDING
462    }
463    #[doc = "`1`"]
464    #[inline(always)]
465    pub fn is_pending(&self) -> bool {
466        *self == RX_TIMEOUT_P_A::PENDING
467    }
468}
469#[doc = "Field `rx_timeout_p` writer - RX Timeout Interrupt Pending"]
470pub type RX_TIMEOUT_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RX_TIMEOUT_P_A>;
471impl<'a, REG> RX_TIMEOUT_P_W<'a, REG>
472where
473    REG: crate::Writable + crate::RegisterSpec,
474{
475    #[doc = "`0`"]
476    #[inline(always)]
477    pub fn no_pending(self) -> &'a mut crate::W<REG> {
478        self.variant(RX_TIMEOUT_P_A::NO_PENDING)
479    }
480    #[doc = "`1`"]
481    #[inline(always)]
482    pub fn pending(self) -> &'a mut crate::W<REG> {
483        self.variant(RX_TIMEOUT_P_A::PENDING)
484    }
485}
486#[doc = "Field `rx_overflow_p` reader - RX FIFO Overflow Error Interrupt Pending"]
487pub type RX_OVERFLOW_P_R = crate::BitReader<RX_OVERFLOW_P_A>;
488#[doc = "RX FIFO Overflow Error Interrupt Pending\n\nValue on reset: 0"]
489#[derive(Clone, Copy, Debug, PartialEq, Eq)]
490pub enum RX_OVERFLOW_P_A {
491    #[doc = "0: `0`"]
492    NO_PENDING = 0,
493    #[doc = "1: `1`"]
494    PENDING = 1,
495}
496impl From<RX_OVERFLOW_P_A> for bool {
497    #[inline(always)]
498    fn from(variant: RX_OVERFLOW_P_A) -> Self {
499        variant as u8 != 0
500    }
501}
502impl RX_OVERFLOW_P_R {
503    #[doc = "Get enumerated values variant"]
504    #[inline(always)]
505    pub const fn variant(&self) -> RX_OVERFLOW_P_A {
506        match self.bits {
507            false => RX_OVERFLOW_P_A::NO_PENDING,
508            true => RX_OVERFLOW_P_A::PENDING,
509        }
510    }
511    #[doc = "`0`"]
512    #[inline(always)]
513    pub fn is_no_pending(&self) -> bool {
514        *self == RX_OVERFLOW_P_A::NO_PENDING
515    }
516    #[doc = "`1`"]
517    #[inline(always)]
518    pub fn is_pending(&self) -> bool {
519        *self == RX_OVERFLOW_P_A::PENDING
520    }
521}
522#[doc = "Field `rx_overflow_p` writer - RX FIFO Overflow Error Interrupt Pending"]
523pub type RX_OVERFLOW_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RX_OVERFLOW_P_A>;
524impl<'a, REG> RX_OVERFLOW_P_W<'a, REG>
525where
526    REG: crate::Writable + crate::RegisterSpec,
527{
528    #[doc = "`0`"]
529    #[inline(always)]
530    pub fn no_pending(self) -> &'a mut crate::W<REG> {
531        self.variant(RX_OVERFLOW_P_A::NO_PENDING)
532    }
533    #[doc = "`1`"]
534    #[inline(always)]
535    pub fn pending(self) -> &'a mut crate::W<REG> {
536        self.variant(RX_OVERFLOW_P_A::PENDING)
537    }
538}
539#[doc = "Field `rx_early_p` reader - RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending"]
540pub type RX_EARLY_P_R = crate::BitReader<RX_EARLY_P_A>;
541#[doc = "RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending\n\nValue on reset: 0"]
542#[derive(Clone, Copy, Debug, PartialEq, Eq)]
543pub enum RX_EARLY_P_A {
544    #[doc = "0: `0`"]
545    NO_PENDING = 0,
546    #[doc = "1: `1`"]
547    PENDING = 1,
548}
549impl From<RX_EARLY_P_A> for bool {
550    #[inline(always)]
551    fn from(variant: RX_EARLY_P_A) -> Self {
552        variant as u8 != 0
553    }
554}
555impl RX_EARLY_P_R {
556    #[doc = "Get enumerated values variant"]
557    #[inline(always)]
558    pub const fn variant(&self) -> RX_EARLY_P_A {
559        match self.bits {
560            false => RX_EARLY_P_A::NO_PENDING,
561            true => RX_EARLY_P_A::PENDING,
562        }
563    }
564    #[doc = "`0`"]
565    #[inline(always)]
566    pub fn is_no_pending(&self) -> bool {
567        *self == RX_EARLY_P_A::NO_PENDING
568    }
569    #[doc = "`1`"]
570    #[inline(always)]
571    pub fn is_pending(&self) -> bool {
572        *self == RX_EARLY_P_A::PENDING
573    }
574}
575#[doc = "Field `rx_early_p` writer - RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending"]
576pub type RX_EARLY_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RX_EARLY_P_A>;
577impl<'a, REG> RX_EARLY_P_W<'a, REG>
578where
579    REG: crate::Writable + crate::RegisterSpec,
580{
581    #[doc = "`0`"]
582    #[inline(always)]
583    pub fn no_pending(self) -> &'a mut crate::W<REG> {
584        self.variant(RX_EARLY_P_A::NO_PENDING)
585    }
586    #[doc = "`1`"]
587    #[inline(always)]
588    pub fn pending(self) -> &'a mut crate::W<REG> {
589        self.variant(RX_EARLY_P_A::PENDING)
590    }
591}
592#[doc = "Field `rgmii_link_sta_p` reader - RMII Link Status Changed Interrupt Pending"]
593pub type RGMII_LINK_STA_P_R = crate::BitReader<RGMII_LINK_STA_P_A>;
594#[doc = "RMII Link Status Changed Interrupt Pending\n\nValue on reset: 0"]
595#[derive(Clone, Copy, Debug, PartialEq, Eq)]
596pub enum RGMII_LINK_STA_P_A {
597    #[doc = "0: `0`"]
598    NO_PENDING = 0,
599    #[doc = "1: `1`"]
600    PENDING = 1,
601}
602impl From<RGMII_LINK_STA_P_A> for bool {
603    #[inline(always)]
604    fn from(variant: RGMII_LINK_STA_P_A) -> Self {
605        variant as u8 != 0
606    }
607}
608impl RGMII_LINK_STA_P_R {
609    #[doc = "Get enumerated values variant"]
610    #[inline(always)]
611    pub const fn variant(&self) -> RGMII_LINK_STA_P_A {
612        match self.bits {
613            false => RGMII_LINK_STA_P_A::NO_PENDING,
614            true => RGMII_LINK_STA_P_A::PENDING,
615        }
616    }
617    #[doc = "`0`"]
618    #[inline(always)]
619    pub fn is_no_pending(&self) -> bool {
620        *self == RGMII_LINK_STA_P_A::NO_PENDING
621    }
622    #[doc = "`1`"]
623    #[inline(always)]
624    pub fn is_pending(&self) -> bool {
625        *self == RGMII_LINK_STA_P_A::PENDING
626    }
627}
628#[doc = "Field `rgmii_link_sta_p` writer - RMII Link Status Changed Interrupt Pending"]
629pub type RGMII_LINK_STA_P_W<'a, REG> = crate::BitWriter1C<'a, REG, RGMII_LINK_STA_P_A>;
630impl<'a, REG> RGMII_LINK_STA_P_W<'a, REG>
631where
632    REG: crate::Writable + crate::RegisterSpec,
633{
634    #[doc = "`0`"]
635    #[inline(always)]
636    pub fn no_pending(self) -> &'a mut crate::W<REG> {
637        self.variant(RGMII_LINK_STA_P_A::NO_PENDING)
638    }
639    #[doc = "`1`"]
640    #[inline(always)]
641    pub fn pending(self) -> &'a mut crate::W<REG> {
642        self.variant(RGMII_LINK_STA_P_A::PENDING)
643    }
644}
645impl R {
646    #[doc = "Bit 0 - Frame Transmission Interrupt Pending"]
647    #[inline(always)]
648    pub fn tx_p(&self) -> TX_P_R {
649        TX_P_R::new((self.bits & 1) != 0)
650    }
651    #[doc = "Bit 1 - Transmission DMA Stopped Interrupt Pending"]
652    #[inline(always)]
653    pub fn tx_dma_stopped_p(&self) -> TX_DMA_STOPPED_P_R {
654        TX_DMA_STOPPED_P_R::new(((self.bits >> 1) & 1) != 0)
655    }
656    #[doc = "Bit 2 - TX Buffer UA Interrupt Pending"]
657    #[inline(always)]
658    pub fn tx_buf_ua_p(&self) -> TX_BUF_UA_P_R {
659        TX_BUF_UA_P_R::new(((self.bits >> 2) & 1) != 0)
660    }
661    #[doc = "Bit 3 - Transmitter Timeout Interrupt Pending"]
662    #[inline(always)]
663    pub fn tx_timeout_p(&self) -> TX_TIMEOUT_P_R {
664        TX_TIMEOUT_P_R::new(((self.bits >> 3) & 1) != 0)
665    }
666    #[doc = "Bit 4 - TX FIFO Underflow Interrupt Pending"]
667    #[inline(always)]
668    pub fn tx_underflow_p(&self) -> TX_UNDERFLOW_P_R {
669        TX_UNDERFLOW_P_R::new(((self.bits >> 4) & 1) != 0)
670    }
671    #[doc = "Bit 5 - Total interrupt pending which the frame is transmitted to FIFO"]
672    #[inline(always)]
673    pub fn tx_early_p(&self) -> TX_EARLY_P_R {
674        TX_EARLY_P_R::new(((self.bits >> 5) & 1) != 0)
675    }
676    #[doc = "Bit 8 - Frame RX Completed Interrupt Pending"]
677    #[inline(always)]
678    pub fn rx_p(&self) -> RX_P_R {
679        RX_P_R::new(((self.bits >> 8) & 1) != 0)
680    }
681    #[doc = "Bit 9 - RX Buffer UA Interrupt Pending"]
682    #[inline(always)]
683    pub fn rx_buf_ua_p(&self) -> RX_BUF_UA_P_R {
684        RX_BUF_UA_P_R::new(((self.bits >> 9) & 1) != 0)
685    }
686    #[doc = "Bit 10 - When this bit asserted, the RX DMA FSM is stopped."]
687    #[inline(always)]
688    pub fn rx_dma_stopped_p(&self) -> RX_DMA_STOPPED_P_R {
689        RX_DMA_STOPPED_P_R::new(((self.bits >> 10) & 1) != 0)
690    }
691    #[doc = "Bit 11 - RX Timeout Interrupt Pending"]
692    #[inline(always)]
693    pub fn rx_timeout_p(&self) -> RX_TIMEOUT_P_R {
694        RX_TIMEOUT_P_R::new(((self.bits >> 11) & 1) != 0)
695    }
696    #[doc = "Bit 12 - RX FIFO Overflow Error Interrupt Pending"]
697    #[inline(always)]
698    pub fn rx_overflow_p(&self) -> RX_OVERFLOW_P_R {
699        RX_OVERFLOW_P_R::new(((self.bits >> 12) & 1) != 0)
700    }
701    #[doc = "Bit 13 - RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending"]
702    #[inline(always)]
703    pub fn rx_early_p(&self) -> RX_EARLY_P_R {
704        RX_EARLY_P_R::new(((self.bits >> 13) & 1) != 0)
705    }
706    #[doc = "Bit 16 - RMII Link Status Changed Interrupt Pending"]
707    #[inline(always)]
708    pub fn rgmii_link_sta_p(&self) -> RGMII_LINK_STA_P_R {
709        RGMII_LINK_STA_P_R::new(((self.bits >> 16) & 1) != 0)
710    }
711}
712impl W {
713    #[doc = "Bit 0 - Frame Transmission Interrupt Pending"]
714    #[inline(always)]
715    #[must_use]
716    pub fn tx_p(&mut self) -> TX_P_W<EMAC_INT_STA_SPEC> {
717        TX_P_W::new(self, 0)
718    }
719    #[doc = "Bit 1 - Transmission DMA Stopped Interrupt Pending"]
720    #[inline(always)]
721    #[must_use]
722    pub fn tx_dma_stopped_p(&mut self) -> TX_DMA_STOPPED_P_W<EMAC_INT_STA_SPEC> {
723        TX_DMA_STOPPED_P_W::new(self, 1)
724    }
725    #[doc = "Bit 2 - TX Buffer UA Interrupt Pending"]
726    #[inline(always)]
727    #[must_use]
728    pub fn tx_buf_ua_p(&mut self) -> TX_BUF_UA_P_W<EMAC_INT_STA_SPEC> {
729        TX_BUF_UA_P_W::new(self, 2)
730    }
731    #[doc = "Bit 3 - Transmitter Timeout Interrupt Pending"]
732    #[inline(always)]
733    #[must_use]
734    pub fn tx_timeout_p(&mut self) -> TX_TIMEOUT_P_W<EMAC_INT_STA_SPEC> {
735        TX_TIMEOUT_P_W::new(self, 3)
736    }
737    #[doc = "Bit 4 - TX FIFO Underflow Interrupt Pending"]
738    #[inline(always)]
739    #[must_use]
740    pub fn tx_underflow_p(&mut self) -> TX_UNDERFLOW_P_W<EMAC_INT_STA_SPEC> {
741        TX_UNDERFLOW_P_W::new(self, 4)
742    }
743    #[doc = "Bit 5 - Total interrupt pending which the frame is transmitted to FIFO"]
744    #[inline(always)]
745    #[must_use]
746    pub fn tx_early_p(&mut self) -> TX_EARLY_P_W<EMAC_INT_STA_SPEC> {
747        TX_EARLY_P_W::new(self, 5)
748    }
749    #[doc = "Bit 8 - Frame RX Completed Interrupt Pending"]
750    #[inline(always)]
751    #[must_use]
752    pub fn rx_p(&mut self) -> RX_P_W<EMAC_INT_STA_SPEC> {
753        RX_P_W::new(self, 8)
754    }
755    #[doc = "Bit 9 - RX Buffer UA Interrupt Pending"]
756    #[inline(always)]
757    #[must_use]
758    pub fn rx_buf_ua_p(&mut self) -> RX_BUF_UA_P_W<EMAC_INT_STA_SPEC> {
759        RX_BUF_UA_P_W::new(self, 9)
760    }
761    #[doc = "Bit 10 - When this bit asserted, the RX DMA FSM is stopped."]
762    #[inline(always)]
763    #[must_use]
764    pub fn rx_dma_stopped_p(&mut self) -> RX_DMA_STOPPED_P_W<EMAC_INT_STA_SPEC> {
765        RX_DMA_STOPPED_P_W::new(self, 10)
766    }
767    #[doc = "Bit 11 - RX Timeout Interrupt Pending"]
768    #[inline(always)]
769    #[must_use]
770    pub fn rx_timeout_p(&mut self) -> RX_TIMEOUT_P_W<EMAC_INT_STA_SPEC> {
771        RX_TIMEOUT_P_W::new(self, 11)
772    }
773    #[doc = "Bit 12 - RX FIFO Overflow Error Interrupt Pending"]
774    #[inline(always)]
775    #[must_use]
776    pub fn rx_overflow_p(&mut self) -> RX_OVERFLOW_P_W<EMAC_INT_STA_SPEC> {
777        RX_OVERFLOW_P_W::new(self, 12)
778    }
779    #[doc = "Bit 13 - RX DMA Filled First Data Buffer of the Receive Frame Interrupt Pending"]
780    #[inline(always)]
781    #[must_use]
782    pub fn rx_early_p(&mut self) -> RX_EARLY_P_W<EMAC_INT_STA_SPEC> {
783        RX_EARLY_P_W::new(self, 13)
784    }
785    #[doc = "Bit 16 - RMII Link Status Changed Interrupt Pending"]
786    #[inline(always)]
787    #[must_use]
788    pub fn rgmii_link_sta_p(&mut self) -> RGMII_LINK_STA_P_W<EMAC_INT_STA_SPEC> {
789        RGMII_LINK_STA_P_W::new(self, 16)
790    }
791    #[doc = r" Writes raw bits to the register."]
792    #[doc = r""]
793    #[doc = r" # Safety"]
794    #[doc = r""]
795    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
796    #[inline(always)]
797    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
798        self.bits = bits;
799        self
800    }
801}
802#[doc = "EMAC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_int_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_int_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
803pub struct EMAC_INT_STA_SPEC;
804impl crate::RegisterSpec for EMAC_INT_STA_SPEC {
805    type Ux = u32;
806}
807#[doc = "`read()` method returns [`emac_int_sta::R`](R) reader structure"]
808impl crate::Readable for EMAC_INT_STA_SPEC {}
809#[doc = "`write(|w| ..)` method takes [`emac_int_sta::W`](W) writer structure"]
810impl crate::Writable for EMAC_INT_STA_SPEC {
811    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
812    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0001_3f3f;
813}
814#[doc = "`reset()` method sets emac_int_sta to value 0"]
815impl crate::Resettable for EMAC_INT_STA_SPEC {
816    const RESET_VALUE: Self::Ux = 0;
817}
d1_pac/emac/emac_int_sta.rs

d1_pac/emac/
emac_int_sta.rs
