d1_pac/emac/
emac_int_en.rs

1#[doc = "Register `emac_int_en` reader"]
2pub type R = crate::R<EMAC_INT_EN_SPEC>;
3#[doc = "Register `emac_int_en` writer"]
4pub type W = crate::W<EMAC_INT_EN_SPEC>;
5#[doc = "Field `tx_int_en` reader - Transmit Interrupt"]
6pub type TX_INT_EN_R = crate::BitReader<TX_INT_EN_A>;
7#[doc = "Transmit Interrupt\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TX_INT_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<TX_INT_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TX_INT_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TX_INT_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TX_INT_EN_A {
25        match self.bits {
26            false => TX_INT_EN_A::DISABLE,
27            true => TX_INT_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TX_INT_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TX_INT_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tx_int_en` writer - Transmit Interrupt"]
42pub type TX_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_INT_EN_A>;
43impl<'a, REG> TX_INT_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TX_INT_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TX_INT_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `tx_dma_stopped_int_en` reader - Transmit DMA FSM Stopped Interrupt"]
59pub type TX_DMA_STOPPED_INT_EN_R = crate::BitReader<TX_DMA_STOPPED_INT_EN_A>;
60#[doc = "Transmit DMA FSM Stopped Interrupt\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TX_DMA_STOPPED_INT_EN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<TX_DMA_STOPPED_INT_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: TX_DMA_STOPPED_INT_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TX_DMA_STOPPED_INT_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TX_DMA_STOPPED_INT_EN_A {
78        match self.bits {
79            false => TX_DMA_STOPPED_INT_EN_A::DISABLE,
80            true => TX_DMA_STOPPED_INT_EN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TX_DMA_STOPPED_INT_EN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TX_DMA_STOPPED_INT_EN_A::ENABLE
92    }
93}
94#[doc = "Field `tx_dma_stopped_int_en` writer - Transmit DMA FSM Stopped Interrupt"]
95pub type TX_DMA_STOPPED_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_DMA_STOPPED_INT_EN_A>;
96impl<'a, REG> TX_DMA_STOPPED_INT_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TX_DMA_STOPPED_INT_EN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TX_DMA_STOPPED_INT_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `tx_buf_ua_int_en` reader - Transmit Buffer Available Interrupt"]
112pub type TX_BUF_UA_INT_EN_R = crate::BitReader<TX_BUF_UA_INT_EN_A>;
113#[doc = "Transmit Buffer Available Interrupt\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TX_BUF_UA_INT_EN_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<TX_BUF_UA_INT_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: TX_BUF_UA_INT_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TX_BUF_UA_INT_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TX_BUF_UA_INT_EN_A {
131        match self.bits {
132            false => TX_BUF_UA_INT_EN_A::DISABLE,
133            true => TX_BUF_UA_INT_EN_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == TX_BUF_UA_INT_EN_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == TX_BUF_UA_INT_EN_A::ENABLE
145    }
146}
147#[doc = "Field `tx_buf_ua_int_en` writer - Transmit Buffer Available Interrupt"]
148pub type TX_BUF_UA_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_BUF_UA_INT_EN_A>;
149impl<'a, REG> TX_BUF_UA_INT_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(TX_BUF_UA_INT_EN_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(TX_BUF_UA_INT_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `tx_timeout_int_en` reader - Transmit Timeout Interrupt"]
165pub type TX_TIMEOUT_INT_EN_R = crate::BitReader<TX_TIMEOUT_INT_EN_A>;
166#[doc = "Transmit Timeout Interrupt\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum TX_TIMEOUT_INT_EN_A {
169    #[doc = "0: `0`"]
170    DISABLE = 0,
171    #[doc = "1: `1`"]
172    ENABLE = 1,
173}
174impl From<TX_TIMEOUT_INT_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: TX_TIMEOUT_INT_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl TX_TIMEOUT_INT_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> TX_TIMEOUT_INT_EN_A {
184        match self.bits {
185            false => TX_TIMEOUT_INT_EN_A::DISABLE,
186            true => TX_TIMEOUT_INT_EN_A::ENABLE,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == TX_TIMEOUT_INT_EN_A::DISABLE
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == TX_TIMEOUT_INT_EN_A::ENABLE
198    }
199}
200#[doc = "Field `tx_timeout_int_en` writer - Transmit Timeout Interrupt"]
201pub type TX_TIMEOUT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_TIMEOUT_INT_EN_A>;
202impl<'a, REG> TX_TIMEOUT_INT_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(TX_TIMEOUT_INT_EN_A::DISABLE)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(TX_TIMEOUT_INT_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `tx_underflow_int_en` reader - Transmit Underflow Interrupt"]
218pub type TX_UNDERFLOW_INT_EN_R = crate::BitReader<TX_UNDERFLOW_INT_EN_A>;
219#[doc = "Transmit Underflow Interrupt\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum TX_UNDERFLOW_INT_EN_A {
222    #[doc = "0: `0`"]
223    DISABLE = 0,
224    #[doc = "1: `1`"]
225    ENABLE = 1,
226}
227impl From<TX_UNDERFLOW_INT_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: TX_UNDERFLOW_INT_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl TX_UNDERFLOW_INT_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> TX_UNDERFLOW_INT_EN_A {
237        match self.bits {
238            false => TX_UNDERFLOW_INT_EN_A::DISABLE,
239            true => TX_UNDERFLOW_INT_EN_A::ENABLE,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_disable(&self) -> bool {
245        *self == TX_UNDERFLOW_INT_EN_A::DISABLE
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == TX_UNDERFLOW_INT_EN_A::ENABLE
251    }
252}
253#[doc = "Field `tx_underflow_int_en` writer - Transmit Underflow Interrupt"]
254pub type TX_UNDERFLOW_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_UNDERFLOW_INT_EN_A>;
255impl<'a, REG> TX_UNDERFLOW_INT_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn disable(self) -> &'a mut crate::W<REG> {
262        self.variant(TX_UNDERFLOW_INT_EN_A::DISABLE)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(TX_UNDERFLOW_INT_EN_A::ENABLE)
268    }
269}
270#[doc = "Field `tx_early_int_en` reader - Early Transmit Interrupt"]
271pub type TX_EARLY_INT_EN_R = crate::BitReader<TX_EARLY_INT_EN_A>;
272#[doc = "Early Transmit Interrupt\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum TX_EARLY_INT_EN_A {
275    #[doc = "0: `0`"]
276    DISABLE = 0,
277    #[doc = "1: `1`"]
278    ENABLE = 1,
279}
280impl From<TX_EARLY_INT_EN_A> for bool {
281    #[inline(always)]
282    fn from(variant: TX_EARLY_INT_EN_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl TX_EARLY_INT_EN_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> TX_EARLY_INT_EN_A {
290        match self.bits {
291            false => TX_EARLY_INT_EN_A::DISABLE,
292            true => TX_EARLY_INT_EN_A::ENABLE,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_disable(&self) -> bool {
298        *self == TX_EARLY_INT_EN_A::DISABLE
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_enable(&self) -> bool {
303        *self == TX_EARLY_INT_EN_A::ENABLE
304    }
305}
306#[doc = "Field `tx_early_int_en` writer - Early Transmit Interrupt"]
307pub type TX_EARLY_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_EARLY_INT_EN_A>;
308impl<'a, REG> TX_EARLY_INT_EN_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn disable(self) -> &'a mut crate::W<REG> {
315        self.variant(TX_EARLY_INT_EN_A::DISABLE)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn enable(self) -> &'a mut crate::W<REG> {
320        self.variant(TX_EARLY_INT_EN_A::ENABLE)
321    }
322}
323#[doc = "Field `rx_int_en` reader - Receive Interrupt"]
324pub type RX_INT_EN_R = crate::BitReader<RX_INT_EN_A>;
325#[doc = "Receive Interrupt\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum RX_INT_EN_A {
328    #[doc = "0: `0`"]
329    DISABLE = 0,
330    #[doc = "1: `1`"]
331    ENABLE = 1,
332}
333impl From<RX_INT_EN_A> for bool {
334    #[inline(always)]
335    fn from(variant: RX_INT_EN_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl RX_INT_EN_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> RX_INT_EN_A {
343        match self.bits {
344            false => RX_INT_EN_A::DISABLE,
345            true => RX_INT_EN_A::ENABLE,
346        }
347    }
348    #[doc = "`0`"]
349    #[inline(always)]
350    pub fn is_disable(&self) -> bool {
351        *self == RX_INT_EN_A::DISABLE
352    }
353    #[doc = "`1`"]
354    #[inline(always)]
355    pub fn is_enable(&self) -> bool {
356        *self == RX_INT_EN_A::ENABLE
357    }
358}
359#[doc = "Field `rx_int_en` writer - Receive Interrupt"]
360pub type RX_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_INT_EN_A>;
361impl<'a, REG> RX_INT_EN_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "`0`"]
366    #[inline(always)]
367    pub fn disable(self) -> &'a mut crate::W<REG> {
368        self.variant(RX_INT_EN_A::DISABLE)
369    }
370    #[doc = "`1`"]
371    #[inline(always)]
372    pub fn enable(self) -> &'a mut crate::W<REG> {
373        self.variant(RX_INT_EN_A::ENABLE)
374    }
375}
376#[doc = "Field `rx_buf_ua_int_en` reader - Receive Buffer Unavailable Interrupt"]
377pub type RX_BUF_UA_INT_EN_R = crate::BitReader<RX_BUF_UA_INT_EN_A>;
378#[doc = "Receive Buffer Unavailable Interrupt\n\nValue on reset: 0"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380pub enum RX_BUF_UA_INT_EN_A {
381    #[doc = "0: `0`"]
382    DISABLE = 0,
383    #[doc = "1: `1`"]
384    ENABLE = 1,
385}
386impl From<RX_BUF_UA_INT_EN_A> for bool {
387    #[inline(always)]
388    fn from(variant: RX_BUF_UA_INT_EN_A) -> Self {
389        variant as u8 != 0
390    }
391}
392impl RX_BUF_UA_INT_EN_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> RX_BUF_UA_INT_EN_A {
396        match self.bits {
397            false => RX_BUF_UA_INT_EN_A::DISABLE,
398            true => RX_BUF_UA_INT_EN_A::ENABLE,
399        }
400    }
401    #[doc = "`0`"]
402    #[inline(always)]
403    pub fn is_disable(&self) -> bool {
404        *self == RX_BUF_UA_INT_EN_A::DISABLE
405    }
406    #[doc = "`1`"]
407    #[inline(always)]
408    pub fn is_enable(&self) -> bool {
409        *self == RX_BUF_UA_INT_EN_A::ENABLE
410    }
411}
412#[doc = "Field `rx_buf_ua_int_en` writer - Receive Buffer Unavailable Interrupt"]
413pub type RX_BUF_UA_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_BUF_UA_INT_EN_A>;
414impl<'a, REG> RX_BUF_UA_INT_EN_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "`0`"]
419    #[inline(always)]
420    pub fn disable(self) -> &'a mut crate::W<REG> {
421        self.variant(RX_BUF_UA_INT_EN_A::DISABLE)
422    }
423    #[doc = "`1`"]
424    #[inline(always)]
425    pub fn enable(self) -> &'a mut crate::W<REG> {
426        self.variant(RX_BUF_UA_INT_EN_A::ENABLE)
427    }
428}
429#[doc = "Field `rx_dma_stopped_int_en` reader - Receive DMA FSM Stopped Interrupt"]
430pub type RX_DMA_STOPPED_INT_EN_R = crate::BitReader<RX_DMA_STOPPED_INT_EN_A>;
431#[doc = "Receive DMA FSM Stopped Interrupt\n\nValue on reset: 0"]
432#[derive(Clone, Copy, Debug, PartialEq, Eq)]
433pub enum RX_DMA_STOPPED_INT_EN_A {
434    #[doc = "0: `0`"]
435    DISABLE = 0,
436    #[doc = "1: `1`"]
437    ENABLE = 1,
438}
439impl From<RX_DMA_STOPPED_INT_EN_A> for bool {
440    #[inline(always)]
441    fn from(variant: RX_DMA_STOPPED_INT_EN_A) -> Self {
442        variant as u8 != 0
443    }
444}
445impl RX_DMA_STOPPED_INT_EN_R {
446    #[doc = "Get enumerated values variant"]
447    #[inline(always)]
448    pub const fn variant(&self) -> RX_DMA_STOPPED_INT_EN_A {
449        match self.bits {
450            false => RX_DMA_STOPPED_INT_EN_A::DISABLE,
451            true => RX_DMA_STOPPED_INT_EN_A::ENABLE,
452        }
453    }
454    #[doc = "`0`"]
455    #[inline(always)]
456    pub fn is_disable(&self) -> bool {
457        *self == RX_DMA_STOPPED_INT_EN_A::DISABLE
458    }
459    #[doc = "`1`"]
460    #[inline(always)]
461    pub fn is_enable(&self) -> bool {
462        *self == RX_DMA_STOPPED_INT_EN_A::ENABLE
463    }
464}
465#[doc = "Field `rx_dma_stopped_int_en` writer - Receive DMA FSM Stopped Interrupt"]
466pub type RX_DMA_STOPPED_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_DMA_STOPPED_INT_EN_A>;
467impl<'a, REG> RX_DMA_STOPPED_INT_EN_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    #[doc = "`0`"]
472    #[inline(always)]
473    pub fn disable(self) -> &'a mut crate::W<REG> {
474        self.variant(RX_DMA_STOPPED_INT_EN_A::DISABLE)
475    }
476    #[doc = "`1`"]
477    #[inline(always)]
478    pub fn enable(self) -> &'a mut crate::W<REG> {
479        self.variant(RX_DMA_STOPPED_INT_EN_A::ENABLE)
480    }
481}
482#[doc = "Field `rx_timeout_int_en` reader - Receive Timeout Interrupt"]
483pub type RX_TIMEOUT_INT_EN_R = crate::BitReader<RX_TIMEOUT_INT_EN_A>;
484#[doc = "Receive Timeout Interrupt\n\nValue on reset: 0"]
485#[derive(Clone, Copy, Debug, PartialEq, Eq)]
486pub enum RX_TIMEOUT_INT_EN_A {
487    #[doc = "0: `0`"]
488    DISABLE = 0,
489    #[doc = "1: `1`"]
490    ENABLE = 1,
491}
492impl From<RX_TIMEOUT_INT_EN_A> for bool {
493    #[inline(always)]
494    fn from(variant: RX_TIMEOUT_INT_EN_A) -> Self {
495        variant as u8 != 0
496    }
497}
498impl RX_TIMEOUT_INT_EN_R {
499    #[doc = "Get enumerated values variant"]
500    #[inline(always)]
501    pub const fn variant(&self) -> RX_TIMEOUT_INT_EN_A {
502        match self.bits {
503            false => RX_TIMEOUT_INT_EN_A::DISABLE,
504            true => RX_TIMEOUT_INT_EN_A::ENABLE,
505        }
506    }
507    #[doc = "`0`"]
508    #[inline(always)]
509    pub fn is_disable(&self) -> bool {
510        *self == RX_TIMEOUT_INT_EN_A::DISABLE
511    }
512    #[doc = "`1`"]
513    #[inline(always)]
514    pub fn is_enable(&self) -> bool {
515        *self == RX_TIMEOUT_INT_EN_A::ENABLE
516    }
517}
518#[doc = "Field `rx_timeout_int_en` writer - Receive Timeout Interrupt"]
519pub type RX_TIMEOUT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_TIMEOUT_INT_EN_A>;
520impl<'a, REG> RX_TIMEOUT_INT_EN_W<'a, REG>
521where
522    REG: crate::Writable + crate::RegisterSpec,
523{
524    #[doc = "`0`"]
525    #[inline(always)]
526    pub fn disable(self) -> &'a mut crate::W<REG> {
527        self.variant(RX_TIMEOUT_INT_EN_A::DISABLE)
528    }
529    #[doc = "`1`"]
530    #[inline(always)]
531    pub fn enable(self) -> &'a mut crate::W<REG> {
532        self.variant(RX_TIMEOUT_INT_EN_A::ENABLE)
533    }
534}
535#[doc = "Field `rx_overflow_int_en` reader - Receive Overflow Interrupt"]
536pub type RX_OVERFLOW_INT_EN_R = crate::BitReader<RX_OVERFLOW_INT_EN_A>;
537#[doc = "Receive Overflow Interrupt\n\nValue on reset: 0"]
538#[derive(Clone, Copy, Debug, PartialEq, Eq)]
539pub enum RX_OVERFLOW_INT_EN_A {
540    #[doc = "0: `0`"]
541    DISABLE = 0,
542    #[doc = "1: `1`"]
543    ENABLE = 1,
544}
545impl From<RX_OVERFLOW_INT_EN_A> for bool {
546    #[inline(always)]
547    fn from(variant: RX_OVERFLOW_INT_EN_A) -> Self {
548        variant as u8 != 0
549    }
550}
551impl RX_OVERFLOW_INT_EN_R {
552    #[doc = "Get enumerated values variant"]
553    #[inline(always)]
554    pub const fn variant(&self) -> RX_OVERFLOW_INT_EN_A {
555        match self.bits {
556            false => RX_OVERFLOW_INT_EN_A::DISABLE,
557            true => RX_OVERFLOW_INT_EN_A::ENABLE,
558        }
559    }
560    #[doc = "`0`"]
561    #[inline(always)]
562    pub fn is_disable(&self) -> bool {
563        *self == RX_OVERFLOW_INT_EN_A::DISABLE
564    }
565    #[doc = "`1`"]
566    #[inline(always)]
567    pub fn is_enable(&self) -> bool {
568        *self == RX_OVERFLOW_INT_EN_A::ENABLE
569    }
570}
571#[doc = "Field `rx_overflow_int_en` writer - Receive Overflow Interrupt"]
572pub type RX_OVERFLOW_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_OVERFLOW_INT_EN_A>;
573impl<'a, REG> RX_OVERFLOW_INT_EN_W<'a, REG>
574where
575    REG: crate::Writable + crate::RegisterSpec,
576{
577    #[doc = "`0`"]
578    #[inline(always)]
579    pub fn disable(self) -> &'a mut crate::W<REG> {
580        self.variant(RX_OVERFLOW_INT_EN_A::DISABLE)
581    }
582    #[doc = "`1`"]
583    #[inline(always)]
584    pub fn enable(self) -> &'a mut crate::W<REG> {
585        self.variant(RX_OVERFLOW_INT_EN_A::ENABLE)
586    }
587}
588#[doc = "Field `rx_early_int_en` reader - Early Receive Interrupt"]
589pub type RX_EARLY_INT_EN_R = crate::BitReader<RX_EARLY_INT_EN_A>;
590#[doc = "Early Receive Interrupt\n\nValue on reset: 0"]
591#[derive(Clone, Copy, Debug, PartialEq, Eq)]
592pub enum RX_EARLY_INT_EN_A {
593    #[doc = "0: `0`"]
594    DISABLE = 0,
595    #[doc = "1: `1`"]
596    ENABLE = 1,
597}
598impl From<RX_EARLY_INT_EN_A> for bool {
599    #[inline(always)]
600    fn from(variant: RX_EARLY_INT_EN_A) -> Self {
601        variant as u8 != 0
602    }
603}
604impl RX_EARLY_INT_EN_R {
605    #[doc = "Get enumerated values variant"]
606    #[inline(always)]
607    pub const fn variant(&self) -> RX_EARLY_INT_EN_A {
608        match self.bits {
609            false => RX_EARLY_INT_EN_A::DISABLE,
610            true => RX_EARLY_INT_EN_A::ENABLE,
611        }
612    }
613    #[doc = "`0`"]
614    #[inline(always)]
615    pub fn is_disable(&self) -> bool {
616        *self == RX_EARLY_INT_EN_A::DISABLE
617    }
618    #[doc = "`1`"]
619    #[inline(always)]
620    pub fn is_enable(&self) -> bool {
621        *self == RX_EARLY_INT_EN_A::ENABLE
622    }
623}
624#[doc = "Field `rx_early_int_en` writer - Early Receive Interrupt"]
625pub type RX_EARLY_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_EARLY_INT_EN_A>;
626impl<'a, REG> RX_EARLY_INT_EN_W<'a, REG>
627where
628    REG: crate::Writable + crate::RegisterSpec,
629{
630    #[doc = "`0`"]
631    #[inline(always)]
632    pub fn disable(self) -> &'a mut crate::W<REG> {
633        self.variant(RX_EARLY_INT_EN_A::DISABLE)
634    }
635    #[doc = "`1`"]
636    #[inline(always)]
637    pub fn enable(self) -> &'a mut crate::W<REG> {
638        self.variant(RX_EARLY_INT_EN_A::ENABLE)
639    }
640}
641impl R {
642    #[doc = "Bit 0 - Transmit Interrupt"]
643    #[inline(always)]
644    pub fn tx_int_en(&self) -> TX_INT_EN_R {
645        TX_INT_EN_R::new((self.bits & 1) != 0)
646    }
647    #[doc = "Bit 1 - Transmit DMA FSM Stopped Interrupt"]
648    #[inline(always)]
649    pub fn tx_dma_stopped_int_en(&self) -> TX_DMA_STOPPED_INT_EN_R {
650        TX_DMA_STOPPED_INT_EN_R::new(((self.bits >> 1) & 1) != 0)
651    }
652    #[doc = "Bit 2 - Transmit Buffer Available Interrupt"]
653    #[inline(always)]
654    pub fn tx_buf_ua_int_en(&self) -> TX_BUF_UA_INT_EN_R {
655        TX_BUF_UA_INT_EN_R::new(((self.bits >> 2) & 1) != 0)
656    }
657    #[doc = "Bit 3 - Transmit Timeout Interrupt"]
658    #[inline(always)]
659    pub fn tx_timeout_int_en(&self) -> TX_TIMEOUT_INT_EN_R {
660        TX_TIMEOUT_INT_EN_R::new(((self.bits >> 3) & 1) != 0)
661    }
662    #[doc = "Bit 4 - Transmit Underflow Interrupt"]
663    #[inline(always)]
664    pub fn tx_underflow_int_en(&self) -> TX_UNDERFLOW_INT_EN_R {
665        TX_UNDERFLOW_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
666    }
667    #[doc = "Bit 5 - Early Transmit Interrupt"]
668    #[inline(always)]
669    pub fn tx_early_int_en(&self) -> TX_EARLY_INT_EN_R {
670        TX_EARLY_INT_EN_R::new(((self.bits >> 5) & 1) != 0)
671    }
672    #[doc = "Bit 8 - Receive Interrupt"]
673    #[inline(always)]
674    pub fn rx_int_en(&self) -> RX_INT_EN_R {
675        RX_INT_EN_R::new(((self.bits >> 8) & 1) != 0)
676    }
677    #[doc = "Bit 9 - Receive Buffer Unavailable Interrupt"]
678    #[inline(always)]
679    pub fn rx_buf_ua_int_en(&self) -> RX_BUF_UA_INT_EN_R {
680        RX_BUF_UA_INT_EN_R::new(((self.bits >> 9) & 1) != 0)
681    }
682    #[doc = "Bit 10 - Receive DMA FSM Stopped Interrupt"]
683    #[inline(always)]
684    pub fn rx_dma_stopped_int_en(&self) -> RX_DMA_STOPPED_INT_EN_R {
685        RX_DMA_STOPPED_INT_EN_R::new(((self.bits >> 10) & 1) != 0)
686    }
687    #[doc = "Bit 11 - Receive Timeout Interrupt"]
688    #[inline(always)]
689    pub fn rx_timeout_int_en(&self) -> RX_TIMEOUT_INT_EN_R {
690        RX_TIMEOUT_INT_EN_R::new(((self.bits >> 11) & 1) != 0)
691    }
692    #[doc = "Bit 12 - Receive Overflow Interrupt"]
693    #[inline(always)]
694    pub fn rx_overflow_int_en(&self) -> RX_OVERFLOW_INT_EN_R {
695        RX_OVERFLOW_INT_EN_R::new(((self.bits >> 12) & 1) != 0)
696    }
697    #[doc = "Bit 13 - Early Receive Interrupt"]
698    #[inline(always)]
699    pub fn rx_early_int_en(&self) -> RX_EARLY_INT_EN_R {
700        RX_EARLY_INT_EN_R::new(((self.bits >> 13) & 1) != 0)
701    }
702}
703impl W {
704    #[doc = "Bit 0 - Transmit Interrupt"]
705    #[inline(always)]
706    #[must_use]
707    pub fn tx_int_en(&mut self) -> TX_INT_EN_W<EMAC_INT_EN_SPEC> {
708        TX_INT_EN_W::new(self, 0)
709    }
710    #[doc = "Bit 1 - Transmit DMA FSM Stopped Interrupt"]
711    #[inline(always)]
712    #[must_use]
713    pub fn tx_dma_stopped_int_en(&mut self) -> TX_DMA_STOPPED_INT_EN_W<EMAC_INT_EN_SPEC> {
714        TX_DMA_STOPPED_INT_EN_W::new(self, 1)
715    }
716    #[doc = "Bit 2 - Transmit Buffer Available Interrupt"]
717    #[inline(always)]
718    #[must_use]
719    pub fn tx_buf_ua_int_en(&mut self) -> TX_BUF_UA_INT_EN_W<EMAC_INT_EN_SPEC> {
720        TX_BUF_UA_INT_EN_W::new(self, 2)
721    }
722    #[doc = "Bit 3 - Transmit Timeout Interrupt"]
723    #[inline(always)]
724    #[must_use]
725    pub fn tx_timeout_int_en(&mut self) -> TX_TIMEOUT_INT_EN_W<EMAC_INT_EN_SPEC> {
726        TX_TIMEOUT_INT_EN_W::new(self, 3)
727    }
728    #[doc = "Bit 4 - Transmit Underflow Interrupt"]
729    #[inline(always)]
730    #[must_use]
731    pub fn tx_underflow_int_en(&mut self) -> TX_UNDERFLOW_INT_EN_W<EMAC_INT_EN_SPEC> {
732        TX_UNDERFLOW_INT_EN_W::new(self, 4)
733    }
734    #[doc = "Bit 5 - Early Transmit Interrupt"]
735    #[inline(always)]
736    #[must_use]
737    pub fn tx_early_int_en(&mut self) -> TX_EARLY_INT_EN_W<EMAC_INT_EN_SPEC> {
738        TX_EARLY_INT_EN_W::new(self, 5)
739    }
740    #[doc = "Bit 8 - Receive Interrupt"]
741    #[inline(always)]
742    #[must_use]
743    pub fn rx_int_en(&mut self) -> RX_INT_EN_W<EMAC_INT_EN_SPEC> {
744        RX_INT_EN_W::new(self, 8)
745    }
746    #[doc = "Bit 9 - Receive Buffer Unavailable Interrupt"]
747    #[inline(always)]
748    #[must_use]
749    pub fn rx_buf_ua_int_en(&mut self) -> RX_BUF_UA_INT_EN_W<EMAC_INT_EN_SPEC> {
750        RX_BUF_UA_INT_EN_W::new(self, 9)
751    }
752    #[doc = "Bit 10 - Receive DMA FSM Stopped Interrupt"]
753    #[inline(always)]
754    #[must_use]
755    pub fn rx_dma_stopped_int_en(&mut self) -> RX_DMA_STOPPED_INT_EN_W<EMAC_INT_EN_SPEC> {
756        RX_DMA_STOPPED_INT_EN_W::new(self, 10)
757    }
758    #[doc = "Bit 11 - Receive Timeout Interrupt"]
759    #[inline(always)]
760    #[must_use]
761    pub fn rx_timeout_int_en(&mut self) -> RX_TIMEOUT_INT_EN_W<EMAC_INT_EN_SPEC> {
762        RX_TIMEOUT_INT_EN_W::new(self, 11)
763    }
764    #[doc = "Bit 12 - Receive Overflow Interrupt"]
765    #[inline(always)]
766    #[must_use]
767    pub fn rx_overflow_int_en(&mut self) -> RX_OVERFLOW_INT_EN_W<EMAC_INT_EN_SPEC> {
768        RX_OVERFLOW_INT_EN_W::new(self, 12)
769    }
770    #[doc = "Bit 13 - Early Receive Interrupt"]
771    #[inline(always)]
772    #[must_use]
773    pub fn rx_early_int_en(&mut self) -> RX_EARLY_INT_EN_W<EMAC_INT_EN_SPEC> {
774        RX_EARLY_INT_EN_W::new(self, 13)
775    }
776    #[doc = r" Writes raw bits to the register."]
777    #[doc = r""]
778    #[doc = r" # Safety"]
779    #[doc = r""]
780    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
781    #[inline(always)]
782    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
783        self.bits = bits;
784        self
785    }
786}
787#[doc = "EMAC Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
788pub struct EMAC_INT_EN_SPEC;
789impl crate::RegisterSpec for EMAC_INT_EN_SPEC {
790    type Ux = u32;
791}
792#[doc = "`read()` method returns [`emac_int_en::R`](R) reader structure"]
793impl crate::Readable for EMAC_INT_EN_SPEC {}
794#[doc = "`write(|w| ..)` method takes [`emac_int_en::W`](W) writer structure"]
795impl crate::Writable for EMAC_INT_EN_SPEC {
796    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
797    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
798}
799#[doc = "`reset()` method sets emac_int_en to value 0"]
800impl crate::Resettable for EMAC_INT_EN_SPEC {
801    const RESET_VALUE: Self::Ux = 0;
802}
d1_pac/emac/emac_int_en.rs

d1_pac/emac/
emac_int_en.rs
