d1_pac/dmac/
dmac_para.rs

1#[doc = "Register `dmac_para%s` reader"]
2pub type R = crate::R<DMAC_PARA_SPEC>;
3#[doc = "Field `wait_cyc` reader - Wait Clock Cycle"]
4pub type WAIT_CYC_R = crate::FieldReader;
5impl R {
6    #[doc = "Bits 0:7 - Wait Clock Cycle"]
7    #[inline(always)]
8    pub fn wait_cyc(&self) -> WAIT_CYC_R {
9        WAIT_CYC_R::new((self.bits & 0xff) as u8)
10    }
11}
12#[doc = "DMAC Channel Parameter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_para::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13pub struct DMAC_PARA_SPEC;
14impl crate::RegisterSpec for DMAC_PARA_SPEC {
15    type Ux = u32;
16}
17#[doc = "`read()` method returns [`dmac_para::R`](R) reader structure"]
18impl crate::Readable for DMAC_PARA_SPEC {}
19#[doc = "`reset()` method sets dmac_para%s to value 0"]
20impl crate::Resettable for DMAC_PARA_SPEC {
21    const RESET_VALUE: Self::Ux = 0;
22}
d1_pac/dmac/dmac_para.rs

d1_pac/dmac/
dmac_para.rs
