d1_pac/dmac/
dmac_cfg.rs

1#[doc = "Register `dmac_cfg%s` reader"]
2pub type R = crate::R<DMAC_CFG_SPEC>;
3#[doc = "Field `dma_src_drq_type` reader - DMA Source DRQ Type"]
4pub type DMA_SRC_DRQ_TYPE_R = crate::FieldReader;
5#[doc = "Field `dma_src_block_size` reader - DMA Source Block Size"]
6pub type DMA_SRC_BLOCK_SIZE_R = crate::FieldReader<DMA_SRC_BLOCK_SIZE_A>;
7#[doc = "DMA Source Block Size\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum DMA_SRC_BLOCK_SIZE_A {
11    #[doc = "0: `0`"]
12    S1 = 0,
13    #[doc = "1: `1`"]
14    S4 = 1,
15    #[doc = "2: `10`"]
16    S8 = 2,
17    #[doc = "3: `11`"]
18    S16 = 3,
19}
20impl From<DMA_SRC_BLOCK_SIZE_A> for u8 {
21    #[inline(always)]
22    fn from(variant: DMA_SRC_BLOCK_SIZE_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for DMA_SRC_BLOCK_SIZE_A {
27    type Ux = u8;
28}
29impl DMA_SRC_BLOCK_SIZE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> DMA_SRC_BLOCK_SIZE_A {
33        match self.bits {
34            0 => DMA_SRC_BLOCK_SIZE_A::S1,
35            1 => DMA_SRC_BLOCK_SIZE_A::S4,
36            2 => DMA_SRC_BLOCK_SIZE_A::S8,
37            3 => DMA_SRC_BLOCK_SIZE_A::S16,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "`0`"]
42    #[inline(always)]
43    pub fn is_s1(&self) -> bool {
44        *self == DMA_SRC_BLOCK_SIZE_A::S1
45    }
46    #[doc = "`1`"]
47    #[inline(always)]
48    pub fn is_s4(&self) -> bool {
49        *self == DMA_SRC_BLOCK_SIZE_A::S4
50    }
51    #[doc = "`10`"]
52    #[inline(always)]
53    pub fn is_s8(&self) -> bool {
54        *self == DMA_SRC_BLOCK_SIZE_A::S8
55    }
56    #[doc = "`11`"]
57    #[inline(always)]
58    pub fn is_s16(&self) -> bool {
59        *self == DMA_SRC_BLOCK_SIZE_A::S16
60    }
61}
62#[doc = "Field `dma_src_addr_mode` reader - DMA Source Address Mode"]
63pub type DMA_SRC_ADDR_MODE_R = crate::BitReader<DMA_SRC_ADDR_MODE_A>;
64#[doc = "DMA Source Address Mode\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum DMA_SRC_ADDR_MODE_A {
67    #[doc = "0: `0`"]
68    LINEAR = 0,
69    #[doc = "1: `1`"]
70    IO = 1,
71}
72impl From<DMA_SRC_ADDR_MODE_A> for bool {
73    #[inline(always)]
74    fn from(variant: DMA_SRC_ADDR_MODE_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl DMA_SRC_ADDR_MODE_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> DMA_SRC_ADDR_MODE_A {
82        match self.bits {
83            false => DMA_SRC_ADDR_MODE_A::LINEAR,
84            true => DMA_SRC_ADDR_MODE_A::IO,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_linear(&self) -> bool {
90        *self == DMA_SRC_ADDR_MODE_A::LINEAR
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_io(&self) -> bool {
95        *self == DMA_SRC_ADDR_MODE_A::IO
96    }
97}
98#[doc = "Field `dma_src_data_width` reader - DMA Source Data Width"]
99pub type DMA_SRC_DATA_WIDTH_R = crate::FieldReader<DMA_SRC_DATA_WIDTH_A>;
100#[doc = "DMA Source Data Width\n\nValue on reset: 0"]
101#[derive(Clone, Copy, Debug, PartialEq, Eq)]
102#[repr(u8)]
103pub enum DMA_SRC_DATA_WIDTH_A {
104    #[doc = "0: 8 bit"]
105    B8 = 0,
106    #[doc = "1: 16 bit"]
107    B16 = 1,
108    #[doc = "2: 32 bit"]
109    B32 = 2,
110    #[doc = "3: 64 bit"]
111    B64 = 3,
112}
113impl From<DMA_SRC_DATA_WIDTH_A> for u8 {
114    #[inline(always)]
115    fn from(variant: DMA_SRC_DATA_WIDTH_A) -> Self {
116        variant as _
117    }
118}
119impl crate::FieldSpec for DMA_SRC_DATA_WIDTH_A {
120    type Ux = u8;
121}
122impl DMA_SRC_DATA_WIDTH_R {
123    #[doc = "Get enumerated values variant"]
124    #[inline(always)]
125    pub const fn variant(&self) -> DMA_SRC_DATA_WIDTH_A {
126        match self.bits {
127            0 => DMA_SRC_DATA_WIDTH_A::B8,
128            1 => DMA_SRC_DATA_WIDTH_A::B16,
129            2 => DMA_SRC_DATA_WIDTH_A::B32,
130            3 => DMA_SRC_DATA_WIDTH_A::B64,
131            _ => unreachable!(),
132        }
133    }
134    #[doc = "8 bit"]
135    #[inline(always)]
136    pub fn is_b8(&self) -> bool {
137        *self == DMA_SRC_DATA_WIDTH_A::B8
138    }
139    #[doc = "16 bit"]
140    #[inline(always)]
141    pub fn is_b16(&self) -> bool {
142        *self == DMA_SRC_DATA_WIDTH_A::B16
143    }
144    #[doc = "32 bit"]
145    #[inline(always)]
146    pub fn is_b32(&self) -> bool {
147        *self == DMA_SRC_DATA_WIDTH_A::B32
148    }
149    #[doc = "64 bit"]
150    #[inline(always)]
151    pub fn is_b64(&self) -> bool {
152        *self == DMA_SRC_DATA_WIDTH_A::B64
153    }
154}
155#[doc = "Field `dma_dest_drq_type` reader - DMA Destination DRQ Type"]
156pub type DMA_DEST_DRQ_TYPE_R = crate::FieldReader;
157#[doc = "Field `dma_dest_block_size` reader - DMA Destination Block Size"]
158pub type DMA_DEST_BLOCK_SIZE_R = crate::FieldReader<DMA_DEST_BLOCK_SIZE_A>;
159#[doc = "DMA Destination Block Size\n\nValue on reset: 0"]
160#[derive(Clone, Copy, Debug, PartialEq, Eq)]
161#[repr(u8)]
162pub enum DMA_DEST_BLOCK_SIZE_A {
163    #[doc = "0: `0`"]
164    S1 = 0,
165    #[doc = "1: `1`"]
166    S4 = 1,
167    #[doc = "2: `10`"]
168    S8 = 2,
169    #[doc = "3: `11`"]
170    S16 = 3,
171}
172impl From<DMA_DEST_BLOCK_SIZE_A> for u8 {
173    #[inline(always)]
174    fn from(variant: DMA_DEST_BLOCK_SIZE_A) -> Self {
175        variant as _
176    }
177}
178impl crate::FieldSpec for DMA_DEST_BLOCK_SIZE_A {
179    type Ux = u8;
180}
181impl DMA_DEST_BLOCK_SIZE_R {
182    #[doc = "Get enumerated values variant"]
183    #[inline(always)]
184    pub const fn variant(&self) -> DMA_DEST_BLOCK_SIZE_A {
185        match self.bits {
186            0 => DMA_DEST_BLOCK_SIZE_A::S1,
187            1 => DMA_DEST_BLOCK_SIZE_A::S4,
188            2 => DMA_DEST_BLOCK_SIZE_A::S8,
189            3 => DMA_DEST_BLOCK_SIZE_A::S16,
190            _ => unreachable!(),
191        }
192    }
193    #[doc = "`0`"]
194    #[inline(always)]
195    pub fn is_s1(&self) -> bool {
196        *self == DMA_DEST_BLOCK_SIZE_A::S1
197    }
198    #[doc = "`1`"]
199    #[inline(always)]
200    pub fn is_s4(&self) -> bool {
201        *self == DMA_DEST_BLOCK_SIZE_A::S4
202    }
203    #[doc = "`10`"]
204    #[inline(always)]
205    pub fn is_s8(&self) -> bool {
206        *self == DMA_DEST_BLOCK_SIZE_A::S8
207    }
208    #[doc = "`11`"]
209    #[inline(always)]
210    pub fn is_s16(&self) -> bool {
211        *self == DMA_DEST_BLOCK_SIZE_A::S16
212    }
213}
214#[doc = "Field `dma_addr_mode` reader - DMA Destination Address Mode"]
215pub type DMA_ADDR_MODE_R = crate::BitReader<DMA_ADDR_MODE_A>;
216#[doc = "DMA Destination Address Mode\n\nValue on reset: 0"]
217#[derive(Clone, Copy, Debug, PartialEq, Eq)]
218pub enum DMA_ADDR_MODE_A {
219    #[doc = "0: `0`"]
220    LINEAR = 0,
221    #[doc = "1: `1`"]
222    IO = 1,
223}
224impl From<DMA_ADDR_MODE_A> for bool {
225    #[inline(always)]
226    fn from(variant: DMA_ADDR_MODE_A) -> Self {
227        variant as u8 != 0
228    }
229}
230impl DMA_ADDR_MODE_R {
231    #[doc = "Get enumerated values variant"]
232    #[inline(always)]
233    pub const fn variant(&self) -> DMA_ADDR_MODE_A {
234        match self.bits {
235            false => DMA_ADDR_MODE_A::LINEAR,
236            true => DMA_ADDR_MODE_A::IO,
237        }
238    }
239    #[doc = "`0`"]
240    #[inline(always)]
241    pub fn is_linear(&self) -> bool {
242        *self == DMA_ADDR_MODE_A::LINEAR
243    }
244    #[doc = "`1`"]
245    #[inline(always)]
246    pub fn is_io(&self) -> bool {
247        *self == DMA_ADDR_MODE_A::IO
248    }
249}
250#[doc = "Field `dma_dest_data_width` reader - DMA Destination Data Width"]
251pub type DMA_DEST_DATA_WIDTH_R = crate::FieldReader<DMA_DEST_DATA_WIDTH_A>;
252#[doc = "DMA Destination Data Width\n\nValue on reset: 0"]
253#[derive(Clone, Copy, Debug, PartialEq, Eq)]
254#[repr(u8)]
255pub enum DMA_DEST_DATA_WIDTH_A {
256    #[doc = "0: 8 bit"]
257    B8 = 0,
258    #[doc = "1: 16 bit"]
259    B16 = 1,
260    #[doc = "2: 32 bit"]
261    B32 = 2,
262    #[doc = "3: 64 bit"]
263    B64 = 3,
264}
265impl From<DMA_DEST_DATA_WIDTH_A> for u8 {
266    #[inline(always)]
267    fn from(variant: DMA_DEST_DATA_WIDTH_A) -> Self {
268        variant as _
269    }
270}
271impl crate::FieldSpec for DMA_DEST_DATA_WIDTH_A {
272    type Ux = u8;
273}
274impl DMA_DEST_DATA_WIDTH_R {
275    #[doc = "Get enumerated values variant"]
276    #[inline(always)]
277    pub const fn variant(&self) -> DMA_DEST_DATA_WIDTH_A {
278        match self.bits {
279            0 => DMA_DEST_DATA_WIDTH_A::B8,
280            1 => DMA_DEST_DATA_WIDTH_A::B16,
281            2 => DMA_DEST_DATA_WIDTH_A::B32,
282            3 => DMA_DEST_DATA_WIDTH_A::B64,
283            _ => unreachable!(),
284        }
285    }
286    #[doc = "8 bit"]
287    #[inline(always)]
288    pub fn is_b8(&self) -> bool {
289        *self == DMA_DEST_DATA_WIDTH_A::B8
290    }
291    #[doc = "16 bit"]
292    #[inline(always)]
293    pub fn is_b16(&self) -> bool {
294        *self == DMA_DEST_DATA_WIDTH_A::B16
295    }
296    #[doc = "32 bit"]
297    #[inline(always)]
298    pub fn is_b32(&self) -> bool {
299        *self == DMA_DEST_DATA_WIDTH_A::B32
300    }
301    #[doc = "64 bit"]
302    #[inline(always)]
303    pub fn is_b64(&self) -> bool {
304        *self == DMA_DEST_DATA_WIDTH_A::B64
305    }
306}
307#[doc = "Field `bmode_sel` reader - "]
308pub type BMODE_SEL_R = crate::BitReader<BMODE_SEL_A>;
309#[doc = "\n\nValue on reset: 0"]
310#[derive(Clone, Copy, Debug, PartialEq, Eq)]
311pub enum BMODE_SEL_A {
312    #[doc = "0: `0`"]
313    NORMAL = 0,
314    #[doc = "1: `1`"]
315    BMODE = 1,
316}
317impl From<BMODE_SEL_A> for bool {
318    #[inline(always)]
319    fn from(variant: BMODE_SEL_A) -> Self {
320        variant as u8 != 0
321    }
322}
323impl BMODE_SEL_R {
324    #[doc = "Get enumerated values variant"]
325    #[inline(always)]
326    pub const fn variant(&self) -> BMODE_SEL_A {
327        match self.bits {
328            false => BMODE_SEL_A::NORMAL,
329            true => BMODE_SEL_A::BMODE,
330        }
331    }
332    #[doc = "`0`"]
333    #[inline(always)]
334    pub fn is_normal(&self) -> bool {
335        *self == BMODE_SEL_A::NORMAL
336    }
337    #[doc = "`1`"]
338    #[inline(always)]
339    pub fn is_bmode(&self) -> bool {
340        *self == BMODE_SEL_A::BMODE
341    }
342}
343impl R {
344    #[doc = "Bits 0:5 - DMA Source DRQ Type"]
345    #[inline(always)]
346    pub fn dma_src_drq_type(&self) -> DMA_SRC_DRQ_TYPE_R {
347        DMA_SRC_DRQ_TYPE_R::new((self.bits & 0x3f) as u8)
348    }
349    #[doc = "Bits 6:7 - DMA Source Block Size"]
350    #[inline(always)]
351    pub fn dma_src_block_size(&self) -> DMA_SRC_BLOCK_SIZE_R {
352        DMA_SRC_BLOCK_SIZE_R::new(((self.bits >> 6) & 3) as u8)
353    }
354    #[doc = "Bit 8 - DMA Source Address Mode"]
355    #[inline(always)]
356    pub fn dma_src_addr_mode(&self) -> DMA_SRC_ADDR_MODE_R {
357        DMA_SRC_ADDR_MODE_R::new(((self.bits >> 8) & 1) != 0)
358    }
359    #[doc = "Bits 9:10 - DMA Source Data Width"]
360    #[inline(always)]
361    pub fn dma_src_data_width(&self) -> DMA_SRC_DATA_WIDTH_R {
362        DMA_SRC_DATA_WIDTH_R::new(((self.bits >> 9) & 3) as u8)
363    }
364    #[doc = "Bits 16:21 - DMA Destination DRQ Type"]
365    #[inline(always)]
366    pub fn dma_dest_drq_type(&self) -> DMA_DEST_DRQ_TYPE_R {
367        DMA_DEST_DRQ_TYPE_R::new(((self.bits >> 16) & 0x3f) as u8)
368    }
369    #[doc = "Bits 22:23 - DMA Destination Block Size"]
370    #[inline(always)]
371    pub fn dma_dest_block_size(&self) -> DMA_DEST_BLOCK_SIZE_R {
372        DMA_DEST_BLOCK_SIZE_R::new(((self.bits >> 22) & 3) as u8)
373    }
374    #[doc = "Bit 24 - DMA Destination Address Mode"]
375    #[inline(always)]
376    pub fn dma_addr_mode(&self) -> DMA_ADDR_MODE_R {
377        DMA_ADDR_MODE_R::new(((self.bits >> 24) & 1) != 0)
378    }
379    #[doc = "Bits 25:26 - DMA Destination Data Width"]
380    #[inline(always)]
381    pub fn dma_dest_data_width(&self) -> DMA_DEST_DATA_WIDTH_R {
382        DMA_DEST_DATA_WIDTH_R::new(((self.bits >> 25) & 3) as u8)
383    }
384    #[doc = "Bit 30"]
385    #[inline(always)]
386    pub fn bmode_sel(&self) -> BMODE_SEL_R {
387        BMODE_SEL_R::new(((self.bits >> 30) & 1) != 0)
388    }
389}
390#[doc = "DMAC Channel Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_cfg::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
391pub struct DMAC_CFG_SPEC;
392impl crate::RegisterSpec for DMAC_CFG_SPEC {
393    type Ux = u32;
394}
395#[doc = "`read()` method returns [`dmac_cfg::R`](R) reader structure"]
396impl crate::Readable for DMAC_CFG_SPEC {}
397#[doc = "`reset()` method sets dmac_cfg%s to value 0"]
398impl crate::Resettable for DMAC_CFG_SPEC {
399    const RESET_VALUE: Self::Ux = 0;
400}
d1_pac/dmac/dmac_cfg.rs

d1_pac/dmac/
dmac_cfg.rs
