d1_pac/dmac/
dmac_auto_gate.rs

1#[doc = "Register `dmac_auto_gate` reader"]
2pub type R = crate::R<DMAC_AUTO_GATE_SPEC>;
3#[doc = "Register `dmac_auto_gate` writer"]
4pub type W = crate::W<DMAC_AUTO_GATE_SPEC>;
5#[doc = "Field `dma_chan_circuit` reader - Auto gating bit of DMA channel circuit"]
6pub type DMA_CHAN_CIRCUIT_R = crate::BitReader<DMA_CHAN_CIRCUIT_A>;
7#[doc = "Auto gating bit of DMA channel circuit\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DMA_CHAN_CIRCUIT_A {
10    #[doc = "0: `0`"]
11    ENABLED = 0,
12    #[doc = "1: `1`"]
13    DISABLED = 1,
14}
15impl From<DMA_CHAN_CIRCUIT_A> for bool {
16    #[inline(always)]
17    fn from(variant: DMA_CHAN_CIRCUIT_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl DMA_CHAN_CIRCUIT_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> DMA_CHAN_CIRCUIT_A {
25        match self.bits {
26            false => DMA_CHAN_CIRCUIT_A::ENABLED,
27            true => DMA_CHAN_CIRCUIT_A::DISABLED,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_enabled(&self) -> bool {
33        *self == DMA_CHAN_CIRCUIT_A::ENABLED
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_disabled(&self) -> bool {
38        *self == DMA_CHAN_CIRCUIT_A::DISABLED
39    }
40}
41#[doc = "Field `dma_chan_circuit` writer - Auto gating bit of DMA channel circuit"]
42pub type DMA_CHAN_CIRCUIT_W<'a, REG> = crate::BitWriter<'a, REG, DMA_CHAN_CIRCUIT_A>;
43impl<'a, REG> DMA_CHAN_CIRCUIT_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn enabled(self) -> &'a mut crate::W<REG> {
50        self.variant(DMA_CHAN_CIRCUIT_A::ENABLED)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn disabled(self) -> &'a mut crate::W<REG> {
55        self.variant(DMA_CHAN_CIRCUIT_A::DISABLED)
56    }
57}
58#[doc = "Field `dma_common_circuit` reader - Auto gating bit of DMA common circuit"]
59pub type DMA_COMMON_CIRCUIT_R = crate::BitReader<DMA_COMMON_CIRCUIT_A>;
60#[doc = "Auto gating bit of DMA common circuit\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum DMA_COMMON_CIRCUIT_A {
63    #[doc = "0: `0`"]
64    ENABLED = 0,
65    #[doc = "1: `1`"]
66    DISABLED = 1,
67}
68impl From<DMA_COMMON_CIRCUIT_A> for bool {
69    #[inline(always)]
70    fn from(variant: DMA_COMMON_CIRCUIT_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl DMA_COMMON_CIRCUIT_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DMA_COMMON_CIRCUIT_A {
78        match self.bits {
79            false => DMA_COMMON_CIRCUIT_A::ENABLED,
80            true => DMA_COMMON_CIRCUIT_A::DISABLED,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_enabled(&self) -> bool {
86        *self == DMA_COMMON_CIRCUIT_A::ENABLED
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_disabled(&self) -> bool {
91        *self == DMA_COMMON_CIRCUIT_A::DISABLED
92    }
93}
94#[doc = "Field `dma_common_circuit` writer - Auto gating bit of DMA common circuit"]
95pub type DMA_COMMON_CIRCUIT_W<'a, REG> = crate::BitWriter<'a, REG, DMA_COMMON_CIRCUIT_A>;
96impl<'a, REG> DMA_COMMON_CIRCUIT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn enabled(self) -> &'a mut crate::W<REG> {
103        self.variant(DMA_COMMON_CIRCUIT_A::ENABLED)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn disabled(self) -> &'a mut crate::W<REG> {
108        self.variant(DMA_COMMON_CIRCUIT_A::DISABLED)
109    }
110}
111#[doc = "Field `dma_mclk_circuit` reader - Auto gating bit of DMA MCLK interfact circuit"]
112pub type DMA_MCLK_CIRCUIT_R = crate::BitReader<DMA_MCLK_CIRCUIT_A>;
113#[doc = "Auto gating bit of DMA MCLK interfact circuit\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DMA_MCLK_CIRCUIT_A {
116    #[doc = "0: `0`"]
117    ENABLED = 0,
118    #[doc = "1: `1`"]
119    DISABLED = 1,
120}
121impl From<DMA_MCLK_CIRCUIT_A> for bool {
122    #[inline(always)]
123    fn from(variant: DMA_MCLK_CIRCUIT_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl DMA_MCLK_CIRCUIT_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> DMA_MCLK_CIRCUIT_A {
131        match self.bits {
132            false => DMA_MCLK_CIRCUIT_A::ENABLED,
133            true => DMA_MCLK_CIRCUIT_A::DISABLED,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_enabled(&self) -> bool {
139        *self == DMA_MCLK_CIRCUIT_A::ENABLED
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_disabled(&self) -> bool {
144        *self == DMA_MCLK_CIRCUIT_A::DISABLED
145    }
146}
147#[doc = "Field `dma_mclk_circuit` writer - Auto gating bit of DMA MCLK interfact circuit"]
148pub type DMA_MCLK_CIRCUIT_W<'a, REG> = crate::BitWriter<'a, REG, DMA_MCLK_CIRCUIT_A>;
149impl<'a, REG> DMA_MCLK_CIRCUIT_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn enabled(self) -> &'a mut crate::W<REG> {
156        self.variant(DMA_MCLK_CIRCUIT_A::ENABLED)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn disabled(self) -> &'a mut crate::W<REG> {
161        self.variant(DMA_MCLK_CIRCUIT_A::DISABLED)
162    }
163}
164impl R {
165    #[doc = "Bit 0 - Auto gating bit of DMA channel circuit"]
166    #[inline(always)]
167    pub fn dma_chan_circuit(&self) -> DMA_CHAN_CIRCUIT_R {
168        DMA_CHAN_CIRCUIT_R::new((self.bits & 1) != 0)
169    }
170    #[doc = "Bit 1 - Auto gating bit of DMA common circuit"]
171    #[inline(always)]
172    pub fn dma_common_circuit(&self) -> DMA_COMMON_CIRCUIT_R {
173        DMA_COMMON_CIRCUIT_R::new(((self.bits >> 1) & 1) != 0)
174    }
175    #[doc = "Bit 2 - Auto gating bit of DMA MCLK interfact circuit"]
176    #[inline(always)]
177    pub fn dma_mclk_circuit(&self) -> DMA_MCLK_CIRCUIT_R {
178        DMA_MCLK_CIRCUIT_R::new(((self.bits >> 2) & 1) != 0)
179    }
180}
181impl W {
182    #[doc = "Bit 0 - Auto gating bit of DMA channel circuit"]
183    #[inline(always)]
184    #[must_use]
185    pub fn dma_chan_circuit(&mut self) -> DMA_CHAN_CIRCUIT_W<DMAC_AUTO_GATE_SPEC> {
186        DMA_CHAN_CIRCUIT_W::new(self, 0)
187    }
188    #[doc = "Bit 1 - Auto gating bit of DMA common circuit"]
189    #[inline(always)]
190    #[must_use]
191    pub fn dma_common_circuit(&mut self) -> DMA_COMMON_CIRCUIT_W<DMAC_AUTO_GATE_SPEC> {
192        DMA_COMMON_CIRCUIT_W::new(self, 1)
193    }
194    #[doc = "Bit 2 - Auto gating bit of DMA MCLK interfact circuit"]
195    #[inline(always)]
196    #[must_use]
197    pub fn dma_mclk_circuit(&mut self) -> DMA_MCLK_CIRCUIT_W<DMAC_AUTO_GATE_SPEC> {
198        DMA_MCLK_CIRCUIT_W::new(self, 2)
199    }
200    #[doc = r" Writes raw bits to the register."]
201    #[doc = r""]
202    #[doc = r" # Safety"]
203    #[doc = r""]
204    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.bits = bits;
208        self
209    }
210}
211#[doc = "DMAC Auto Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_auto_gate::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac_auto_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct DMAC_AUTO_GATE_SPEC;
213impl crate::RegisterSpec for DMAC_AUTO_GATE_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`dmac_auto_gate::R`](R) reader structure"]
217impl crate::Readable for DMAC_AUTO_GATE_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`dmac_auto_gate::W`](W) writer structure"]
219impl crate::Writable for DMAC_AUTO_GATE_SPEC {
220    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
221    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
222}
223#[doc = "`reset()` method sets dmac_auto_gate to value 0"]
224impl crate::Resettable for DMAC_AUTO_GATE_SPEC {
225    const RESET_VALUE: Self::Ux = 0;
226}
d1_pac/dmac/dmac_auto_gate.rs

d1_pac/dmac/
dmac_auto_gate.rs
