d1_pac/csic/csic_parser0/
prs_en.rs

1#[doc = "Register `prs_en` reader"]
2pub type R = crate::R<PRS_EN_SPEC>;
3#[doc = "Register `prs_en` writer"]
4pub type W = crate::W<PRS_EN_SPEC>;
5#[doc = "Field `prs_en` reader - "]
6pub type PRS_EN_R = crate::BitReader<PRS_EN_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PRS_EN_A {
10    #[doc = "0: Reset and disable the parser module"]
11    RESET_DISABLE = 0,
12    #[doc = "1: Enable the parser module"]
13    ENABLE = 1,
14}
15impl From<PRS_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: PRS_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl PRS_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PRS_EN_A {
25        match self.bits {
26            false => PRS_EN_A::RESET_DISABLE,
27            true => PRS_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Reset and disable the parser module"]
31    #[inline(always)]
32    pub fn is_reset_disable(&self) -> bool {
33        *self == PRS_EN_A::RESET_DISABLE
34    }
35    #[doc = "Enable the parser module"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == PRS_EN_A::ENABLE
39    }
40}
41#[doc = "Field `prs_en` writer - "]
42pub type PRS_EN_W<'a, REG> = crate::BitWriter<'a, REG, PRS_EN_A>;
43impl<'a, REG> PRS_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Reset and disable the parser module"]
48    #[inline(always)]
49    pub fn reset_disable(self) -> &'a mut crate::W<REG> {
50        self.variant(PRS_EN_A::RESET_DISABLE)
51    }
52    #[doc = "Enable the parser module"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(PRS_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `prs_mode` reader - "]
59pub type PRS_MODE_R = crate::BitReader<PRS_MODE_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum PRS_MODE_A {
63    #[doc = "1: MCSI"]
64    MCSI = 1,
65}
66impl From<PRS_MODE_A> for bool {
67    #[inline(always)]
68    fn from(variant: PRS_MODE_A) -> Self {
69        variant as u8 != 0
70    }
71}
72impl PRS_MODE_R {
73    #[doc = "Get enumerated values variant"]
74    #[inline(always)]
75    pub const fn variant(&self) -> Option<PRS_MODE_A> {
76        match self.bits {
77            true => Some(PRS_MODE_A::MCSI),
78            _ => None,
79        }
80    }
81    #[doc = "MCSI"]
82    #[inline(always)]
83    pub fn is_mcsi(&self) -> bool {
84        *self == PRS_MODE_A::MCSI
85    }
86}
87#[doc = "Field `prs_mode` writer - "]
88pub type PRS_MODE_W<'a, REG> = crate::BitWriter<'a, REG, PRS_MODE_A>;
89impl<'a, REG> PRS_MODE_W<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92{
93    #[doc = "MCSI"]
94    #[inline(always)]
95    pub fn mcsi(self) -> &'a mut crate::W<REG> {
96        self.variant(PRS_MODE_A::MCSI)
97    }
98}
99#[doc = "Field `prs_ch_mode` reader - "]
100pub type PRS_CH_MODE_R = crate::BitReader<PRS_CH_MODE_A>;
101#[doc = "\n\nValue on reset: 0"]
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103pub enum PRS_CH_MODE_A {
104    #[doc = "0: Parser output channel 0-3 corresponding from input channel 0-3"]
105    CORRESPONDING = 0,
106    #[doc = "1: Parser output channel 0-3 all from input channel 0 (MIPI SEHDR)"]
107    ALL_FROM_0 = 1,
108}
109impl From<PRS_CH_MODE_A> for bool {
110    #[inline(always)]
111    fn from(variant: PRS_CH_MODE_A) -> Self {
112        variant as u8 != 0
113    }
114}
115impl PRS_CH_MODE_R {
116    #[doc = "Get enumerated values variant"]
117    #[inline(always)]
118    pub const fn variant(&self) -> PRS_CH_MODE_A {
119        match self.bits {
120            false => PRS_CH_MODE_A::CORRESPONDING,
121            true => PRS_CH_MODE_A::ALL_FROM_0,
122        }
123    }
124    #[doc = "Parser output channel 0-3 corresponding from input channel 0-3"]
125    #[inline(always)]
126    pub fn is_corresponding(&self) -> bool {
127        *self == PRS_CH_MODE_A::CORRESPONDING
128    }
129    #[doc = "Parser output channel 0-3 all from input channel 0 (MIPI SEHDR)"]
130    #[inline(always)]
131    pub fn is_all_from_0(&self) -> bool {
132        *self == PRS_CH_MODE_A::ALL_FROM_0
133    }
134}
135#[doc = "Field `prs_ch_mode` writer - "]
136pub type PRS_CH_MODE_W<'a, REG> = crate::BitWriter<'a, REG, PRS_CH_MODE_A>;
137impl<'a, REG> PRS_CH_MODE_W<'a, REG>
138where
139    REG: crate::Writable + crate::RegisterSpec,
140{
141    #[doc = "Parser output channel 0-3 corresponding from input channel 0-3"]
142    #[inline(always)]
143    pub fn corresponding(self) -> &'a mut crate::W<REG> {
144        self.variant(PRS_CH_MODE_A::CORRESPONDING)
145    }
146    #[doc = "Parser output channel 0-3 all from input channel 0 (MIPI SEHDR)"]
147    #[inline(always)]
148    pub fn all_from_0(self) -> &'a mut crate::W<REG> {
149        self.variant(PRS_CH_MODE_A::ALL_FROM_0)
150    }
151}
152#[doc = "Field `pclk_en` reader - "]
153pub type PCLK_EN_R = crate::BitReader<PCLK_EN_A>;
154#[doc = "\n\nValue on reset: 0"]
155#[derive(Clone, Copy, Debug, PartialEq, Eq)]
156pub enum PCLK_EN_A {
157    #[doc = "0: Gate pclk input"]
158    G_ATE = 0,
159    #[doc = "1: Enable pclk input"]
160    ENABLE = 1,
161}
162impl From<PCLK_EN_A> for bool {
163    #[inline(always)]
164    fn from(variant: PCLK_EN_A) -> Self {
165        variant as u8 != 0
166    }
167}
168impl PCLK_EN_R {
169    #[doc = "Get enumerated values variant"]
170    #[inline(always)]
171    pub const fn variant(&self) -> PCLK_EN_A {
172        match self.bits {
173            false => PCLK_EN_A::G_ATE,
174            true => PCLK_EN_A::ENABLE,
175        }
176    }
177    #[doc = "Gate pclk input"]
178    #[inline(always)]
179    pub fn is_g_ate(&self) -> bool {
180        *self == PCLK_EN_A::G_ATE
181    }
182    #[doc = "Enable pclk input"]
183    #[inline(always)]
184    pub fn is_enable(&self) -> bool {
185        *self == PCLK_EN_A::ENABLE
186    }
187}
188#[doc = "Field `pclk_en` writer - "]
189pub type PCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, PCLK_EN_A>;
190impl<'a, REG> PCLK_EN_W<'a, REG>
191where
192    REG: crate::Writable + crate::RegisterSpec,
193{
194    #[doc = "Gate pclk input"]
195    #[inline(always)]
196    pub fn g_ate(self) -> &'a mut crate::W<REG> {
197        self.variant(PCLK_EN_A::G_ATE)
198    }
199    #[doc = "Enable pclk input"]
200    #[inline(always)]
201    pub fn enable(self) -> &'a mut crate::W<REG> {
202        self.variant(PCLK_EN_A::ENABLE)
203    }
204}
205#[doc = "Field `ncsic_en` reader - "]
206pub type NCSIC_EN_R = crate::BitReader<NCSIC_EN_A>;
207#[doc = "\n\nValue on reset: 0"]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209pub enum NCSIC_EN_A {
210    #[doc = "0: Reset and disable the NCSIC module"]
211    RESET_DISABLE = 0,
212    #[doc = "1: Enable the NCSIC module"]
213    ENABLE = 1,
214}
215impl From<NCSIC_EN_A> for bool {
216    #[inline(always)]
217    fn from(variant: NCSIC_EN_A) -> Self {
218        variant as u8 != 0
219    }
220}
221impl NCSIC_EN_R {
222    #[doc = "Get enumerated values variant"]
223    #[inline(always)]
224    pub const fn variant(&self) -> NCSIC_EN_A {
225        match self.bits {
226            false => NCSIC_EN_A::RESET_DISABLE,
227            true => NCSIC_EN_A::ENABLE,
228        }
229    }
230    #[doc = "Reset and disable the NCSIC module"]
231    #[inline(always)]
232    pub fn is_reset_disable(&self) -> bool {
233        *self == NCSIC_EN_A::RESET_DISABLE
234    }
235    #[doc = "Enable the NCSIC module"]
236    #[inline(always)]
237    pub fn is_enable(&self) -> bool {
238        *self == NCSIC_EN_A::ENABLE
239    }
240}
241#[doc = "Field `ncsic_en` writer - "]
242pub type NCSIC_EN_W<'a, REG> = crate::BitWriter<'a, REG, NCSIC_EN_A>;
243impl<'a, REG> NCSIC_EN_W<'a, REG>
244where
245    REG: crate::Writable + crate::RegisterSpec,
246{
247    #[doc = "Reset and disable the NCSIC module"]
248    #[inline(always)]
249    pub fn reset_disable(self) -> &'a mut crate::W<REG> {
250        self.variant(NCSIC_EN_A::RESET_DISABLE)
251    }
252    #[doc = "Enable the NCSIC module"]
253    #[inline(always)]
254    pub fn enable(self) -> &'a mut crate::W<REG> {
255        self.variant(NCSIC_EN_A::ENABLE)
256    }
257}
258impl R {
259    #[doc = "Bit 0"]
260    #[inline(always)]
261    pub fn prs_en(&self) -> PRS_EN_R {
262        PRS_EN_R::new((self.bits & 1) != 0)
263    }
264    #[doc = "Bit 1"]
265    #[inline(always)]
266    pub fn prs_mode(&self) -> PRS_MODE_R {
267        PRS_MODE_R::new(((self.bits >> 1) & 1) != 0)
268    }
269    #[doc = "Bit 2"]
270    #[inline(always)]
271    pub fn prs_ch_mode(&self) -> PRS_CH_MODE_R {
272        PRS_CH_MODE_R::new(((self.bits >> 2) & 1) != 0)
273    }
274    #[doc = "Bit 15"]
275    #[inline(always)]
276    pub fn pclk_en(&self) -> PCLK_EN_R {
277        PCLK_EN_R::new(((self.bits >> 15) & 1) != 0)
278    }
279    #[doc = "Bit 16"]
280    #[inline(always)]
281    pub fn ncsic_en(&self) -> NCSIC_EN_R {
282        NCSIC_EN_R::new(((self.bits >> 16) & 1) != 0)
283    }
284}
285impl W {
286    #[doc = "Bit 0"]
287    #[inline(always)]
288    #[must_use]
289    pub fn prs_en(&mut self) -> PRS_EN_W<PRS_EN_SPEC> {
290        PRS_EN_W::new(self, 0)
291    }
292    #[doc = "Bit 1"]
293    #[inline(always)]
294    #[must_use]
295    pub fn prs_mode(&mut self) -> PRS_MODE_W<PRS_EN_SPEC> {
296        PRS_MODE_W::new(self, 1)
297    }
298    #[doc = "Bit 2"]
299    #[inline(always)]
300    #[must_use]
301    pub fn prs_ch_mode(&mut self) -> PRS_CH_MODE_W<PRS_EN_SPEC> {
302        PRS_CH_MODE_W::new(self, 2)
303    }
304    #[doc = "Bit 15"]
305    #[inline(always)]
306    #[must_use]
307    pub fn pclk_en(&mut self) -> PCLK_EN_W<PRS_EN_SPEC> {
308        PCLK_EN_W::new(self, 15)
309    }
310    #[doc = "Bit 16"]
311    #[inline(always)]
312    #[must_use]
313    pub fn ncsic_en(&mut self) -> NCSIC_EN_W<PRS_EN_SPEC> {
314        NCSIC_EN_W::new(self, 16)
315    }
316    #[doc = r" Writes raw bits to the register."]
317    #[doc = r""]
318    #[doc = r" # Safety"]
319    #[doc = r""]
320    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
321    #[inline(always)]
322    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
323        self.bits = bits;
324        self
325    }
326}
327#[doc = "Parser Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prs_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prs_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
328pub struct PRS_EN_SPEC;
329impl crate::RegisterSpec for PRS_EN_SPEC {
330    type Ux = u32;
331}
332#[doc = "`read()` method returns [`prs_en::R`](R) reader structure"]
333impl crate::Readable for PRS_EN_SPEC {}
334#[doc = "`write(|w| ..)` method takes [`prs_en::W`](W) writer structure"]
335impl crate::Writable for PRS_EN_SPEC {
336    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
337    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
338}
339#[doc = "`reset()` method sets prs_en to value 0"]
340impl crate::Resettable for PRS_EN_SPEC {
341    const RESET_VALUE: Self::Ux = 0;
342}
d1_pac/csic/csic_parser0/prs_en.rs

d1_pac/csic/csic_parser0/
prs_en.rs
