d1_pac/csic/csic_parser0/
prs_ch0_line_time.rs

1#[doc = "Register `prs_ch%s0_line_time` reader"]
2pub type R = crate::R<PRS_CH0_LINE_TIME_SPEC>;
3#[doc = "Field `hsyn_time` reader - Time of H SYNC when vsync is valid\n\nThe unit is csi_top_clk cycle"]
4pub type HSYN_TIME_R = crate::FieldReader<u16>;
5#[doc = "Field `hblk_time` reader - Time of H Blanking when vsync is valid\n\nThe unit is csi_top_clk cycle"]
6pub type HBLK_TIME_R = crate::FieldReader<u16>;
7impl R {
8    #[doc = "Bits 0:15 - Time of H SYNC when vsync is valid\n\nThe unit is csi_top_clk cycle"]
9    #[inline(always)]
10    pub fn hsyn_time(&self) -> HSYN_TIME_R {
11        HSYN_TIME_R::new((self.bits & 0xffff) as u16)
12    }
13    #[doc = "Bits 16:31 - Time of H Blanking when vsync is valid\n\nThe unit is csi_top_clk cycle"]
14    #[inline(always)]
15    pub fn hblk_time(&self) -> HBLK_TIME_R {
16        HBLK_TIME_R::new(((self.bits >> 16) & 0xffff) as u16)
17    }
18}
19#[doc = "Parser Channel\\[i\\] Line Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prs_ch0_line_time::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20pub struct PRS_CH0_LINE_TIME_SPEC;
21impl crate::RegisterSpec for PRS_CH0_LINE_TIME_SPEC {
22    type Ux = u32;
23}
24#[doc = "`read()` method returns [`prs_ch0_line_time::R`](R) reader structure"]
25impl crate::Readable for PRS_CH0_LINE_TIME_SPEC {}
26#[doc = "`reset()` method sets prs_ch%s0_line_time to value 0"]
27impl crate::Resettable for PRS_CH0_LINE_TIME_SPEC {
28    const RESET_VALUE: Self::Ux = 0;
29}
d1_pac/csic/csic_parser0/prs_ch0_line_time.rs

d1_pac/csic/csic_parser0/
prs_ch0_line_time.rs
