d1_pac/csic/csic_parser0/
csic_prs_signal_sta.rs

1#[doc = "Register `csic_prs_signal_sta` reader"]
2pub type R = crate::R<CSIC_PRS_SIGNAL_STA_SPEC>;
3#[doc = "Register `csic_prs_signal_sta` writer"]
4pub type W = crate::W<CSIC_PRS_SIGNAL_STA_SPEC>;
5#[doc = "Field `data_sta` reader - Indicates the Dn status (n=0-23), MSB for D23, LSB for D0"]
6pub type DATA_STA_R = crate::FieldReader<u32>;
7#[doc = "Field `pclk_sta` reader - Indicates the pclk status"]
8pub type PCLK_STA_R = crate::BitReader<PCLK_STA_A>;
9#[doc = "Indicates the pclk status\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum PCLK_STA_A {
12    #[doc = "0: low"]
13    LOW = 0,
14    #[doc = "1: high"]
15    HIGH = 1,
16}
17impl From<PCLK_STA_A> for bool {
18    #[inline(always)]
19    fn from(variant: PCLK_STA_A) -> Self {
20        variant as u8 != 0
21    }
22}
23impl PCLK_STA_R {
24    #[doc = "Get enumerated values variant"]
25    #[inline(always)]
26    pub const fn variant(&self) -> PCLK_STA_A {
27        match self.bits {
28            false => PCLK_STA_A::LOW,
29            true => PCLK_STA_A::HIGH,
30        }
31    }
32    #[doc = "low"]
33    #[inline(always)]
34    pub fn is_low(&self) -> bool {
35        *self == PCLK_STA_A::LOW
36    }
37    #[doc = "high"]
38    #[inline(always)]
39    pub fn is_high(&self) -> bool {
40        *self == PCLK_STA_A::HIGH
41    }
42}
43impl R {
44    #[doc = "Bits 0:23 - Indicates the Dn status (n=0-23), MSB for D23, LSB for D0"]
45    #[inline(always)]
46    pub fn data_sta(&self) -> DATA_STA_R {
47        DATA_STA_R::new(self.bits & 0x00ff_ffff)
48    }
49    #[doc = "Bit 24 - Indicates the pclk status"]
50    #[inline(always)]
51    pub fn pclk_sta(&self) -> PCLK_STA_R {
52        PCLK_STA_R::new(((self.bits >> 24) & 1) != 0)
53    }
54}
55impl W {
56    #[doc = r" Writes raw bits to the register."]
57    #[doc = r""]
58    #[doc = r" # Safety"]
59    #[doc = r""]
60    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
61    #[inline(always)]
62    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
63        self.bits = bits;
64        self
65    }
66}
67#[doc = "CSIC Parser Signal Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_prs_signal_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_prs_signal_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
68pub struct CSIC_PRS_SIGNAL_STA_SPEC;
69impl crate::RegisterSpec for CSIC_PRS_SIGNAL_STA_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [`csic_prs_signal_sta::R`](R) reader structure"]
73impl crate::Readable for CSIC_PRS_SIGNAL_STA_SPEC {}
74#[doc = "`write(|w| ..)` method takes [`csic_prs_signal_sta::W`](W) writer structure"]
75impl crate::Writable for CSIC_PRS_SIGNAL_STA_SPEC {
76    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
77    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
78}
79#[doc = "`reset()` method sets csic_prs_signal_sta to value 0"]
80impl crate::Resettable for CSIC_PRS_SIGNAL_STA_SPEC {
81    const RESET_VALUE: Self::Ux = 0;
82}
d1_pac/csic/csic_parser0/csic_prs_signal_sta.rs

d1_pac/csic/csic_parser0/
csic_prs_signal_sta.rs
