d1_pac/csic/csic_dma/
csic_dma_en.rs

1#[doc = "Register `csic_dma_en` reader"]
2pub type R = crate::R<CSIC_DMA_EN_SPEC>;
3#[doc = "Register `csic_dma_en` writer"]
4pub type W = crate::W<CSIC_DMA_EN_SPEC>;
5#[doc = "Field `bk_top_en` reader - "]
6pub type BK_TOP_EN_R = crate::BitReader<BK_TOP_EN_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum BK_TOP_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<BK_TOP_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: BK_TOP_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl BK_TOP_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> BK_TOP_EN_A {
25        match self.bits {
26            false => BK_TOP_EN_A::DISABLE,
27            true => BK_TOP_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == BK_TOP_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == BK_TOP_EN_A::ENABLE
39    }
40}
41#[doc = "Field `bk_top_en` writer - "]
42pub type BK_TOP_EN_W<'a, REG> = crate::BitWriter<'a, REG, BK_TOP_EN_A>;
43impl<'a, REG> BK_TOP_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(BK_TOP_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(BK_TOP_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `clk_cnt_en` reader - clk count per frame enable"]
59pub type CLK_CNT_EN_R = crate::BitReader<CLK_CNT_EN_A>;
60#[doc = "clk count per frame enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CLK_CNT_EN_A {
63    #[doc = "0: Disable"]
64    DISABLE = 0,
65    #[doc = "1: Enable"]
66    ENABLE = 1,
67}
68impl From<CLK_CNT_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: CLK_CNT_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl CLK_CNT_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> CLK_CNT_EN_A {
78        match self.bits {
79            false => CLK_CNT_EN_A::DISABLE,
80            true => CLK_CNT_EN_A::ENABLE,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == CLK_CNT_EN_A::DISABLE
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == CLK_CNT_EN_A::ENABLE
92    }
93}
94#[doc = "Field `clk_cnt_en` writer - clk count per frame enable"]
95pub type CLK_CNT_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK_CNT_EN_A>;
96impl<'a, REG> CLK_CNT_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(CLK_CNT_EN_A::DISABLE)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(CLK_CNT_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `clk_cnt_spl` reader - Sampling time for clk counter per frame"]
112pub type CLK_CNT_SPL_R = crate::BitReader<CLK_CNT_SPL_A>;
113#[doc = "Sampling time for clk counter per frame\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CLK_CNT_SPL_A {
116    #[doc = "0: Sampling clock counter every frame done"]
117    FRAME_DONE = 0,
118    #[doc = "1: Sampling clock counter every vsync"]
119    VSYNC = 1,
120}
121impl From<CLK_CNT_SPL_A> for bool {
122    #[inline(always)]
123    fn from(variant: CLK_CNT_SPL_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl CLK_CNT_SPL_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> CLK_CNT_SPL_A {
131        match self.bits {
132            false => CLK_CNT_SPL_A::FRAME_DONE,
133            true => CLK_CNT_SPL_A::VSYNC,
134        }
135    }
136    #[doc = "Sampling clock counter every frame done"]
137    #[inline(always)]
138    pub fn is_frame_done(&self) -> bool {
139        *self == CLK_CNT_SPL_A::FRAME_DONE
140    }
141    #[doc = "Sampling clock counter every vsync"]
142    #[inline(always)]
143    pub fn is_vsync(&self) -> bool {
144        *self == CLK_CNT_SPL_A::VSYNC
145    }
146}
147#[doc = "Field `clk_cnt_spl` writer - Sampling time for clk counter per frame"]
148pub type CLK_CNT_SPL_W<'a, REG> = crate::BitWriter<'a, REG, CLK_CNT_SPL_A>;
149impl<'a, REG> CLK_CNT_SPL_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Sampling clock counter every frame done"]
154    #[inline(always)]
155    pub fn frame_done(self) -> &'a mut crate::W<REG> {
156        self.variant(CLK_CNT_SPL_A::FRAME_DONE)
157    }
158    #[doc = "Sampling clock counter every vsync"]
159    #[inline(always)]
160    pub fn vsync(self) -> &'a mut crate::W<REG> {
161        self.variant(CLK_CNT_SPL_A::VSYNC)
162    }
163}
164#[doc = "Field `dma_en` reader - When BK_TOP_EN is enabled, setting 1 to this bit indicates the module works in DMA mode."]
165pub type DMA_EN_R = crate::BitReader<DMA_EN_A>;
166#[doc = "When BK_TOP_EN is enabled, setting 1 to this bit indicates the module works in DMA mode.\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum DMA_EN_A {
169    #[doc = "0: Disable"]
170    DISABLE = 0,
171    #[doc = "1: Enable"]
172    ENABLE = 1,
173}
174impl From<DMA_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: DMA_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl DMA_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> DMA_EN_A {
184        match self.bits {
185            false => DMA_EN_A::DISABLE,
186            true => DMA_EN_A::ENABLE,
187        }
188    }
189    #[doc = "Disable"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == DMA_EN_A::DISABLE
193    }
194    #[doc = "Enable"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == DMA_EN_A::ENABLE
198    }
199}
200#[doc = "Field `dma_en` writer - When BK_TOP_EN is enabled, setting 1 to this bit indicates the module works in DMA mode."]
201pub type DMA_EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA_EN_A>;
202impl<'a, REG> DMA_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Disable"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(DMA_EN_A::DISABLE)
210    }
211    #[doc = "Enable"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(DMA_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `frame_cnt_en` reader - When BK_TOP_EN is enabled, setting 1 to this bit indicates the Frame counter starts to add."]
218pub type FRAME_CNT_EN_R = crate::BitReader<FRAME_CNT_EN_A>;
219#[doc = "When BK_TOP_EN is enabled, setting 1 to this bit indicates the Frame counter starts to add.\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum FRAME_CNT_EN_A {
222    #[doc = "0: Disable"]
223    DISABLE = 0,
224    #[doc = "1: Enable"]
225    ENABLE = 1,
226}
227impl From<FRAME_CNT_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: FRAME_CNT_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl FRAME_CNT_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> FRAME_CNT_EN_A {
237        match self.bits {
238            false => FRAME_CNT_EN_A::DISABLE,
239            true => FRAME_CNT_EN_A::ENABLE,
240        }
241    }
242    #[doc = "Disable"]
243    #[inline(always)]
244    pub fn is_disable(&self) -> bool {
245        *self == FRAME_CNT_EN_A::DISABLE
246    }
247    #[doc = "Enable"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == FRAME_CNT_EN_A::ENABLE
251    }
252}
253#[doc = "Field `frame_cnt_en` writer - When BK_TOP_EN is enabled, setting 1 to this bit indicates the Frame counter starts to add."]
254pub type FRAME_CNT_EN_W<'a, REG> = crate::BitWriter<'a, REG, FRAME_CNT_EN_A>;
255impl<'a, REG> FRAME_CNT_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Disable"]
260    #[inline(always)]
261    pub fn disable(self) -> &'a mut crate::W<REG> {
262        self.variant(FRAME_CNT_EN_A::DISABLE)
263    }
264    #[doc = "Enable"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(FRAME_CNT_EN_A::ENABLE)
268    }
269}
270#[doc = "Field `vi_to_cnt_en` reader - Enable Video Input Timeout counter, add 1 when there is no effective video input in a 12M clock, clear to 0 when detecting effective video input."]
271pub type VI_TO_CNT_EN_R = crate::BitReader<VI_TO_CNT_EN_A>;
272#[doc = "Enable Video Input Timeout counter, add 1 when there is no effective video input in a 12M clock, clear to 0 when detecting effective video input.\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum VI_TO_CNT_EN_A {
275    #[doc = "0: Disable"]
276    DISABLE = 0,
277    #[doc = "1: Enable"]
278    ENABLE = 1,
279}
280impl From<VI_TO_CNT_EN_A> for bool {
281    #[inline(always)]
282    fn from(variant: VI_TO_CNT_EN_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl VI_TO_CNT_EN_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> VI_TO_CNT_EN_A {
290        match self.bits {
291            false => VI_TO_CNT_EN_A::DISABLE,
292            true => VI_TO_CNT_EN_A::ENABLE,
293        }
294    }
295    #[doc = "Disable"]
296    #[inline(always)]
297    pub fn is_disable(&self) -> bool {
298        *self == VI_TO_CNT_EN_A::DISABLE
299    }
300    #[doc = "Enable"]
301    #[inline(always)]
302    pub fn is_enable(&self) -> bool {
303        *self == VI_TO_CNT_EN_A::ENABLE
304    }
305}
306#[doc = "Field `vi_to_cnt_en` writer - Enable Video Input Timeout counter, add 1 when there is no effective video input in a 12M clock, clear to 0 when detecting effective video input."]
307pub type VI_TO_CNT_EN_W<'a, REG> = crate::BitWriter<'a, REG, VI_TO_CNT_EN_A>;
308impl<'a, REG> VI_TO_CNT_EN_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Disable"]
313    #[inline(always)]
314    pub fn disable(self) -> &'a mut crate::W<REG> {
315        self.variant(VI_TO_CNT_EN_A::DISABLE)
316    }
317    #[doc = "Enable"]
318    #[inline(always)]
319    pub fn enable(self) -> &'a mut crate::W<REG> {
320        self.variant(VI_TO_CNT_EN_A::ENABLE)
321    }
322}
323#[doc = "Field `buf_addr_mode` reader - "]
324pub type BUF_ADDR_MODE_R = crate::BitReader<BUF_ADDR_MODE_A>;
325#[doc = "\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum BUF_ADDR_MODE_A {
328    #[doc = "0: Buffer Address Register Mode"]
329    R_EGISTER = 0,
330    #[doc = "1: Buffer Address FIFO Mode"]
331    FIFO = 1,
332}
333impl From<BUF_ADDR_MODE_A> for bool {
334    #[inline(always)]
335    fn from(variant: BUF_ADDR_MODE_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl BUF_ADDR_MODE_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> BUF_ADDR_MODE_A {
343        match self.bits {
344            false => BUF_ADDR_MODE_A::R_EGISTER,
345            true => BUF_ADDR_MODE_A::FIFO,
346        }
347    }
348    #[doc = "Buffer Address Register Mode"]
349    #[inline(always)]
350    pub fn is_r_egister(&self) -> bool {
351        *self == BUF_ADDR_MODE_A::R_EGISTER
352    }
353    #[doc = "Buffer Address FIFO Mode"]
354    #[inline(always)]
355    pub fn is_fifo(&self) -> bool {
356        *self == BUF_ADDR_MODE_A::FIFO
357    }
358}
359#[doc = "Field `buf_addr_mode` writer - "]
360pub type BUF_ADDR_MODE_W<'a, REG> = crate::BitWriter<'a, REG, BUF_ADDR_MODE_A>;
361impl<'a, REG> BUF_ADDR_MODE_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "Buffer Address Register Mode"]
366    #[inline(always)]
367    pub fn r_egister(self) -> &'a mut crate::W<REG> {
368        self.variant(BUF_ADDR_MODE_A::R_EGISTER)
369    }
370    #[doc = "Buffer Address FIFO Mode"]
371    #[inline(always)]
372    pub fn fifo(self) -> &'a mut crate::W<REG> {
373        self.variant(BUF_ADDR_MODE_A::FIFO)
374    }
375}
376#[doc = "Field `flip_size_cfg_mode` reader - FLIP SIZE set by software or calculated by hardware"]
377pub type FLIP_SIZE_CFG_MODE_R = crate::BitReader<FLIP_SIZE_CFG_MODE_A>;
378#[doc = "FLIP SIZE set by software or calculated by hardware\n\nValue on reset: 1"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380pub enum FLIP_SIZE_CFG_MODE_A {
381    #[doc = "0: Hardware"]
382    H_ARDWARE = 0,
383    #[doc = "1: Software"]
384    S_OFTWARE = 1,
385}
386impl From<FLIP_SIZE_CFG_MODE_A> for bool {
387    #[inline(always)]
388    fn from(variant: FLIP_SIZE_CFG_MODE_A) -> Self {
389        variant as u8 != 0
390    }
391}
392impl FLIP_SIZE_CFG_MODE_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> FLIP_SIZE_CFG_MODE_A {
396        match self.bits {
397            false => FLIP_SIZE_CFG_MODE_A::H_ARDWARE,
398            true => FLIP_SIZE_CFG_MODE_A::S_OFTWARE,
399        }
400    }
401    #[doc = "Hardware"]
402    #[inline(always)]
403    pub fn is_h_ardware(&self) -> bool {
404        *self == FLIP_SIZE_CFG_MODE_A::H_ARDWARE
405    }
406    #[doc = "Software"]
407    #[inline(always)]
408    pub fn is_s_oftware(&self) -> bool {
409        *self == FLIP_SIZE_CFG_MODE_A::S_OFTWARE
410    }
411}
412#[doc = "Field `flip_size_cfg_mode` writer - FLIP SIZE set by software or calculated by hardware"]
413pub type FLIP_SIZE_CFG_MODE_W<'a, REG> = crate::BitWriter<'a, REG, FLIP_SIZE_CFG_MODE_A>;
414impl<'a, REG> FLIP_SIZE_CFG_MODE_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "Hardware"]
419    #[inline(always)]
420    pub fn h_ardware(self) -> &'a mut crate::W<REG> {
421        self.variant(FLIP_SIZE_CFG_MODE_A::H_ARDWARE)
422    }
423    #[doc = "Software"]
424    #[inline(always)]
425    pub fn s_oftware(self) -> &'a mut crate::W<REG> {
426        self.variant(FLIP_SIZE_CFG_MODE_A::S_OFTWARE)
427    }
428}
429#[doc = "Field `buf_length_cfg_mode` reader - Buffer length set by software or calculated by hardware"]
430pub type BUF_LENGTH_CFG_MODE_R = crate::BitReader<BUF_LENGTH_CFG_MODE_A>;
431#[doc = "Buffer length set by software or calculated by hardware\n\nValue on reset: 1"]
432#[derive(Clone, Copy, Debug, PartialEq, Eq)]
433pub enum BUF_LENGTH_CFG_MODE_A {
434    #[doc = "0: Hardware"]
435    H_ARDWARE = 0,
436    #[doc = "1: Software"]
437    S_OFTWARE = 1,
438}
439impl From<BUF_LENGTH_CFG_MODE_A> for bool {
440    #[inline(always)]
441    fn from(variant: BUF_LENGTH_CFG_MODE_A) -> Self {
442        variant as u8 != 0
443    }
444}
445impl BUF_LENGTH_CFG_MODE_R {
446    #[doc = "Get enumerated values variant"]
447    #[inline(always)]
448    pub const fn variant(&self) -> BUF_LENGTH_CFG_MODE_A {
449        match self.bits {
450            false => BUF_LENGTH_CFG_MODE_A::H_ARDWARE,
451            true => BUF_LENGTH_CFG_MODE_A::S_OFTWARE,
452        }
453    }
454    #[doc = "Hardware"]
455    #[inline(always)]
456    pub fn is_h_ardware(&self) -> bool {
457        *self == BUF_LENGTH_CFG_MODE_A::H_ARDWARE
458    }
459    #[doc = "Software"]
460    #[inline(always)]
461    pub fn is_s_oftware(&self) -> bool {
462        *self == BUF_LENGTH_CFG_MODE_A::S_OFTWARE
463    }
464}
465#[doc = "Field `buf_length_cfg_mode` writer - Buffer length set by software or calculated by hardware"]
466pub type BUF_LENGTH_CFG_MODE_W<'a, REG> = crate::BitWriter<'a, REG, BUF_LENGTH_CFG_MODE_A>;
467impl<'a, REG> BUF_LENGTH_CFG_MODE_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    #[doc = "Hardware"]
472    #[inline(always)]
473    pub fn h_ardware(self) -> &'a mut crate::W<REG> {
474        self.variant(BUF_LENGTH_CFG_MODE_A::H_ARDWARE)
475    }
476    #[doc = "Software"]
477    #[inline(always)]
478    pub fn s_oftware(self) -> &'a mut crate::W<REG> {
479        self.variant(BUF_LENGTH_CFG_MODE_A::S_OFTWARE)
480    }
481}
482#[doc = "Field `vflip_buf_addr_cfg_mode` reader - Vflip buffer address set by software or calculated by hardware"]
483pub type VFLIP_BUF_ADDR_CFG_MODE_R = crate::BitReader<VFLIP_BUF_ADDR_CFG_MODE_A>;
484#[doc = "Vflip buffer address set by software or calculated by hardware\n\nValue on reset: 1"]
485#[derive(Clone, Copy, Debug, PartialEq, Eq)]
486pub enum VFLIP_BUF_ADDR_CFG_MODE_A {
487    #[doc = "0: Hardware"]
488    H_ARDWARE = 0,
489    #[doc = "1: Software"]
490    S_OFTWARE = 1,
491}
492impl From<VFLIP_BUF_ADDR_CFG_MODE_A> for bool {
493    #[inline(always)]
494    fn from(variant: VFLIP_BUF_ADDR_CFG_MODE_A) -> Self {
495        variant as u8 != 0
496    }
497}
498impl VFLIP_BUF_ADDR_CFG_MODE_R {
499    #[doc = "Get enumerated values variant"]
500    #[inline(always)]
501    pub const fn variant(&self) -> VFLIP_BUF_ADDR_CFG_MODE_A {
502        match self.bits {
503            false => VFLIP_BUF_ADDR_CFG_MODE_A::H_ARDWARE,
504            true => VFLIP_BUF_ADDR_CFG_MODE_A::S_OFTWARE,
505        }
506    }
507    #[doc = "Hardware"]
508    #[inline(always)]
509    pub fn is_h_ardware(&self) -> bool {
510        *self == VFLIP_BUF_ADDR_CFG_MODE_A::H_ARDWARE
511    }
512    #[doc = "Software"]
513    #[inline(always)]
514    pub fn is_s_oftware(&self) -> bool {
515        *self == VFLIP_BUF_ADDR_CFG_MODE_A::S_OFTWARE
516    }
517}
518#[doc = "Field `vflip_buf_addr_cfg_mode` writer - Vflip buffer address set by software or calculated by hardware"]
519pub type VFLIP_BUF_ADDR_CFG_MODE_W<'a, REG> = crate::BitWriter<'a, REG, VFLIP_BUF_ADDR_CFG_MODE_A>;
520impl<'a, REG> VFLIP_BUF_ADDR_CFG_MODE_W<'a, REG>
521where
522    REG: crate::Writable + crate::RegisterSpec,
523{
524    #[doc = "Hardware"]
525    #[inline(always)]
526    pub fn h_ardware(self) -> &'a mut crate::W<REG> {
527        self.variant(VFLIP_BUF_ADDR_CFG_MODE_A::H_ARDWARE)
528    }
529    #[doc = "Software"]
530    #[inline(always)]
531    pub fn s_oftware(self) -> &'a mut crate::W<REG> {
532        self.variant(VFLIP_BUF_ADDR_CFG_MODE_A::S_OFTWARE)
533    }
534}
535#[doc = "Field `ver_en` reader - "]
536pub type VER_EN_R = crate::BitReader;
537#[doc = "Field `ver_en` writer - "]
538pub type VER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
539impl R {
540    #[doc = "Bit 0"]
541    #[inline(always)]
542    pub fn bk_top_en(&self) -> BK_TOP_EN_R {
543        BK_TOP_EN_R::new((self.bits & 1) != 0)
544    }
545    #[doc = "Bit 1 - clk count per frame enable"]
546    #[inline(always)]
547    pub fn clk_cnt_en(&self) -> CLK_CNT_EN_R {
548        CLK_CNT_EN_R::new(((self.bits >> 1) & 1) != 0)
549    }
550    #[doc = "Bit 2 - Sampling time for clk counter per frame"]
551    #[inline(always)]
552    pub fn clk_cnt_spl(&self) -> CLK_CNT_SPL_R {
553        CLK_CNT_SPL_R::new(((self.bits >> 2) & 1) != 0)
554    }
555    #[doc = "Bit 4 - When BK_TOP_EN is enabled, setting 1 to this bit indicates the module works in DMA mode."]
556    #[inline(always)]
557    pub fn dma_en(&self) -> DMA_EN_R {
558        DMA_EN_R::new(((self.bits >> 4) & 1) != 0)
559    }
560    #[doc = "Bit 5 - When BK_TOP_EN is enabled, setting 1 to this bit indicates the Frame counter starts to add."]
561    #[inline(always)]
562    pub fn frame_cnt_en(&self) -> FRAME_CNT_EN_R {
563        FRAME_CNT_EN_R::new(((self.bits >> 5) & 1) != 0)
564    }
565    #[doc = "Bit 6 - Enable Video Input Timeout counter, add 1 when there is no effective video input in a 12M clock, clear to 0 when detecting effective video input."]
566    #[inline(always)]
567    pub fn vi_to_cnt_en(&self) -> VI_TO_CNT_EN_R {
568        VI_TO_CNT_EN_R::new(((self.bits >> 6) & 1) != 0)
569    }
570    #[doc = "Bit 7"]
571    #[inline(always)]
572    pub fn buf_addr_mode(&self) -> BUF_ADDR_MODE_R {
573        BUF_ADDR_MODE_R::new(((self.bits >> 7) & 1) != 0)
574    }
575    #[doc = "Bit 28 - FLIP SIZE set by software or calculated by hardware"]
576    #[inline(always)]
577    pub fn flip_size_cfg_mode(&self) -> FLIP_SIZE_CFG_MODE_R {
578        FLIP_SIZE_CFG_MODE_R::new(((self.bits >> 28) & 1) != 0)
579    }
580    #[doc = "Bit 29 - Buffer length set by software or calculated by hardware"]
581    #[inline(always)]
582    pub fn buf_length_cfg_mode(&self) -> BUF_LENGTH_CFG_MODE_R {
583        BUF_LENGTH_CFG_MODE_R::new(((self.bits >> 29) & 1) != 0)
584    }
585    #[doc = "Bit 30 - Vflip buffer address set by software or calculated by hardware"]
586    #[inline(always)]
587    pub fn vflip_buf_addr_cfg_mode(&self) -> VFLIP_BUF_ADDR_CFG_MODE_R {
588        VFLIP_BUF_ADDR_CFG_MODE_R::new(((self.bits >> 30) & 1) != 0)
589    }
590    #[doc = "Bit 31"]
591    #[inline(always)]
592    pub fn ver_en(&self) -> VER_EN_R {
593        VER_EN_R::new(((self.bits >> 31) & 1) != 0)
594    }
595}
596impl W {
597    #[doc = "Bit 0"]
598    #[inline(always)]
599    #[must_use]
600    pub fn bk_top_en(&mut self) -> BK_TOP_EN_W<CSIC_DMA_EN_SPEC> {
601        BK_TOP_EN_W::new(self, 0)
602    }
603    #[doc = "Bit 1 - clk count per frame enable"]
604    #[inline(always)]
605    #[must_use]
606    pub fn clk_cnt_en(&mut self) -> CLK_CNT_EN_W<CSIC_DMA_EN_SPEC> {
607        CLK_CNT_EN_W::new(self, 1)
608    }
609    #[doc = "Bit 2 - Sampling time for clk counter per frame"]
610    #[inline(always)]
611    #[must_use]
612    pub fn clk_cnt_spl(&mut self) -> CLK_CNT_SPL_W<CSIC_DMA_EN_SPEC> {
613        CLK_CNT_SPL_W::new(self, 2)
614    }
615    #[doc = "Bit 4 - When BK_TOP_EN is enabled, setting 1 to this bit indicates the module works in DMA mode."]
616    #[inline(always)]
617    #[must_use]
618    pub fn dma_en(&mut self) -> DMA_EN_W<CSIC_DMA_EN_SPEC> {
619        DMA_EN_W::new(self, 4)
620    }
621    #[doc = "Bit 5 - When BK_TOP_EN is enabled, setting 1 to this bit indicates the Frame counter starts to add."]
622    #[inline(always)]
623    #[must_use]
624    pub fn frame_cnt_en(&mut self) -> FRAME_CNT_EN_W<CSIC_DMA_EN_SPEC> {
625        FRAME_CNT_EN_W::new(self, 5)
626    }
627    #[doc = "Bit 6 - Enable Video Input Timeout counter, add 1 when there is no effective video input in a 12M clock, clear to 0 when detecting effective video input."]
628    #[inline(always)]
629    #[must_use]
630    pub fn vi_to_cnt_en(&mut self) -> VI_TO_CNT_EN_W<CSIC_DMA_EN_SPEC> {
631        VI_TO_CNT_EN_W::new(self, 6)
632    }
633    #[doc = "Bit 7"]
634    #[inline(always)]
635    #[must_use]
636    pub fn buf_addr_mode(&mut self) -> BUF_ADDR_MODE_W<CSIC_DMA_EN_SPEC> {
637        BUF_ADDR_MODE_W::new(self, 7)
638    }
639    #[doc = "Bit 28 - FLIP SIZE set by software or calculated by hardware"]
640    #[inline(always)]
641    #[must_use]
642    pub fn flip_size_cfg_mode(&mut self) -> FLIP_SIZE_CFG_MODE_W<CSIC_DMA_EN_SPEC> {
643        FLIP_SIZE_CFG_MODE_W::new(self, 28)
644    }
645    #[doc = "Bit 29 - Buffer length set by software or calculated by hardware"]
646    #[inline(always)]
647    #[must_use]
648    pub fn buf_length_cfg_mode(&mut self) -> BUF_LENGTH_CFG_MODE_W<CSIC_DMA_EN_SPEC> {
649        BUF_LENGTH_CFG_MODE_W::new(self, 29)
650    }
651    #[doc = "Bit 30 - Vflip buffer address set by software or calculated by hardware"]
652    #[inline(always)]
653    #[must_use]
654    pub fn vflip_buf_addr_cfg_mode(&mut self) -> VFLIP_BUF_ADDR_CFG_MODE_W<CSIC_DMA_EN_SPEC> {
655        VFLIP_BUF_ADDR_CFG_MODE_W::new(self, 30)
656    }
657    #[doc = "Bit 31"]
658    #[inline(always)]
659    #[must_use]
660    pub fn ver_en(&mut self) -> VER_EN_W<CSIC_DMA_EN_SPEC> {
661        VER_EN_W::new(self, 31)
662    }
663    #[doc = r" Writes raw bits to the register."]
664    #[doc = r""]
665    #[doc = r" # Safety"]
666    #[doc = r""]
667    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
668    #[inline(always)]
669    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
670        self.bits = bits;
671        self
672    }
673}
674#[doc = "CSIC DMA Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
675pub struct CSIC_DMA_EN_SPEC;
676impl crate::RegisterSpec for CSIC_DMA_EN_SPEC {
677    type Ux = u32;
678}
679#[doc = "`read()` method returns [`csic_dma_en::R`](R) reader structure"]
680impl crate::Readable for CSIC_DMA_EN_SPEC {}
681#[doc = "`write(|w| ..)` method takes [`csic_dma_en::W`](W) writer structure"]
682impl crate::Writable for CSIC_DMA_EN_SPEC {
683    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
684    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
685}
686#[doc = "`reset()` method sets csic_dma_en to value 0x7000_0000"]
687impl crate::Resettable for CSIC_DMA_EN_SPEC {
688    const RESET_VALUE: Self::Ux = 0x7000_0000;
689}
d1_pac/csic/csic_dma/csic_dma_en.rs

d1_pac/csic/csic_dma/
csic_dma_en.rs
