d1_pac/cir_tx/
cir_txsta.rs

1#[doc = "Register `cir_txsta` reader"]
2pub type R = crate::R<CIR_TXSTA_SPEC>;
3#[doc = "Register `cir_txsta` writer"]
4pub type W = crate::W<CIR_TXSTA_SPEC>;
5#[doc = "Field `tpe_tur` reader - Transmitter Packet End Flag for Cyclical Pulse / TUR Transmitter FIFO Underrun Flag for Non-cyclical Pulse"]
6pub type TPE_TUR_R = crate::BitReader<TPE_TUR_A>;
7#[doc = "Transmitter Packet End Flag for Cyclical Pulse / TUR Transmitter FIFO Underrun Flag for Non-cyclical Pulse\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TPE_TUR_A {
10    #[doc = "0: Transmissions of address, control and data fields not completed / No transmitter FIFO underrun"]
11    NOT_COMPLETE_OR_TRANSMIT = 0,
12    #[doc = "1: Transmissions of address, control and data fields completed / Transmitter FIFO underrun"]
13    COMPLETE_OR_TRANSMIT = 1,
14}
15impl From<TPE_TUR_A> for bool {
16    #[inline(always)]
17    fn from(variant: TPE_TUR_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TPE_TUR_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TPE_TUR_A {
25        match self.bits {
26            false => TPE_TUR_A::NOT_COMPLETE_OR_TRANSMIT,
27            true => TPE_TUR_A::COMPLETE_OR_TRANSMIT,
28        }
29    }
30    #[doc = "Transmissions of address, control and data fields not completed / No transmitter FIFO underrun"]
31    #[inline(always)]
32    pub fn is_not_complete_or_transmit(&self) -> bool {
33        *self == TPE_TUR_A::NOT_COMPLETE_OR_TRANSMIT
34    }
35    #[doc = "Transmissions of address, control and data fields completed / Transmitter FIFO underrun"]
36    #[inline(always)]
37    pub fn is_complete_or_transmit(&self) -> bool {
38        *self == TPE_TUR_A::COMPLETE_OR_TRANSMIT
39    }
40}
41#[doc = "Field `tpe_tur` writer - Transmitter Packet End Flag for Cyclical Pulse / TUR Transmitter FIFO Underrun Flag for Non-cyclical Pulse"]
42pub type TPE_TUR_W<'a, REG> = crate::BitWriter1C<'a, REG, TPE_TUR_A>;
43impl<'a, REG> TPE_TUR_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Transmissions of address, control and data fields not completed / No transmitter FIFO underrun"]
48    #[inline(always)]
49    pub fn not_complete_or_transmit(self) -> &'a mut crate::W<REG> {
50        self.variant(TPE_TUR_A::NOT_COMPLETE_OR_TRANSMIT)
51    }
52    #[doc = "Transmissions of address, control and data fields completed / Transmitter FIFO underrun"]
53    #[inline(always)]
54    pub fn complete_or_transmit(self) -> &'a mut crate::W<REG> {
55        self.variant(TPE_TUR_A::COMPLETE_OR_TRANSMIT)
56    }
57}
58#[doc = "Field `tai` reader - TX FIFO Available Interrupt Flag"]
59pub type TAI_R = crate::BitReader<TAI_A>;
60#[doc = "TX FIFO Available Interrupt Flag\n\nValue on reset: 1"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TAI_A {
63    #[doc = "0: TX FIFO not available by its level"]
64    NOT_AVAILABLE = 0,
65    #[doc = "1: TX FIFO available by its level Writing 1 clears this bit."]
66    AVAILABLE = 1,
67}
68impl From<TAI_A> for bool {
69    #[inline(always)]
70    fn from(variant: TAI_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TAI_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TAI_A {
78        match self.bits {
79            false => TAI_A::NOT_AVAILABLE,
80            true => TAI_A::AVAILABLE,
81        }
82    }
83    #[doc = "TX FIFO not available by its level"]
84    #[inline(always)]
85    pub fn is_not_available(&self) -> bool {
86        *self == TAI_A::NOT_AVAILABLE
87    }
88    #[doc = "TX FIFO available by its level Writing 1 clears this bit."]
89    #[inline(always)]
90    pub fn is_available(&self) -> bool {
91        *self == TAI_A::AVAILABLE
92    }
93}
94#[doc = "Field `tai` writer - TX FIFO Available Interrupt Flag"]
95pub type TAI_W<'a, REG> = crate::BitWriter<'a, REG, TAI_A>;
96impl<'a, REG> TAI_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "TX FIFO not available by its level"]
101    #[inline(always)]
102    pub fn not_available(self) -> &'a mut crate::W<REG> {
103        self.variant(TAI_A::NOT_AVAILABLE)
104    }
105    #[doc = "TX FIFO available by its level Writing 1 clears this bit."]
106    #[inline(always)]
107    pub fn available(self) -> &'a mut crate::W<REG> {
108        self.variant(TAI_A::AVAILABLE)
109    }
110}
111#[doc = "Field `drq` reader - DMA Request Flag"]
112pub type DRQ_R = crate::BitReader;
113#[doc = "Field `stct` reader - Status of CIR Transmitter"]
114pub type STCT_R = crate::BitReader<STCT_A>;
115#[doc = "Status of CIR Transmitter\n\nValue on reset: 0"]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum STCT_A {
118    #[doc = "0: Idle"]
119    IDLE = 0,
120    #[doc = "1: Active"]
121    ACTIVE = 1,
122}
123impl From<STCT_A> for bool {
124    #[inline(always)]
125    fn from(variant: STCT_A) -> Self {
126        variant as u8 != 0
127    }
128}
129impl STCT_R {
130    #[doc = "Get enumerated values variant"]
131    #[inline(always)]
132    pub const fn variant(&self) -> STCT_A {
133        match self.bits {
134            false => STCT_A::IDLE,
135            true => STCT_A::ACTIVE,
136        }
137    }
138    #[doc = "Idle"]
139    #[inline(always)]
140    pub fn is_idle(&self) -> bool {
141        *self == STCT_A::IDLE
142    }
143    #[doc = "Active"]
144    #[inline(always)]
145    pub fn is_active(&self) -> bool {
146        *self == STCT_A::ACTIVE
147    }
148}
149impl R {
150    #[doc = "Bit 0 - Transmitter Packet End Flag for Cyclical Pulse / TUR Transmitter FIFO Underrun Flag for Non-cyclical Pulse"]
151    #[inline(always)]
152    pub fn tpe_tur(&self) -> TPE_TUR_R {
153        TPE_TUR_R::new((self.bits & 1) != 0)
154    }
155    #[doc = "Bit 1 - TX FIFO Available Interrupt Flag"]
156    #[inline(always)]
157    pub fn tai(&self) -> TAI_R {
158        TAI_R::new(((self.bits >> 1) & 1) != 0)
159    }
160    #[doc = "Bit 2 - DMA Request Flag"]
161    #[inline(always)]
162    pub fn drq(&self) -> DRQ_R {
163        DRQ_R::new(((self.bits >> 2) & 1) != 0)
164    }
165    #[doc = "Bit 3 - Status of CIR Transmitter"]
166    #[inline(always)]
167    pub fn stct(&self) -> STCT_R {
168        STCT_R::new(((self.bits >> 3) & 1) != 0)
169    }
170}
171impl W {
172    #[doc = "Bit 0 - Transmitter Packet End Flag for Cyclical Pulse / TUR Transmitter FIFO Underrun Flag for Non-cyclical Pulse"]
173    #[inline(always)]
174    #[must_use]
175    pub fn tpe_tur(&mut self) -> TPE_TUR_W<CIR_TXSTA_SPEC> {
176        TPE_TUR_W::new(self, 0)
177    }
178    #[doc = "Bit 1 - TX FIFO Available Interrupt Flag"]
179    #[inline(always)]
180    #[must_use]
181    pub fn tai(&mut self) -> TAI_W<CIR_TXSTA_SPEC> {
182        TAI_W::new(self, 1)
183    }
184    #[doc = r" Writes raw bits to the register."]
185    #[doc = r""]
186    #[doc = r" # Safety"]
187    #[doc = r""]
188    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
189    #[inline(always)]
190    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
191        self.bits = bits;
192        self
193    }
194}
195#[doc = "CIR Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txsta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txsta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
196pub struct CIR_TXSTA_SPEC;
197impl crate::RegisterSpec for CIR_TXSTA_SPEC {
198    type Ux = u32;
199}
200#[doc = "`read()` method returns [`cir_txsta::R`](R) reader structure"]
201impl crate::Readable for CIR_TXSTA_SPEC {}
202#[doc = "`write(|w| ..)` method takes [`cir_txsta::W`](W) writer structure"]
203impl crate::Writable for CIR_TXSTA_SPEC {
204    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x01;
206}
207#[doc = "`reset()` method sets cir_txsta to value 0x02"]
208impl crate::Resettable for CIR_TXSTA_SPEC {
209    const RESET_VALUE: Self::Ux = 0x02;
210}
d1_pac/cir_tx/cir_txsta.rs

d1_pac/cir_tx/
cir_txsta.rs
