d1_pac/cir_tx/
cir_dma_ctl.rs

1#[doc = "Register `cir_dma_ctl` reader"]
2pub type R = crate::R<CIR_DMA_CTL_SPEC>;
3#[doc = "Register `cir_dma_ctl` writer"]
4pub type W = crate::W<CIR_DMA_CTL_SPEC>;
5#[doc = "Field `dma` reader - Handshake Configuration"]
6pub type DMA_R = crate::FieldReader<DMA_A>;
7#[doc = "Handshake Configuration\n\nValue on reset: 165"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum DMA_A {
11    #[doc = "165: DMA waiting cycle mode"]
12    WAITING_CYCLE = 165,
13    #[doc = "234: DMA handshake mode"]
14    HANDSHAKE = 234,
15}
16impl From<DMA_A> for u8 {
17    #[inline(always)]
18    fn from(variant: DMA_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for DMA_A {
23    type Ux = u8;
24}
25impl DMA_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<DMA_A> {
29        match self.bits {
30            165 => Some(DMA_A::WAITING_CYCLE),
31            234 => Some(DMA_A::HANDSHAKE),
32            _ => None,
33        }
34    }
35    #[doc = "DMA waiting cycle mode"]
36    #[inline(always)]
37    pub fn is_waiting_cycle(&self) -> bool {
38        *self == DMA_A::WAITING_CYCLE
39    }
40    #[doc = "DMA handshake mode"]
41    #[inline(always)]
42    pub fn is_handshake(&self) -> bool {
43        *self == DMA_A::HANDSHAKE
44    }
45}
46#[doc = "Field `dma` writer - Handshake Configuration"]
47pub type DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 8, DMA_A>;
48impl<'a, REG> DMA_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u8>,
52{
53    #[doc = "DMA waiting cycle mode"]
54    #[inline(always)]
55    pub fn waiting_cycle(self) -> &'a mut crate::W<REG> {
56        self.variant(DMA_A::WAITING_CYCLE)
57    }
58    #[doc = "DMA handshake mode"]
59    #[inline(always)]
60    pub fn handshake(self) -> &'a mut crate::W<REG> {
61        self.variant(DMA_A::HANDSHAKE)
62    }
63}
64impl R {
65    #[doc = "Bits 0:7 - Handshake Configuration"]
66    #[inline(always)]
67    pub fn dma(&self) -> DMA_R {
68        DMA_R::new((self.bits & 0xff) as u8)
69    }
70}
71impl W {
72    #[doc = "Bits 0:7 - Handshake Configuration"]
73    #[inline(always)]
74    #[must_use]
75    pub fn dma(&mut self) -> DMA_W<CIR_DMA_CTL_SPEC> {
76        DMA_W::new(self, 0)
77    }
78    #[doc = r" Writes raw bits to the register."]
79    #[doc = r""]
80    #[doc = r" # Safety"]
81    #[doc = r""]
82    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.bits = bits;
86        self
87    }
88}
89#[doc = "CIR DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_dma_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_dma_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
90pub struct CIR_DMA_CTL_SPEC;
91impl crate::RegisterSpec for CIR_DMA_CTL_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [`cir_dma_ctl::R`](R) reader structure"]
95impl crate::Readable for CIR_DMA_CTL_SPEC {}
96#[doc = "`write(|w| ..)` method takes [`cir_dma_ctl::W`](W) writer structure"]
97impl crate::Writable for CIR_DMA_CTL_SPEC {
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100}
101#[doc = "`reset()` method sets cir_dma_ctl to value 0xa5"]
102impl crate::Resettable for CIR_DMA_CTL_SPEC {
103    const RESET_VALUE: Self::Ux = 0xa5;
104}
d1_pac/cir_tx/cir_dma_ctl.rs

d1_pac/cir_tx/
cir_dma_ctl.rs
