d1_pac/ccu/
usb1_clk.rs

1#[doc = "Register `usb1_clk` reader"]
2pub type R = crate::R<USB1_CLK_SPEC>;
3#[doc = "Register `usb1_clk` writer"]
4pub type W = crate::W<USB1_CLK_SPEC>;
5#[doc = "Field `clk12m_sel` reader - OHCI 12M Source Select"]
6pub type CLK12M_SEL_R = crate::FieldReader<CLK12M_SEL_A>;
7#[doc = "OHCI 12M Source Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum CLK12M_SEL_A {
11    #[doc = "0: `0`"]
12    DIV_48M = 0,
13    #[doc = "1: `1`"]
14    DIV_24M = 1,
15    #[doc = "2: `10`"]
16    RTC_32K = 2,
17}
18impl From<CLK12M_SEL_A> for u8 {
19    #[inline(always)]
20    fn from(variant: CLK12M_SEL_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for CLK12M_SEL_A {
25    type Ux = u8;
26}
27impl CLK12M_SEL_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<CLK12M_SEL_A> {
31        match self.bits {
32            0 => Some(CLK12M_SEL_A::DIV_48M),
33            1 => Some(CLK12M_SEL_A::DIV_24M),
34            2 => Some(CLK12M_SEL_A::RTC_32K),
35            _ => None,
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_div_48m(&self) -> bool {
41        *self == CLK12M_SEL_A::DIV_48M
42    }
43    #[doc = "`1`"]
44    #[inline(always)]
45    pub fn is_div_24m(&self) -> bool {
46        *self == CLK12M_SEL_A::DIV_24M
47    }
48    #[doc = "`10`"]
49    #[inline(always)]
50    pub fn is_rtc_32k(&self) -> bool {
51        *self == CLK12M_SEL_A::RTC_32K
52    }
53}
54#[doc = "Field `clk12m_sel` writer - OHCI 12M Source Select"]
55pub type CLK12M_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CLK12M_SEL_A>;
56impl<'a, REG> CLK12M_SEL_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "`0`"]
62    #[inline(always)]
63    pub fn div_48m(self) -> &'a mut crate::W<REG> {
64        self.variant(CLK12M_SEL_A::DIV_48M)
65    }
66    #[doc = "`1`"]
67    #[inline(always)]
68    pub fn div_24m(self) -> &'a mut crate::W<REG> {
69        self.variant(CLK12M_SEL_A::DIV_24M)
70    }
71    #[doc = "`10`"]
72    #[inline(always)]
73    pub fn rtc_32k(self) -> &'a mut crate::W<REG> {
74        self.variant(CLK12M_SEL_A::RTC_32K)
75    }
76}
77#[doc = "Field `rstn` reader - PHY Reset"]
78pub type RSTN_R = crate::BitReader<RSTN_A>;
79#[doc = "PHY Reset\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81pub enum RSTN_A {
82    #[doc = "0: `0`"]
83    ASSERT = 0,
84    #[doc = "1: `1`"]
85    DEASSERT = 1,
86}
87impl From<RSTN_A> for bool {
88    #[inline(always)]
89    fn from(variant: RSTN_A) -> Self {
90        variant as u8 != 0
91    }
92}
93impl RSTN_R {
94    #[doc = "Get enumerated values variant"]
95    #[inline(always)]
96    pub const fn variant(&self) -> RSTN_A {
97        match self.bits {
98            false => RSTN_A::ASSERT,
99            true => RSTN_A::DEASSERT,
100        }
101    }
102    #[doc = "`0`"]
103    #[inline(always)]
104    pub fn is_assert(&self) -> bool {
105        *self == RSTN_A::ASSERT
106    }
107    #[doc = "`1`"]
108    #[inline(always)]
109    pub fn is_deassert(&self) -> bool {
110        *self == RSTN_A::DEASSERT
111    }
112}
113#[doc = "Field `rstn` writer - PHY Reset"]
114pub type RSTN_W<'a, REG> = crate::BitWriter<'a, REG, RSTN_A>;
115impl<'a, REG> RSTN_W<'a, REG>
116where
117    REG: crate::Writable + crate::RegisterSpec,
118{
119    #[doc = "`0`"]
120    #[inline(always)]
121    pub fn assert(self) -> &'a mut crate::W<REG> {
122        self.variant(RSTN_A::ASSERT)
123    }
124    #[doc = "`1`"]
125    #[inline(always)]
126    pub fn deassert(self) -> &'a mut crate::W<REG> {
127        self.variant(RSTN_A::DEASSERT)
128    }
129}
130#[doc = "Field `clken` reader - Gating Special Clock"]
131pub type CLKEN_R = crate::BitReader<CLKEN_A>;
132#[doc = "Gating Special Clock\n\nValue on reset: 0"]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134pub enum CLKEN_A {
135    #[doc = "0: `0`"]
136    OFF = 0,
137    #[doc = "1: `1`"]
138    ON = 1,
139}
140impl From<CLKEN_A> for bool {
141    #[inline(always)]
142    fn from(variant: CLKEN_A) -> Self {
143        variant as u8 != 0
144    }
145}
146impl CLKEN_R {
147    #[doc = "Get enumerated values variant"]
148    #[inline(always)]
149    pub const fn variant(&self) -> CLKEN_A {
150        match self.bits {
151            false => CLKEN_A::OFF,
152            true => CLKEN_A::ON,
153        }
154    }
155    #[doc = "`0`"]
156    #[inline(always)]
157    pub fn is_off(&self) -> bool {
158        *self == CLKEN_A::OFF
159    }
160    #[doc = "`1`"]
161    #[inline(always)]
162    pub fn is_on(&self) -> bool {
163        *self == CLKEN_A::ON
164    }
165}
166#[doc = "Field `clken` writer - Gating Special Clock"]
167pub type CLKEN_W<'a, REG> = crate::BitWriter<'a, REG, CLKEN_A>;
168impl<'a, REG> CLKEN_W<'a, REG>
169where
170    REG: crate::Writable + crate::RegisterSpec,
171{
172    #[doc = "`0`"]
173    #[inline(always)]
174    pub fn off(self) -> &'a mut crate::W<REG> {
175        self.variant(CLKEN_A::OFF)
176    }
177    #[doc = "`1`"]
178    #[inline(always)]
179    pub fn on(self) -> &'a mut crate::W<REG> {
180        self.variant(CLKEN_A::ON)
181    }
182}
183impl R {
184    #[doc = "Bits 24:25 - OHCI 12M Source Select"]
185    #[inline(always)]
186    pub fn clk12m_sel(&self) -> CLK12M_SEL_R {
187        CLK12M_SEL_R::new(((self.bits >> 24) & 3) as u8)
188    }
189    #[doc = "Bit 30 - PHY Reset"]
190    #[inline(always)]
191    pub fn rstn(&self) -> RSTN_R {
192        RSTN_R::new(((self.bits >> 30) & 1) != 0)
193    }
194    #[doc = "Bit 31 - Gating Special Clock"]
195    #[inline(always)]
196    pub fn clken(&self) -> CLKEN_R {
197        CLKEN_R::new(((self.bits >> 31) & 1) != 0)
198    }
199}
200impl W {
201    #[doc = "Bits 24:25 - OHCI 12M Source Select"]
202    #[inline(always)]
203    #[must_use]
204    pub fn clk12m_sel(&mut self) -> CLK12M_SEL_W<USB1_CLK_SPEC> {
205        CLK12M_SEL_W::new(self, 24)
206    }
207    #[doc = "Bit 30 - PHY Reset"]
208    #[inline(always)]
209    #[must_use]
210    pub fn rstn(&mut self) -> RSTN_W<USB1_CLK_SPEC> {
211        RSTN_W::new(self, 30)
212    }
213    #[doc = "Bit 31 - Gating Special Clock"]
214    #[inline(always)]
215    #[must_use]
216    pub fn clken(&mut self) -> CLKEN_W<USB1_CLK_SPEC> {
217        CLKEN_W::new(self, 31)
218    }
219    #[doc = r" Writes raw bits to the register."]
220    #[doc = r""]
221    #[doc = r" # Safety"]
222    #[doc = r""]
223    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
224    #[inline(always)]
225    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
226        self.bits = bits;
227        self
228    }
229}
230#[doc = "USB1 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb1_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb1_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
231pub struct USB1_CLK_SPEC;
232impl crate::RegisterSpec for USB1_CLK_SPEC {
233    type Ux = u32;
234}
235#[doc = "`read()` method returns [`usb1_clk::R`](R) reader structure"]
236impl crate::Readable for USB1_CLK_SPEC {}
237#[doc = "`write(|w| ..)` method takes [`usb1_clk::W`](W) writer structure"]
238impl crate::Writable for USB1_CLK_SPEC {
239    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241}
242#[doc = "`reset()` method sets usb1_clk to value 0"]
243impl crate::Resettable for USB1_CLK_SPEC {
244    const RESET_VALUE: Self::Ux = 0;
245}
d1_pac/ccu/usb1_clk.rs

d1_pac/ccu/
usb1_clk.rs
