d1_pac/ccu/
pll_lock_dbg_ctrl.rs

1#[doc = "Register `pll_lock_dbg_ctrl` reader"]
2pub type R = crate::R<PLL_LOCK_DBG_CTRL_SPEC>;
3#[doc = "Register `pll_lock_dbg_ctrl` writer"]
4pub type W = crate::W<PLL_LOCK_DBG_CTRL_SPEC>;
5#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
6pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
7#[doc = "Clock Source Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum CLK_SRC_SEL_A {
11    #[doc = "0: `0`"]
12    PLL_CPUX = 0,
13    #[doc = "1: `1`"]
14    PLL_DDR = 1,
15    #[doc = "2: `10`"]
16    PLL_PERI_2X = 2,
17    #[doc = "3: `11`"]
18    PLL_VIDEO0_4X = 3,
19    #[doc = "4: `100`"]
20    PLL_VIDEO1_4X = 4,
21    #[doc = "5: `101`"]
22    PLL_VE = 5,
23    #[doc = "6: `110`"]
24    PLL_AUDIO0 = 6,
25    #[doc = "7: `111`"]
26    PLL_AUDIO1 = 7,
27}
28impl From<CLK_SRC_SEL_A> for u8 {
29    #[inline(always)]
30    fn from(variant: CLK_SRC_SEL_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for CLK_SRC_SEL_A {
35    type Ux = u8;
36}
37impl CLK_SRC_SEL_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> CLK_SRC_SEL_A {
41        match self.bits {
42            0 => CLK_SRC_SEL_A::PLL_CPUX,
43            1 => CLK_SRC_SEL_A::PLL_DDR,
44            2 => CLK_SRC_SEL_A::PLL_PERI_2X,
45            3 => CLK_SRC_SEL_A::PLL_VIDEO0_4X,
46            4 => CLK_SRC_SEL_A::PLL_VIDEO1_4X,
47            5 => CLK_SRC_SEL_A::PLL_VE,
48            6 => CLK_SRC_SEL_A::PLL_AUDIO0,
49            7 => CLK_SRC_SEL_A::PLL_AUDIO1,
50            _ => unreachable!(),
51        }
52    }
53    #[doc = "`0`"]
54    #[inline(always)]
55    pub fn is_pll_cpux(&self) -> bool {
56        *self == CLK_SRC_SEL_A::PLL_CPUX
57    }
58    #[doc = "`1`"]
59    #[inline(always)]
60    pub fn is_pll_ddr(&self) -> bool {
61        *self == CLK_SRC_SEL_A::PLL_DDR
62    }
63    #[doc = "`10`"]
64    #[inline(always)]
65    pub fn is_pll_peri_2x(&self) -> bool {
66        *self == CLK_SRC_SEL_A::PLL_PERI_2X
67    }
68    #[doc = "`11`"]
69    #[inline(always)]
70    pub fn is_pll_video0_4x(&self) -> bool {
71        *self == CLK_SRC_SEL_A::PLL_VIDEO0_4X
72    }
73    #[doc = "`100`"]
74    #[inline(always)]
75    pub fn is_pll_video1_4x(&self) -> bool {
76        *self == CLK_SRC_SEL_A::PLL_VIDEO1_4X
77    }
78    #[doc = "`101`"]
79    #[inline(always)]
80    pub fn is_pll_ve(&self) -> bool {
81        *self == CLK_SRC_SEL_A::PLL_VE
82    }
83    #[doc = "`110`"]
84    #[inline(always)]
85    pub fn is_pll_audio0(&self) -> bool {
86        *self == CLK_SRC_SEL_A::PLL_AUDIO0
87    }
88    #[doc = "`111`"]
89    #[inline(always)]
90    pub fn is_pll_audio1(&self) -> bool {
91        *self == CLK_SRC_SEL_A::PLL_AUDIO1
92    }
93}
94#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
95pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, CLK_SRC_SEL_A>;
96impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99    REG::Ux: From<u8>,
100{
101    #[doc = "`0`"]
102    #[inline(always)]
103    pub fn pll_cpux(self) -> &'a mut crate::W<REG> {
104        self.variant(CLK_SRC_SEL_A::PLL_CPUX)
105    }
106    #[doc = "`1`"]
107    #[inline(always)]
108    pub fn pll_ddr(self) -> &'a mut crate::W<REG> {
109        self.variant(CLK_SRC_SEL_A::PLL_DDR)
110    }
111    #[doc = "`10`"]
112    #[inline(always)]
113    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
114        self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
115    }
116    #[doc = "`11`"]
117    #[inline(always)]
118    pub fn pll_video0_4x(self) -> &'a mut crate::W<REG> {
119        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_4X)
120    }
121    #[doc = "`100`"]
122    #[inline(always)]
123    pub fn pll_video1_4x(self) -> &'a mut crate::W<REG> {
124        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_4X)
125    }
126    #[doc = "`101`"]
127    #[inline(always)]
128    pub fn pll_ve(self) -> &'a mut crate::W<REG> {
129        self.variant(CLK_SRC_SEL_A::PLL_VE)
130    }
131    #[doc = "`110`"]
132    #[inline(always)]
133    pub fn pll_audio0(self) -> &'a mut crate::W<REG> {
134        self.variant(CLK_SRC_SEL_A::PLL_AUDIO0)
135    }
136    #[doc = "`111`"]
137    #[inline(always)]
138    pub fn pll_audio1(self) -> &'a mut crate::W<REG> {
139        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1)
140    }
141}
142#[doc = "Field `pll_lock_flag_en` reader - Debug Enable"]
143pub type PLL_LOCK_FLAG_EN_R = crate::BitReader<PLL_LOCK_FLAG_EN_A>;
144#[doc = "Debug Enable\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146pub enum PLL_LOCK_FLAG_EN_A {
147    #[doc = "0: `0`"]
148    DISABLE = 0,
149    #[doc = "1: `1`"]
150    ENABLE = 1,
151}
152impl From<PLL_LOCK_FLAG_EN_A> for bool {
153    #[inline(always)]
154    fn from(variant: PLL_LOCK_FLAG_EN_A) -> Self {
155        variant as u8 != 0
156    }
157}
158impl PLL_LOCK_FLAG_EN_R {
159    #[doc = "Get enumerated values variant"]
160    #[inline(always)]
161    pub const fn variant(&self) -> PLL_LOCK_FLAG_EN_A {
162        match self.bits {
163            false => PLL_LOCK_FLAG_EN_A::DISABLE,
164            true => PLL_LOCK_FLAG_EN_A::ENABLE,
165        }
166    }
167    #[doc = "`0`"]
168    #[inline(always)]
169    pub fn is_disable(&self) -> bool {
170        *self == PLL_LOCK_FLAG_EN_A::DISABLE
171    }
172    #[doc = "`1`"]
173    #[inline(always)]
174    pub fn is_enable(&self) -> bool {
175        *self == PLL_LOCK_FLAG_EN_A::ENABLE
176    }
177}
178#[doc = "Field `pll_lock_flag_en` writer - Debug Enable"]
179pub type PLL_LOCK_FLAG_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LOCK_FLAG_EN_A>;
180impl<'a, REG> PLL_LOCK_FLAG_EN_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    #[doc = "`0`"]
185    #[inline(always)]
186    pub fn disable(self) -> &'a mut crate::W<REG> {
187        self.variant(PLL_LOCK_FLAG_EN_A::DISABLE)
188    }
189    #[doc = "`1`"]
190    #[inline(always)]
191    pub fn enable(self) -> &'a mut crate::W<REG> {
192        self.variant(PLL_LOCK_FLAG_EN_A::ENABLE)
193    }
194}
195impl R {
196    #[doc = "Bits 20:22 - Clock Source Select"]
197    #[inline(always)]
198    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
199        CLK_SRC_SEL_R::new(((self.bits >> 20) & 7) as u8)
200    }
201    #[doc = "Bit 31 - Debug Enable"]
202    #[inline(always)]
203    pub fn pll_lock_flag_en(&self) -> PLL_LOCK_FLAG_EN_R {
204        PLL_LOCK_FLAG_EN_R::new(((self.bits >> 31) & 1) != 0)
205    }
206}
207impl W {
208    #[doc = "Bits 20:22 - Clock Source Select"]
209    #[inline(always)]
210    #[must_use]
211    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<PLL_LOCK_DBG_CTRL_SPEC> {
212        CLK_SRC_SEL_W::new(self, 20)
213    }
214    #[doc = "Bit 31 - Debug Enable"]
215    #[inline(always)]
216    #[must_use]
217    pub fn pll_lock_flag_en(&mut self) -> PLL_LOCK_FLAG_EN_W<PLL_LOCK_DBG_CTRL_SPEC> {
218        PLL_LOCK_FLAG_EN_W::new(self, 31)
219    }
220    #[doc = r" Writes raw bits to the register."]
221    #[doc = r""]
222    #[doc = r" # Safety"]
223    #[doc = r""]
224    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
225    #[inline(always)]
226    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
227        self.bits = bits;
228        self
229    }
230}
231#[doc = "PLL Lock Debug Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_lock_dbg_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_lock_dbg_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
232pub struct PLL_LOCK_DBG_CTRL_SPEC;
233impl crate::RegisterSpec for PLL_LOCK_DBG_CTRL_SPEC {
234    type Ux = u32;
235}
236#[doc = "`read()` method returns [`pll_lock_dbg_ctrl::R`](R) reader structure"]
237impl crate::Readable for PLL_LOCK_DBG_CTRL_SPEC {}
238#[doc = "`write(|w| ..)` method takes [`pll_lock_dbg_ctrl::W`](W) writer structure"]
239impl crate::Writable for PLL_LOCK_DBG_CTRL_SPEC {
240    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
242}
243#[doc = "`reset()` method sets pll_lock_dbg_ctrl to value 0"]
244impl crate::Resettable for PLL_LOCK_DBG_CTRL_SPEC {
245    const RESET_VALUE: Self::Ux = 0;
246}
d1_pac/ccu/pll_lock_dbg_ctrl.rs

d1_pac/ccu/
pll_lock_dbg_ctrl.rs
