d1_pac/ccu/
pll_cpu_ctrl.rs

1#[doc = "Register `pll_cpu_ctrl` reader"]
2pub type R = crate::R<PLL_CPU_CTRL_SPEC>;
3#[doc = "Register `pll_cpu_ctrl` writer"]
4pub type W = crate::W<PLL_CPU_CTRL_SPEC>;
5#[doc = "Field `pll_m` reader - PLL M"]
6pub type PLL_M_R = crate::FieldReader;
7#[doc = "Field `pll_m` writer - PLL M"]
8pub type PLL_M_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `pll_lock_mdsel` reader - PLL Lock Level"]
10pub type PLL_LOCK_MDSEL_R = crate::BitReader<PLL_LOCK_MDSEL_A>;
11#[doc = "PLL Lock Level\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum PLL_LOCK_MDSEL_A {
14    #[doc = "0: `0`"]
15    CC_24_26 = 0,
16    #[doc = "1: `1`"]
17    CC_23_27 = 1,
18}
19impl From<PLL_LOCK_MDSEL_A> for bool {
20    #[inline(always)]
21    fn from(variant: PLL_LOCK_MDSEL_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl PLL_LOCK_MDSEL_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> PLL_LOCK_MDSEL_A {
29        match self.bits {
30            false => PLL_LOCK_MDSEL_A::CC_24_26,
31            true => PLL_LOCK_MDSEL_A::CC_23_27,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_cc_24_26(&self) -> bool {
37        *self == PLL_LOCK_MDSEL_A::CC_24_26
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_cc_23_27(&self) -> bool {
42        *self == PLL_LOCK_MDSEL_A::CC_23_27
43    }
44}
45#[doc = "Field `pll_lock_mdsel` writer - PLL Lock Level"]
46pub type PLL_LOCK_MDSEL_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LOCK_MDSEL_A>;
47impl<'a, REG> PLL_LOCK_MDSEL_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn cc_24_26(self) -> &'a mut crate::W<REG> {
54        self.variant(PLL_LOCK_MDSEL_A::CC_24_26)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn cc_23_27(self) -> &'a mut crate::W<REG> {
59        self.variant(PLL_LOCK_MDSEL_A::CC_23_27)
60    }
61}
62#[doc = "Field `pll_unlock_mdsel` reader - PLL Unlock Level"]
63pub type PLL_UNLOCK_MDSEL_R = crate::FieldReader<PLL_UNLOCK_MDSEL_A>;
64#[doc = "PLL Unlock Level\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum PLL_UNLOCK_MDSEL_A {
68    #[doc = "0: `0`"]
69    CC_21_29 = 0,
70    #[doc = "1: `1`"]
71    CC_22_28 = 1,
72    #[doc = "2: `10`"]
73    CC_20_30 = 2,
74}
75impl From<PLL_UNLOCK_MDSEL_A> for u8 {
76    #[inline(always)]
77    fn from(variant: PLL_UNLOCK_MDSEL_A) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for PLL_UNLOCK_MDSEL_A {
82    type Ux = u8;
83}
84impl PLL_UNLOCK_MDSEL_R {
85    #[doc = "Get enumerated values variant"]
86    #[inline(always)]
87    pub const fn variant(&self) -> Option<PLL_UNLOCK_MDSEL_A> {
88        match self.bits {
89            0 => Some(PLL_UNLOCK_MDSEL_A::CC_21_29),
90            1 => Some(PLL_UNLOCK_MDSEL_A::CC_22_28),
91            2 => Some(PLL_UNLOCK_MDSEL_A::CC_20_30),
92            _ => None,
93        }
94    }
95    #[doc = "`0`"]
96    #[inline(always)]
97    pub fn is_cc_21_29(&self) -> bool {
98        *self == PLL_UNLOCK_MDSEL_A::CC_21_29
99    }
100    #[doc = "`1`"]
101    #[inline(always)]
102    pub fn is_cc_22_28(&self) -> bool {
103        *self == PLL_UNLOCK_MDSEL_A::CC_22_28
104    }
105    #[doc = "`10`"]
106    #[inline(always)]
107    pub fn is_cc_20_30(&self) -> bool {
108        *self == PLL_UNLOCK_MDSEL_A::CC_20_30
109    }
110}
111#[doc = "Field `pll_unlock_mdsel` writer - PLL Unlock Level"]
112pub type PLL_UNLOCK_MDSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLL_UNLOCK_MDSEL_A>;
113impl<'a, REG> PLL_UNLOCK_MDSEL_W<'a, REG>
114where
115    REG: crate::Writable + crate::RegisterSpec,
116    REG::Ux: From<u8>,
117{
118    #[doc = "`0`"]
119    #[inline(always)]
120    pub fn cc_21_29(self) -> &'a mut crate::W<REG> {
121        self.variant(PLL_UNLOCK_MDSEL_A::CC_21_29)
122    }
123    #[doc = "`1`"]
124    #[inline(always)]
125    pub fn cc_22_28(self) -> &'a mut crate::W<REG> {
126        self.variant(PLL_UNLOCK_MDSEL_A::CC_22_28)
127    }
128    #[doc = "`10`"]
129    #[inline(always)]
130    pub fn cc_20_30(self) -> &'a mut crate::W<REG> {
131        self.variant(PLL_UNLOCK_MDSEL_A::CC_20_30)
132    }
133}
134#[doc = "Field `pll_n` reader - PLL N"]
135pub type PLL_N_R = crate::FieldReader;
136#[doc = "Field `pll_n` writer - PLL N"]
137pub type PLL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
138#[doc = "Field `pll_lock_time` reader - PLL Lock Time"]
139pub type PLL_LOCK_TIME_R = crate::FieldReader;
140#[doc = "Field `pll_lock_time` writer - PLL Lock Time"]
141pub type PLL_LOCK_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
142#[doc = "Field `pll_output_gate` reader - PLL Output Gating Enable"]
143pub type PLL_OUTPUT_GATE_R = crate::BitReader<PLL_OUTPUT_GATE_A>;
144#[doc = "PLL Output Gating Enable\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146pub enum PLL_OUTPUT_GATE_A {
147    #[doc = "0: `0`"]
148    DISABLE = 0,
149    #[doc = "1: `1`"]
150    ENABLE = 1,
151}
152impl From<PLL_OUTPUT_GATE_A> for bool {
153    #[inline(always)]
154    fn from(variant: PLL_OUTPUT_GATE_A) -> Self {
155        variant as u8 != 0
156    }
157}
158impl PLL_OUTPUT_GATE_R {
159    #[doc = "Get enumerated values variant"]
160    #[inline(always)]
161    pub const fn variant(&self) -> PLL_OUTPUT_GATE_A {
162        match self.bits {
163            false => PLL_OUTPUT_GATE_A::DISABLE,
164            true => PLL_OUTPUT_GATE_A::ENABLE,
165        }
166    }
167    #[doc = "`0`"]
168    #[inline(always)]
169    pub fn is_disable(&self) -> bool {
170        *self == PLL_OUTPUT_GATE_A::DISABLE
171    }
172    #[doc = "`1`"]
173    #[inline(always)]
174    pub fn is_enable(&self) -> bool {
175        *self == PLL_OUTPUT_GATE_A::ENABLE
176    }
177}
178#[doc = "Field `pll_output_gate` writer - PLL Output Gating Enable"]
179pub type PLL_OUTPUT_GATE_W<'a, REG> = crate::BitWriter<'a, REG, PLL_OUTPUT_GATE_A>;
180impl<'a, REG> PLL_OUTPUT_GATE_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    #[doc = "`0`"]
185    #[inline(always)]
186    pub fn disable(self) -> &'a mut crate::W<REG> {
187        self.variant(PLL_OUTPUT_GATE_A::DISABLE)
188    }
189    #[doc = "`1`"]
190    #[inline(always)]
191    pub fn enable(self) -> &'a mut crate::W<REG> {
192        self.variant(PLL_OUTPUT_GATE_A::ENABLE)
193    }
194}
195#[doc = "Field `lock` reader - PLL Lock Status"]
196pub type LOCK_R = crate::BitReader<LOCK_A>;
197#[doc = "PLL Lock Status\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum LOCK_A {
200    #[doc = "0: `0`"]
201    UNLOCKED = 0,
202    #[doc = "1: `1`"]
203    LOCKED = 1,
204}
205impl From<LOCK_A> for bool {
206    #[inline(always)]
207    fn from(variant: LOCK_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl LOCK_R {
212    #[doc = "Get enumerated values variant"]
213    #[inline(always)]
214    pub const fn variant(&self) -> LOCK_A {
215        match self.bits {
216            false => LOCK_A::UNLOCKED,
217            true => LOCK_A::LOCKED,
218        }
219    }
220    #[doc = "`0`"]
221    #[inline(always)]
222    pub fn is_unlocked(&self) -> bool {
223        *self == LOCK_A::UNLOCKED
224    }
225    #[doc = "`1`"]
226    #[inline(always)]
227    pub fn is_locked(&self) -> bool {
228        *self == LOCK_A::LOCKED
229    }
230}
231#[doc = "Field `lock_enable` reader - Lock Enable"]
232pub type LOCK_ENABLE_R = crate::BitReader<LOCK_ENABLE_A>;
233#[doc = "Lock Enable\n\nValue on reset: 0"]
234#[derive(Clone, Copy, Debug, PartialEq, Eq)]
235pub enum LOCK_ENABLE_A {
236    #[doc = "0: `0`"]
237    DISABLE = 0,
238    #[doc = "1: `1`"]
239    ENABLE = 1,
240}
241impl From<LOCK_ENABLE_A> for bool {
242    #[inline(always)]
243    fn from(variant: LOCK_ENABLE_A) -> Self {
244        variant as u8 != 0
245    }
246}
247impl LOCK_ENABLE_R {
248    #[doc = "Get enumerated values variant"]
249    #[inline(always)]
250    pub const fn variant(&self) -> LOCK_ENABLE_A {
251        match self.bits {
252            false => LOCK_ENABLE_A::DISABLE,
253            true => LOCK_ENABLE_A::ENABLE,
254        }
255    }
256    #[doc = "`0`"]
257    #[inline(always)]
258    pub fn is_disable(&self) -> bool {
259        *self == LOCK_ENABLE_A::DISABLE
260    }
261    #[doc = "`1`"]
262    #[inline(always)]
263    pub fn is_enable(&self) -> bool {
264        *self == LOCK_ENABLE_A::ENABLE
265    }
266}
267#[doc = "Field `lock_enable` writer - Lock Enable"]
268pub type LOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, LOCK_ENABLE_A>;
269impl<'a, REG> LOCK_ENABLE_W<'a, REG>
270where
271    REG: crate::Writable + crate::RegisterSpec,
272{
273    #[doc = "`0`"]
274    #[inline(always)]
275    pub fn disable(self) -> &'a mut crate::W<REG> {
276        self.variant(LOCK_ENABLE_A::DISABLE)
277    }
278    #[doc = "`1`"]
279    #[inline(always)]
280    pub fn enable(self) -> &'a mut crate::W<REG> {
281        self.variant(LOCK_ENABLE_A::ENABLE)
282    }
283}
284#[doc = "Field `pll_ldo_en` reader - LDO Enable"]
285pub type PLL_LDO_EN_R = crate::BitReader<PLL_LDO_EN_A>;
286#[doc = "LDO Enable\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq, Eq)]
288pub enum PLL_LDO_EN_A {
289    #[doc = "0: `0`"]
290    DISABLE = 0,
291    #[doc = "1: `1`"]
292    ENABLE = 1,
293}
294impl From<PLL_LDO_EN_A> for bool {
295    #[inline(always)]
296    fn from(variant: PLL_LDO_EN_A) -> Self {
297        variant as u8 != 0
298    }
299}
300impl PLL_LDO_EN_R {
301    #[doc = "Get enumerated values variant"]
302    #[inline(always)]
303    pub const fn variant(&self) -> PLL_LDO_EN_A {
304        match self.bits {
305            false => PLL_LDO_EN_A::DISABLE,
306            true => PLL_LDO_EN_A::ENABLE,
307        }
308    }
309    #[doc = "`0`"]
310    #[inline(always)]
311    pub fn is_disable(&self) -> bool {
312        *self == PLL_LDO_EN_A::DISABLE
313    }
314    #[doc = "`1`"]
315    #[inline(always)]
316    pub fn is_enable(&self) -> bool {
317        *self == PLL_LDO_EN_A::ENABLE
318    }
319}
320#[doc = "Field `pll_ldo_en` writer - LDO Enable"]
321pub type PLL_LDO_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LDO_EN_A>;
322impl<'a, REG> PLL_LDO_EN_W<'a, REG>
323where
324    REG: crate::Writable + crate::RegisterSpec,
325{
326    #[doc = "`0`"]
327    #[inline(always)]
328    pub fn disable(self) -> &'a mut crate::W<REG> {
329        self.variant(PLL_LDO_EN_A::DISABLE)
330    }
331    #[doc = "`1`"]
332    #[inline(always)]
333    pub fn enable(self) -> &'a mut crate::W<REG> {
334        self.variant(PLL_LDO_EN_A::ENABLE)
335    }
336}
337#[doc = "Field `pll_en` reader - PLL Enable"]
338pub type PLL_EN_R = crate::BitReader<PLL_EN_A>;
339#[doc = "PLL Enable\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum PLL_EN_A {
342    #[doc = "0: `0`"]
343    DISABLE = 0,
344    #[doc = "1: `1`"]
345    ENABLE = 1,
346}
347impl From<PLL_EN_A> for bool {
348    #[inline(always)]
349    fn from(variant: PLL_EN_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl PLL_EN_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub const fn variant(&self) -> PLL_EN_A {
357        match self.bits {
358            false => PLL_EN_A::DISABLE,
359            true => PLL_EN_A::ENABLE,
360        }
361    }
362    #[doc = "`0`"]
363    #[inline(always)]
364    pub fn is_disable(&self) -> bool {
365        *self == PLL_EN_A::DISABLE
366    }
367    #[doc = "`1`"]
368    #[inline(always)]
369    pub fn is_enable(&self) -> bool {
370        *self == PLL_EN_A::ENABLE
371    }
372}
373#[doc = "Field `pll_en` writer - PLL Enable"]
374pub type PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_EN_A>;
375impl<'a, REG> PLL_EN_W<'a, REG>
376where
377    REG: crate::Writable + crate::RegisterSpec,
378{
379    #[doc = "`0`"]
380    #[inline(always)]
381    pub fn disable(self) -> &'a mut crate::W<REG> {
382        self.variant(PLL_EN_A::DISABLE)
383    }
384    #[doc = "`1`"]
385    #[inline(always)]
386    pub fn enable(self) -> &'a mut crate::W<REG> {
387        self.variant(PLL_EN_A::ENABLE)
388    }
389}
390impl R {
391    #[doc = "Bits 0:1 - PLL M"]
392    #[inline(always)]
393    pub fn pll_m(&self) -> PLL_M_R {
394        PLL_M_R::new((self.bits & 3) as u8)
395    }
396    #[doc = "Bit 5 - PLL Lock Level"]
397    #[inline(always)]
398    pub fn pll_lock_mdsel(&self) -> PLL_LOCK_MDSEL_R {
399        PLL_LOCK_MDSEL_R::new(((self.bits >> 5) & 1) != 0)
400    }
401    #[doc = "Bits 6:7 - PLL Unlock Level"]
402    #[inline(always)]
403    pub fn pll_unlock_mdsel(&self) -> PLL_UNLOCK_MDSEL_R {
404        PLL_UNLOCK_MDSEL_R::new(((self.bits >> 6) & 3) as u8)
405    }
406    #[doc = "Bits 8:15 - PLL N"]
407    #[inline(always)]
408    pub fn pll_n(&self) -> PLL_N_R {
409        PLL_N_R::new(((self.bits >> 8) & 0xff) as u8)
410    }
411    #[doc = "Bits 24:26 - PLL Lock Time"]
412    #[inline(always)]
413    pub fn pll_lock_time(&self) -> PLL_LOCK_TIME_R {
414        PLL_LOCK_TIME_R::new(((self.bits >> 24) & 7) as u8)
415    }
416    #[doc = "Bit 27 - PLL Output Gating Enable"]
417    #[inline(always)]
418    pub fn pll_output_gate(&self) -> PLL_OUTPUT_GATE_R {
419        PLL_OUTPUT_GATE_R::new(((self.bits >> 27) & 1) != 0)
420    }
421    #[doc = "Bit 28 - PLL Lock Status"]
422    #[inline(always)]
423    pub fn lock(&self) -> LOCK_R {
424        LOCK_R::new(((self.bits >> 28) & 1) != 0)
425    }
426    #[doc = "Bit 29 - Lock Enable"]
427    #[inline(always)]
428    pub fn lock_enable(&self) -> LOCK_ENABLE_R {
429        LOCK_ENABLE_R::new(((self.bits >> 29) & 1) != 0)
430    }
431    #[doc = "Bit 30 - LDO Enable"]
432    #[inline(always)]
433    pub fn pll_ldo_en(&self) -> PLL_LDO_EN_R {
434        PLL_LDO_EN_R::new(((self.bits >> 30) & 1) != 0)
435    }
436    #[doc = "Bit 31 - PLL Enable"]
437    #[inline(always)]
438    pub fn pll_en(&self) -> PLL_EN_R {
439        PLL_EN_R::new(((self.bits >> 31) & 1) != 0)
440    }
441}
442impl W {
443    #[doc = "Bits 0:1 - PLL M"]
444    #[inline(always)]
445    #[must_use]
446    pub fn pll_m(&mut self) -> PLL_M_W<PLL_CPU_CTRL_SPEC> {
447        PLL_M_W::new(self, 0)
448    }
449    #[doc = "Bit 5 - PLL Lock Level"]
450    #[inline(always)]
451    #[must_use]
452    pub fn pll_lock_mdsel(&mut self) -> PLL_LOCK_MDSEL_W<PLL_CPU_CTRL_SPEC> {
453        PLL_LOCK_MDSEL_W::new(self, 5)
454    }
455    #[doc = "Bits 6:7 - PLL Unlock Level"]
456    #[inline(always)]
457    #[must_use]
458    pub fn pll_unlock_mdsel(&mut self) -> PLL_UNLOCK_MDSEL_W<PLL_CPU_CTRL_SPEC> {
459        PLL_UNLOCK_MDSEL_W::new(self, 6)
460    }
461    #[doc = "Bits 8:15 - PLL N"]
462    #[inline(always)]
463    #[must_use]
464    pub fn pll_n(&mut self) -> PLL_N_W<PLL_CPU_CTRL_SPEC> {
465        PLL_N_W::new(self, 8)
466    }
467    #[doc = "Bits 24:26 - PLL Lock Time"]
468    #[inline(always)]
469    #[must_use]
470    pub fn pll_lock_time(&mut self) -> PLL_LOCK_TIME_W<PLL_CPU_CTRL_SPEC> {
471        PLL_LOCK_TIME_W::new(self, 24)
472    }
473    #[doc = "Bit 27 - PLL Output Gating Enable"]
474    #[inline(always)]
475    #[must_use]
476    pub fn pll_output_gate(&mut self) -> PLL_OUTPUT_GATE_W<PLL_CPU_CTRL_SPEC> {
477        PLL_OUTPUT_GATE_W::new(self, 27)
478    }
479    #[doc = "Bit 29 - Lock Enable"]
480    #[inline(always)]
481    #[must_use]
482    pub fn lock_enable(&mut self) -> LOCK_ENABLE_W<PLL_CPU_CTRL_SPEC> {
483        LOCK_ENABLE_W::new(self, 29)
484    }
485    #[doc = "Bit 30 - LDO Enable"]
486    #[inline(always)]
487    #[must_use]
488    pub fn pll_ldo_en(&mut self) -> PLL_LDO_EN_W<PLL_CPU_CTRL_SPEC> {
489        PLL_LDO_EN_W::new(self, 30)
490    }
491    #[doc = "Bit 31 - PLL Enable"]
492    #[inline(always)]
493    #[must_use]
494    pub fn pll_en(&mut self) -> PLL_EN_W<PLL_CPU_CTRL_SPEC> {
495        PLL_EN_W::new(self, 31)
496    }
497    #[doc = r" Writes raw bits to the register."]
498    #[doc = r""]
499    #[doc = r" # Safety"]
500    #[doc = r""]
501    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
502    #[inline(always)]
503    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
504        self.bits = bits;
505        self
506    }
507}
508#[doc = "PLL_CPU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
509pub struct PLL_CPU_CTRL_SPEC;
510impl crate::RegisterSpec for PLL_CPU_CTRL_SPEC {
511    type Ux = u32;
512}
513#[doc = "`read()` method returns [`pll_cpu_ctrl::R`](R) reader structure"]
514impl crate::Readable for PLL_CPU_CTRL_SPEC {}
515#[doc = "`write(|w| ..)` method takes [`pll_cpu_ctrl::W`](W) writer structure"]
516impl crate::Writable for PLL_CPU_CTRL_SPEC {
517    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
518    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
519}
520#[doc = "`reset()` method sets pll_cpu_ctrl to value 0"]
521impl crate::Resettable for PLL_CPU_CTRL_SPEC {
522    const RESET_VALUE: Self::Ux = 0;
523}
d1_pac/ccu/pll_cpu_ctrl.rs

d1_pac/ccu/
pll_cpu_ctrl.rs
