d1_pac/ccu/
csi_master_clk.rs

1#[doc = "Register `csi_master_clk` reader"]
2pub type R = crate::R<CSI_MASTER_CLK_SPEC>;
3#[doc = "Register `csi_master_clk` writer"]
4pub type W = crate::W<CSI_MASTER_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
10pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
11#[doc = "Clock Source Select\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum CLK_SRC_SEL_A {
15    #[doc = "0: `0`"]
16    HOSC = 0,
17    #[doc = "1: `1`"]
18    PLL_PERI_1X = 1,
19    #[doc = "2: `10`"]
20    PLL_VIDEO0_1X = 2,
21    #[doc = "3: `11`"]
22    PLL_VIDEO1_1X = 3,
23    #[doc = "4: `100`"]
24    PLL_AUDIO1_DIV2 = 4,
25    #[doc = "5: `101`"]
26    PLL_AUDIO1_DIV5 = 5,
27}
28impl From<CLK_SRC_SEL_A> for u8 {
29    #[inline(always)]
30    fn from(variant: CLK_SRC_SEL_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for CLK_SRC_SEL_A {
35    type Ux = u8;
36}
37impl CLK_SRC_SEL_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
41        match self.bits {
42            0 => Some(CLK_SRC_SEL_A::HOSC),
43            1 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
44            2 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_1X),
45            3 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_1X),
46            4 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
47            5 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5),
48            _ => None,
49        }
50    }
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn is_hosc(&self) -> bool {
54        *self == CLK_SRC_SEL_A::HOSC
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn is_pll_peri_1x(&self) -> bool {
59        *self == CLK_SRC_SEL_A::PLL_PERI_1X
60    }
61    #[doc = "`10`"]
62    #[inline(always)]
63    pub fn is_pll_video0_1x(&self) -> bool {
64        *self == CLK_SRC_SEL_A::PLL_VIDEO0_1X
65    }
66    #[doc = "`11`"]
67    #[inline(always)]
68    pub fn is_pll_video1_1x(&self) -> bool {
69        *self == CLK_SRC_SEL_A::PLL_VIDEO1_1X
70    }
71    #[doc = "`100`"]
72    #[inline(always)]
73    pub fn is_pll_audio1_div2(&self) -> bool {
74        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
75    }
76    #[doc = "`101`"]
77    #[inline(always)]
78    pub fn is_pll_audio1_div5(&self) -> bool {
79        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV5
80    }
81}
82#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
83pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
84impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87    REG::Ux: From<u8>,
88{
89    #[doc = "`0`"]
90    #[inline(always)]
91    pub fn hosc(self) -> &'a mut crate::W<REG> {
92        self.variant(CLK_SRC_SEL_A::HOSC)
93    }
94    #[doc = "`1`"]
95    #[inline(always)]
96    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
97        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
98    }
99    #[doc = "`10`"]
100    #[inline(always)]
101    pub fn pll_video0_1x(self) -> &'a mut crate::W<REG> {
102        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_1X)
103    }
104    #[doc = "`11`"]
105    #[inline(always)]
106    pub fn pll_video1_1x(self) -> &'a mut crate::W<REG> {
107        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_1X)
108    }
109    #[doc = "`100`"]
110    #[inline(always)]
111    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
112        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
113    }
114    #[doc = "`101`"]
115    #[inline(always)]
116    pub fn pll_audio1_div5(self) -> &'a mut crate::W<REG> {
117        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5)
118    }
119}
120#[doc = "Field `clk_gating` reader - Gating Clock"]
121pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
122#[doc = "Gating Clock\n\nValue on reset: 0"]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum CLK_GATING_A {
125    #[doc = "0: `0`"]
126    OFF = 0,
127    #[doc = "1: `1`"]
128    ON = 1,
129}
130impl From<CLK_GATING_A> for bool {
131    #[inline(always)]
132    fn from(variant: CLK_GATING_A) -> Self {
133        variant as u8 != 0
134    }
135}
136impl CLK_GATING_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> CLK_GATING_A {
140        match self.bits {
141            false => CLK_GATING_A::OFF,
142            true => CLK_GATING_A::ON,
143        }
144    }
145    #[doc = "`0`"]
146    #[inline(always)]
147    pub fn is_off(&self) -> bool {
148        *self == CLK_GATING_A::OFF
149    }
150    #[doc = "`1`"]
151    #[inline(always)]
152    pub fn is_on(&self) -> bool {
153        *self == CLK_GATING_A::ON
154    }
155}
156#[doc = "Field `clk_gating` writer - Gating Clock"]
157pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
158impl<'a, REG> CLK_GATING_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    #[doc = "`0`"]
163    #[inline(always)]
164    pub fn off(self) -> &'a mut crate::W<REG> {
165        self.variant(CLK_GATING_A::OFF)
166    }
167    #[doc = "`1`"]
168    #[inline(always)]
169    pub fn on(self) -> &'a mut crate::W<REG> {
170        self.variant(CLK_GATING_A::ON)
171    }
172}
173impl R {
174    #[doc = "Bits 0:4 - Factor M"]
175    #[inline(always)]
176    pub fn factor_m(&self) -> FACTOR_M_R {
177        FACTOR_M_R::new((self.bits & 0x1f) as u8)
178    }
179    #[doc = "Bits 24:26 - Clock Source Select"]
180    #[inline(always)]
181    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
182        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
183    }
184    #[doc = "Bit 31 - Gating Clock"]
185    #[inline(always)]
186    pub fn clk_gating(&self) -> CLK_GATING_R {
187        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
188    }
189}
190impl W {
191    #[doc = "Bits 0:4 - Factor M"]
192    #[inline(always)]
193    #[must_use]
194    pub fn factor_m(&mut self) -> FACTOR_M_W<CSI_MASTER_CLK_SPEC> {
195        FACTOR_M_W::new(self, 0)
196    }
197    #[doc = "Bits 24:26 - Clock Source Select"]
198    #[inline(always)]
199    #[must_use]
200    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<CSI_MASTER_CLK_SPEC> {
201        CLK_SRC_SEL_W::new(self, 24)
202    }
203    #[doc = "Bit 31 - Gating Clock"]
204    #[inline(always)]
205    #[must_use]
206    pub fn clk_gating(&mut self) -> CLK_GATING_W<CSI_MASTER_CLK_SPEC> {
207        CLK_GATING_W::new(self, 31)
208    }
209    #[doc = r" Writes raw bits to the register."]
210    #[doc = r""]
211    #[doc = r" # Safety"]
212    #[doc = r""]
213    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
214    #[inline(always)]
215    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
216        self.bits = bits;
217        self
218    }
219}
220#[doc = "CSI Master Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_master_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_master_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
221pub struct CSI_MASTER_CLK_SPEC;
222impl crate::RegisterSpec for CSI_MASTER_CLK_SPEC {
223    type Ux = u32;
224}
225#[doc = "`read()` method returns [`csi_master_clk::R`](R) reader structure"]
226impl crate::Readable for CSI_MASTER_CLK_SPEC {}
227#[doc = "`write(|w| ..)` method takes [`csi_master_clk::W`](W) writer structure"]
228impl crate::Writable for CSI_MASTER_CLK_SPEC {
229    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
230    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
231}
232#[doc = "`reset()` method sets csi_master_clk to value 0"]
233impl crate::Resettable for CSI_MASTER_CLK_SPEC {
234    const RESET_VALUE: Self::Ux = 0;
235}
d1_pac/ccu/csi_master_clk.rs

d1_pac/ccu/
csi_master_clk.rs
