d1_pac/ccu/
cpu_axi_cfg.rs

1#[doc = "Register `cpu_axi_cfg` reader"]
2pub type R = crate::R<CPU_AXI_CFG_SPEC>;
3#[doc = "Register `cpu_axi_cfg` writer"]
4pub type W = crate::W<CPU_AXI_CFG_SPEC>;
5#[doc = "Field `cpu_div1` reader - Factor M"]
6pub type CPU_DIV1_R = crate::FieldReader;
7#[doc = "Field `cpu_div1` writer - Factor M"]
8pub type CPU_DIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `cpu_div2` reader - Factor N"]
10pub type CPU_DIV2_R = crate::FieldReader;
11#[doc = "Field `cpu_div2` writer - Factor N"]
12pub type CPU_DIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `pll_cpu_out_ext_divp` reader - PLL Output External Divider P"]
14pub type PLL_CPU_OUT_EXT_DIVP_R = crate::FieldReader<PLL_CPU_OUT_EXT_DIVP_A>;
15#[doc = "PLL Output External Divider P\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum PLL_CPU_OUT_EXT_DIVP_A {
19    #[doc = "0: `0`"]
20    P1 = 0,
21    #[doc = "1: `1`"]
22    P2 = 1,
23    #[doc = "2: `10`"]
24    P4 = 2,
25}
26impl From<PLL_CPU_OUT_EXT_DIVP_A> for u8 {
27    #[inline(always)]
28    fn from(variant: PLL_CPU_OUT_EXT_DIVP_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for PLL_CPU_OUT_EXT_DIVP_A {
33    type Ux = u8;
34}
35impl PLL_CPU_OUT_EXT_DIVP_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<PLL_CPU_OUT_EXT_DIVP_A> {
39        match self.bits {
40            0 => Some(PLL_CPU_OUT_EXT_DIVP_A::P1),
41            1 => Some(PLL_CPU_OUT_EXT_DIVP_A::P2),
42            2 => Some(PLL_CPU_OUT_EXT_DIVP_A::P4),
43            _ => None,
44        }
45    }
46    #[doc = "`0`"]
47    #[inline(always)]
48    pub fn is_p1(&self) -> bool {
49        *self == PLL_CPU_OUT_EXT_DIVP_A::P1
50    }
51    #[doc = "`1`"]
52    #[inline(always)]
53    pub fn is_p2(&self) -> bool {
54        *self == PLL_CPU_OUT_EXT_DIVP_A::P2
55    }
56    #[doc = "`10`"]
57    #[inline(always)]
58    pub fn is_p4(&self) -> bool {
59        *self == PLL_CPU_OUT_EXT_DIVP_A::P4
60    }
61}
62#[doc = "Field `pll_cpu_out_ext_divp` writer - PLL Output External Divider P"]
63pub type PLL_CPU_OUT_EXT_DIVP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLL_CPU_OUT_EXT_DIVP_A>;
64impl<'a, REG> PLL_CPU_OUT_EXT_DIVP_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn p1(self) -> &'a mut crate::W<REG> {
72        self.variant(PLL_CPU_OUT_EXT_DIVP_A::P1)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn p2(self) -> &'a mut crate::W<REG> {
77        self.variant(PLL_CPU_OUT_EXT_DIVP_A::P2)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn p4(self) -> &'a mut crate::W<REG> {
82        self.variant(PLL_CPU_OUT_EXT_DIVP_A::P4)
83    }
84}
85#[doc = "Field `cpu_clk_sel` reader - Clock Source Select"]
86pub type CPU_CLK_SEL_R = crate::FieldReader<CPU_CLK_SEL_A>;
87#[doc = "Clock Source Select\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89#[repr(u8)]
90pub enum CPU_CLK_SEL_A {
91    #[doc = "0: `0`"]
92    HOSC = 0,
93    #[doc = "1: `1`"]
94    CLK32K = 1,
95    #[doc = "2: `10`"]
96    CLK16M_RC = 2,
97    #[doc = "3: `11`"]
98    PLL_CPU_P = 3,
99    #[doc = "4: `100`"]
100    PLL_PERI_1X = 4,
101    #[doc = "5: `101`"]
102    PLL_PERI_2X = 5,
103    #[doc = "6: `110`"]
104    PLL_PERI_800M = 6,
105}
106impl From<CPU_CLK_SEL_A> for u8 {
107    #[inline(always)]
108    fn from(variant: CPU_CLK_SEL_A) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for CPU_CLK_SEL_A {
113    type Ux = u8;
114}
115impl CPU_CLK_SEL_R {
116    #[doc = "Get enumerated values variant"]
117    #[inline(always)]
118    pub const fn variant(&self) -> Option<CPU_CLK_SEL_A> {
119        match self.bits {
120            0 => Some(CPU_CLK_SEL_A::HOSC),
121            1 => Some(CPU_CLK_SEL_A::CLK32K),
122            2 => Some(CPU_CLK_SEL_A::CLK16M_RC),
123            3 => Some(CPU_CLK_SEL_A::PLL_CPU_P),
124            4 => Some(CPU_CLK_SEL_A::PLL_PERI_1X),
125            5 => Some(CPU_CLK_SEL_A::PLL_PERI_2X),
126            6 => Some(CPU_CLK_SEL_A::PLL_PERI_800M),
127            _ => None,
128        }
129    }
130    #[doc = "`0`"]
131    #[inline(always)]
132    pub fn is_hosc(&self) -> bool {
133        *self == CPU_CLK_SEL_A::HOSC
134    }
135    #[doc = "`1`"]
136    #[inline(always)]
137    pub fn is_clk32k(&self) -> bool {
138        *self == CPU_CLK_SEL_A::CLK32K
139    }
140    #[doc = "`10`"]
141    #[inline(always)]
142    pub fn is_clk16m_rc(&self) -> bool {
143        *self == CPU_CLK_SEL_A::CLK16M_RC
144    }
145    #[doc = "`11`"]
146    #[inline(always)]
147    pub fn is_pll_cpu_p(&self) -> bool {
148        *self == CPU_CLK_SEL_A::PLL_CPU_P
149    }
150    #[doc = "`100`"]
151    #[inline(always)]
152    pub fn is_pll_peri_1x(&self) -> bool {
153        *self == CPU_CLK_SEL_A::PLL_PERI_1X
154    }
155    #[doc = "`101`"]
156    #[inline(always)]
157    pub fn is_pll_peri_2x(&self) -> bool {
158        *self == CPU_CLK_SEL_A::PLL_PERI_2X
159    }
160    #[doc = "`110`"]
161    #[inline(always)]
162    pub fn is_pll_peri_800m(&self) -> bool {
163        *self == CPU_CLK_SEL_A::PLL_PERI_800M
164    }
165}
166#[doc = "Field `cpu_clk_sel` writer - Clock Source Select"]
167pub type CPU_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CPU_CLK_SEL_A>;
168impl<'a, REG> CPU_CLK_SEL_W<'a, REG>
169where
170    REG: crate::Writable + crate::RegisterSpec,
171    REG::Ux: From<u8>,
172{
173    #[doc = "`0`"]
174    #[inline(always)]
175    pub fn hosc(self) -> &'a mut crate::W<REG> {
176        self.variant(CPU_CLK_SEL_A::HOSC)
177    }
178    #[doc = "`1`"]
179    #[inline(always)]
180    pub fn clk32k(self) -> &'a mut crate::W<REG> {
181        self.variant(CPU_CLK_SEL_A::CLK32K)
182    }
183    #[doc = "`10`"]
184    #[inline(always)]
185    pub fn clk16m_rc(self) -> &'a mut crate::W<REG> {
186        self.variant(CPU_CLK_SEL_A::CLK16M_RC)
187    }
188    #[doc = "`11`"]
189    #[inline(always)]
190    pub fn pll_cpu_p(self) -> &'a mut crate::W<REG> {
191        self.variant(CPU_CLK_SEL_A::PLL_CPU_P)
192    }
193    #[doc = "`100`"]
194    #[inline(always)]
195    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
196        self.variant(CPU_CLK_SEL_A::PLL_PERI_1X)
197    }
198    #[doc = "`101`"]
199    #[inline(always)]
200    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
201        self.variant(CPU_CLK_SEL_A::PLL_PERI_2X)
202    }
203    #[doc = "`110`"]
204    #[inline(always)]
205    pub fn pll_peri_800m(self) -> &'a mut crate::W<REG> {
206        self.variant(CPU_CLK_SEL_A::PLL_PERI_800M)
207    }
208}
209impl R {
210    #[doc = "Bits 0:1 - Factor M"]
211    #[inline(always)]
212    pub fn cpu_div1(&self) -> CPU_DIV1_R {
213        CPU_DIV1_R::new((self.bits & 3) as u8)
214    }
215    #[doc = "Bits 8:9 - Factor N"]
216    #[inline(always)]
217    pub fn cpu_div2(&self) -> CPU_DIV2_R {
218        CPU_DIV2_R::new(((self.bits >> 8) & 3) as u8)
219    }
220    #[doc = "Bits 16:17 - PLL Output External Divider P"]
221    #[inline(always)]
222    pub fn pll_cpu_out_ext_divp(&self) -> PLL_CPU_OUT_EXT_DIVP_R {
223        PLL_CPU_OUT_EXT_DIVP_R::new(((self.bits >> 16) & 3) as u8)
224    }
225    #[doc = "Bits 24:26 - Clock Source Select"]
226    #[inline(always)]
227    pub fn cpu_clk_sel(&self) -> CPU_CLK_SEL_R {
228        CPU_CLK_SEL_R::new(((self.bits >> 24) & 7) as u8)
229    }
230}
231impl W {
232    #[doc = "Bits 0:1 - Factor M"]
233    #[inline(always)]
234    #[must_use]
235    pub fn cpu_div1(&mut self) -> CPU_DIV1_W<CPU_AXI_CFG_SPEC> {
236        CPU_DIV1_W::new(self, 0)
237    }
238    #[doc = "Bits 8:9 - Factor N"]
239    #[inline(always)]
240    #[must_use]
241    pub fn cpu_div2(&mut self) -> CPU_DIV2_W<CPU_AXI_CFG_SPEC> {
242        CPU_DIV2_W::new(self, 8)
243    }
244    #[doc = "Bits 16:17 - PLL Output External Divider P"]
245    #[inline(always)]
246    #[must_use]
247    pub fn pll_cpu_out_ext_divp(&mut self) -> PLL_CPU_OUT_EXT_DIVP_W<CPU_AXI_CFG_SPEC> {
248        PLL_CPU_OUT_EXT_DIVP_W::new(self, 16)
249    }
250    #[doc = "Bits 24:26 - Clock Source Select"]
251    #[inline(always)]
252    #[must_use]
253    pub fn cpu_clk_sel(&mut self) -> CPU_CLK_SEL_W<CPU_AXI_CFG_SPEC> {
254        CPU_CLK_SEL_W::new(self, 24)
255    }
256    #[doc = r" Writes raw bits to the register."]
257    #[doc = r""]
258    #[doc = r" # Safety"]
259    #[doc = r""]
260    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
261    #[inline(always)]
262    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
263        self.bits = bits;
264        self
265    }
266}
267#[doc = "CPU_AXI Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_axi_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_axi_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
268pub struct CPU_AXI_CFG_SPEC;
269impl crate::RegisterSpec for CPU_AXI_CFG_SPEC {
270    type Ux = u32;
271}
272#[doc = "`read()` method returns [`cpu_axi_cfg::R`](R) reader structure"]
273impl crate::Readable for CPU_AXI_CFG_SPEC {}
274#[doc = "`write(|w| ..)` method takes [`cpu_axi_cfg::W`](W) writer structure"]
275impl crate::Writable for CPU_AXI_CFG_SPEC {
276    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
277    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
278}
279#[doc = "`reset()` method sets cpu_axi_cfg to value 0"]
280impl crate::Resettable for CPU_AXI_CFG_SPEC {
281    const RESET_VALUE: Self::Ux = 0;
282}
d1_pac/ccu/cpu_axi_cfg.rs

d1_pac/ccu/
cpu_axi_cfg.rs
