d1_pac/ccu/
ccu_fan_gate.rs

1#[doc = "Register `ccu_fan_gate` reader"]
2pub type R = crate::R<CCU_FAN_GATE_SPEC>;
3#[doc = "Register `ccu_fan_gate` writer"]
4pub type W = crate::W<CCU_FAN_GATE_SPEC>;
5#[doc = "Field `clk24m_en` reader - Gating for CLK24M"]
6pub type CLK24M_EN_R = crate::BitReader<CLK24M_EN_A>;
7#[doc = "Gating for CLK24M\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CLK24M_EN_A {
10    #[doc = "0: `0`"]
11    OFF = 0,
12    #[doc = "1: `1`"]
13    ON = 1,
14}
15impl From<CLK24M_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: CLK24M_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CLK24M_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CLK24M_EN_A {
25        match self.bits {
26            false => CLK24M_EN_A::OFF,
27            true => CLK24M_EN_A::ON,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_off(&self) -> bool {
33        *self == CLK24M_EN_A::OFF
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_on(&self) -> bool {
38        *self == CLK24M_EN_A::ON
39    }
40}
41#[doc = "Field `clk24m_en` writer - Gating for CLK24M"]
42pub type CLK24M_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK24M_EN_A>;
43impl<'a, REG> CLK24M_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn off(self) -> &'a mut crate::W<REG> {
50        self.variant(CLK24M_EN_A::OFF)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn on(self) -> &'a mut crate::W<REG> {
55        self.variant(CLK24M_EN_A::ON)
56    }
57}
58#[doc = "Field `clk12m_en` reader - Gating for CLK12M"]
59pub type CLK12M_EN_R = crate::BitReader<CLK12M_EN_A>;
60#[doc = "Gating for CLK12M\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CLK12M_EN_A {
63    #[doc = "0: `0`"]
64    OFF = 0,
65    #[doc = "1: `1`"]
66    ON = 1,
67}
68impl From<CLK12M_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: CLK12M_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl CLK12M_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> CLK12M_EN_A {
78        match self.bits {
79            false => CLK12M_EN_A::OFF,
80            true => CLK12M_EN_A::ON,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_off(&self) -> bool {
86        *self == CLK12M_EN_A::OFF
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_on(&self) -> bool {
91        *self == CLK12M_EN_A::ON
92    }
93}
94#[doc = "Field `clk12m_en` writer - Gating for CLK12M"]
95pub type CLK12M_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK12M_EN_A>;
96impl<'a, REG> CLK12M_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn off(self) -> &'a mut crate::W<REG> {
103        self.variant(CLK12M_EN_A::OFF)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn on(self) -> &'a mut crate::W<REG> {
108        self.variant(CLK12M_EN_A::ON)
109    }
110}
111#[doc = "Field `clk16m_en` reader - Gating for CLK16M"]
112pub type CLK16M_EN_R = crate::BitReader<CLK16M_EN_A>;
113#[doc = "Gating for CLK16M\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CLK16M_EN_A {
116    #[doc = "0: `0`"]
117    OFF = 0,
118    #[doc = "1: `1`"]
119    ON = 1,
120}
121impl From<CLK16M_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: CLK16M_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl CLK16M_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> CLK16M_EN_A {
131        match self.bits {
132            false => CLK16M_EN_A::OFF,
133            true => CLK16M_EN_A::ON,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_off(&self) -> bool {
139        *self == CLK16M_EN_A::OFF
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_on(&self) -> bool {
144        *self == CLK16M_EN_A::ON
145    }
146}
147#[doc = "Field `clk16m_en` writer - Gating for CLK16M"]
148pub type CLK16M_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK16M_EN_A>;
149impl<'a, REG> CLK16M_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn off(self) -> &'a mut crate::W<REG> {
156        self.variant(CLK16M_EN_A::OFF)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn on(self) -> &'a mut crate::W<REG> {
161        self.variant(CLK16M_EN_A::ON)
162    }
163}
164#[doc = "Field `clk25m_en` reader - Gating for CLK25M"]
165pub type CLK25M_EN_R = crate::BitReader<CLK25M_EN_A>;
166#[doc = "Gating for CLK25M\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum CLK25M_EN_A {
169    #[doc = "0: `0`"]
170    OFF = 0,
171    #[doc = "1: `1`"]
172    ON = 1,
173}
174impl From<CLK25M_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: CLK25M_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl CLK25M_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> CLK25M_EN_A {
184        match self.bits {
185            false => CLK25M_EN_A::OFF,
186            true => CLK25M_EN_A::ON,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_off(&self) -> bool {
192        *self == CLK25M_EN_A::OFF
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_on(&self) -> bool {
197        *self == CLK25M_EN_A::ON
198    }
199}
200#[doc = "Field `clk25m_en` writer - Gating for CLK25M"]
201pub type CLK25M_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK25M_EN_A>;
202impl<'a, REG> CLK25M_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn off(self) -> &'a mut crate::W<REG> {
209        self.variant(CLK25M_EN_A::OFF)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn on(self) -> &'a mut crate::W<REG> {
214        self.variant(CLK25M_EN_A::ON)
215    }
216}
217#[doc = "Field `clk32k_en` reader - Gating for CLK32K"]
218pub type CLK32K_EN_R = crate::BitReader<CLK32K_EN_A>;
219#[doc = "Gating for CLK32K\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum CLK32K_EN_A {
222    #[doc = "0: `0`"]
223    OFF = 0,
224    #[doc = "1: `1`"]
225    ON = 1,
226}
227impl From<CLK32K_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: CLK32K_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl CLK32K_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> CLK32K_EN_A {
237        match self.bits {
238            false => CLK32K_EN_A::OFF,
239            true => CLK32K_EN_A::ON,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_off(&self) -> bool {
245        *self == CLK32K_EN_A::OFF
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_on(&self) -> bool {
250        *self == CLK32K_EN_A::ON
251    }
252}
253#[doc = "Field `clk32k_en` writer - Gating for CLK32K"]
254pub type CLK32K_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK32K_EN_A>;
255impl<'a, REG> CLK32K_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn off(self) -> &'a mut crate::W<REG> {
262        self.variant(CLK32K_EN_A::OFF)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn on(self) -> &'a mut crate::W<REG> {
267        self.variant(CLK32K_EN_A::ON)
268    }
269}
270impl R {
271    #[doc = "Bit 0 - Gating for CLK24M"]
272    #[inline(always)]
273    pub fn clk24m_en(&self) -> CLK24M_EN_R {
274        CLK24M_EN_R::new((self.bits & 1) != 0)
275    }
276    #[doc = "Bit 1 - Gating for CLK12M"]
277    #[inline(always)]
278    pub fn clk12m_en(&self) -> CLK12M_EN_R {
279        CLK12M_EN_R::new(((self.bits >> 1) & 1) != 0)
280    }
281    #[doc = "Bit 2 - Gating for CLK16M"]
282    #[inline(always)]
283    pub fn clk16m_en(&self) -> CLK16M_EN_R {
284        CLK16M_EN_R::new(((self.bits >> 2) & 1) != 0)
285    }
286    #[doc = "Bit 3 - Gating for CLK25M"]
287    #[inline(always)]
288    pub fn clk25m_en(&self) -> CLK25M_EN_R {
289        CLK25M_EN_R::new(((self.bits >> 3) & 1) != 0)
290    }
291    #[doc = "Bit 4 - Gating for CLK32K"]
292    #[inline(always)]
293    pub fn clk32k_en(&self) -> CLK32K_EN_R {
294        CLK32K_EN_R::new(((self.bits >> 4) & 1) != 0)
295    }
296}
297impl W {
298    #[doc = "Bit 0 - Gating for CLK24M"]
299    #[inline(always)]
300    #[must_use]
301    pub fn clk24m_en(&mut self) -> CLK24M_EN_W<CCU_FAN_GATE_SPEC> {
302        CLK24M_EN_W::new(self, 0)
303    }
304    #[doc = "Bit 1 - Gating for CLK12M"]
305    #[inline(always)]
306    #[must_use]
307    pub fn clk12m_en(&mut self) -> CLK12M_EN_W<CCU_FAN_GATE_SPEC> {
308        CLK12M_EN_W::new(self, 1)
309    }
310    #[doc = "Bit 2 - Gating for CLK16M"]
311    #[inline(always)]
312    #[must_use]
313    pub fn clk16m_en(&mut self) -> CLK16M_EN_W<CCU_FAN_GATE_SPEC> {
314        CLK16M_EN_W::new(self, 2)
315    }
316    #[doc = "Bit 3 - Gating for CLK25M"]
317    #[inline(always)]
318    #[must_use]
319    pub fn clk25m_en(&mut self) -> CLK25M_EN_W<CCU_FAN_GATE_SPEC> {
320        CLK25M_EN_W::new(self, 3)
321    }
322    #[doc = "Bit 4 - Gating for CLK32K"]
323    #[inline(always)]
324    #[must_use]
325    pub fn clk32k_en(&mut self) -> CLK32K_EN_W<CCU_FAN_GATE_SPEC> {
326        CLK32K_EN_W::new(self, 4)
327    }
328    #[doc = r" Writes raw bits to the register."]
329    #[doc = r""]
330    #[doc = r" # Safety"]
331    #[doc = r""]
332    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
333    #[inline(always)]
334    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
335        self.bits = bits;
336        self
337    }
338}
339#[doc = "CCU FANOUT CLOCK GATE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_fan_gate::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_fan_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
340pub struct CCU_FAN_GATE_SPEC;
341impl crate::RegisterSpec for CCU_FAN_GATE_SPEC {
342    type Ux = u32;
343}
344#[doc = "`read()` method returns [`ccu_fan_gate::R`](R) reader structure"]
345impl crate::Readable for CCU_FAN_GATE_SPEC {}
346#[doc = "`write(|w| ..)` method takes [`ccu_fan_gate::W`](W) writer structure"]
347impl crate::Writable for CCU_FAN_GATE_SPEC {
348    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
349    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
350}
351#[doc = "`reset()` method sets ccu_fan_gate to value 0"]
352impl crate::Resettable for CCU_FAN_GATE_SPEC {
353    const RESET_VALUE: Self::Ux = 0;
354}
d1_pac/ccu/ccu_fan_gate.rs

d1_pac/ccu/
ccu_fan_gate.rs
