d1_pac/audio_codec/
dac.rs

1#[doc = "Register `dac` reader"]
2pub type R = crate::R<DAC_SPEC>;
3#[doc = "Register `dac` writer"]
4pub type W = crate::W<DAC_SPEC>;
5#[doc = "Field `lineout_vol_ctrl` reader - LINEOUT Volume Control.\n\nTotal 30 level from 0x1F to 0x02 with the volume 0 dB to -43.5 dB, -1.5 dB/step, mute when 00000 or 00001"]
6pub type LINEOUT_VOL_CTRL_R = crate::FieldReader;
7#[doc = "Field `lineout_vol_ctrl` writer - LINEOUT Volume Control.\n\nTotal 30 level from 0x1F to 0x02 with the volume 0 dB to -43.5 dB, -1.5 dB/step, mute when 00000 or 00001"]
8pub type LINEOUT_VOL_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `lineoutr_diffen` reader - Right Channel LINEOUT Output Control"]
10pub type LINEOUTR_DIFFEN_R = crate::BitReader<LINEOUTR_DIFFEN_A>;
11#[doc = "Right Channel LINEOUT Output Control\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum LINEOUTR_DIFFEN_A {
14    #[doc = "0: `0`"]
15    SINGLE = 0,
16    #[doc = "1: `1`"]
17    DIFFERENTIAL = 1,
18}
19impl From<LINEOUTR_DIFFEN_A> for bool {
20    #[inline(always)]
21    fn from(variant: LINEOUTR_DIFFEN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl LINEOUTR_DIFFEN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> LINEOUTR_DIFFEN_A {
29        match self.bits {
30            false => LINEOUTR_DIFFEN_A::SINGLE,
31            true => LINEOUTR_DIFFEN_A::DIFFERENTIAL,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_single(&self) -> bool {
37        *self == LINEOUTR_DIFFEN_A::SINGLE
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_differential(&self) -> bool {
42        *self == LINEOUTR_DIFFEN_A::DIFFERENTIAL
43    }
44}
45#[doc = "Field `lineoutr_diffen` writer - Right Channel LINEOUT Output Control"]
46pub type LINEOUTR_DIFFEN_W<'a, REG> = crate::BitWriter<'a, REG, LINEOUTR_DIFFEN_A>;
47impl<'a, REG> LINEOUTR_DIFFEN_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn single(self) -> &'a mut crate::W<REG> {
54        self.variant(LINEOUTR_DIFFEN_A::SINGLE)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn differential(self) -> &'a mut crate::W<REG> {
59        self.variant(LINEOUTR_DIFFEN_A::DIFFERENTIAL)
60    }
61}
62#[doc = "Field `lineoutl_diffen` reader - Left Channel LINEOUT Output Control"]
63pub type LINEOUTL_DIFFEN_R = crate::BitReader<LINEOUTL_DIFFEN_A>;
64#[doc = "Left Channel LINEOUT Output Control\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum LINEOUTL_DIFFEN_A {
67    #[doc = "0: `0`"]
68    SINGLE = 0,
69    #[doc = "1: `1`"]
70    DIFFERENTIAL = 1,
71}
72impl From<LINEOUTL_DIFFEN_A> for bool {
73    #[inline(always)]
74    fn from(variant: LINEOUTL_DIFFEN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl LINEOUTL_DIFFEN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> LINEOUTL_DIFFEN_A {
82        match self.bits {
83            false => LINEOUTL_DIFFEN_A::SINGLE,
84            true => LINEOUTL_DIFFEN_A::DIFFERENTIAL,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_single(&self) -> bool {
90        *self == LINEOUTL_DIFFEN_A::SINGLE
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_differential(&self) -> bool {
95        *self == LINEOUTL_DIFFEN_A::DIFFERENTIAL
96    }
97}
98#[doc = "Field `lineoutl_diffen` writer - Left Channel LINEOUT Output Control"]
99pub type LINEOUTL_DIFFEN_W<'a, REG> = crate::BitWriter<'a, REG, LINEOUTL_DIFFEN_A>;
100impl<'a, REG> LINEOUTL_DIFFEN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn single(self) -> &'a mut crate::W<REG> {
107        self.variant(LINEOUTL_DIFFEN_A::SINGLE)
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn differential(self) -> &'a mut crate::W<REG> {
112        self.variant(LINEOUTL_DIFFEN_A::DIFFERENTIAL)
113    }
114}
115#[doc = "Field `rmute` reader - DACR to Right Channel LINEOUT Mute Control"]
116pub type RMUTE_R = crate::BitReader<RMUTE_A>;
117#[doc = "DACR to Right Channel LINEOUT Mute Control\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum RMUTE_A {
120    #[doc = "0: `0`"]
121    MUTE = 0,
122    #[doc = "1: `1`"]
123    UNMUTE = 1,
124}
125impl From<RMUTE_A> for bool {
126    #[inline(always)]
127    fn from(variant: RMUTE_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl RMUTE_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> RMUTE_A {
135        match self.bits {
136            false => RMUTE_A::MUTE,
137            true => RMUTE_A::UNMUTE,
138        }
139    }
140    #[doc = "`0`"]
141    #[inline(always)]
142    pub fn is_mute(&self) -> bool {
143        *self == RMUTE_A::MUTE
144    }
145    #[doc = "`1`"]
146    #[inline(always)]
147    pub fn is_unmute(&self) -> bool {
148        *self == RMUTE_A::UNMUTE
149    }
150}
151#[doc = "Field `rmute` writer - DACR to Right Channel LINEOUT Mute Control"]
152pub type RMUTE_W<'a, REG> = crate::BitWriter<'a, REG, RMUTE_A>;
153impl<'a, REG> RMUTE_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "`0`"]
158    #[inline(always)]
159    pub fn mute(self) -> &'a mut crate::W<REG> {
160        self.variant(RMUTE_A::MUTE)
161    }
162    #[doc = "`1`"]
163    #[inline(always)]
164    pub fn unmute(self) -> &'a mut crate::W<REG> {
165        self.variant(RMUTE_A::UNMUTE)
166    }
167}
168#[doc = "Field `lineoutren` reader - Right Channel LINEOUT Enable"]
169pub type LINEOUTREN_R = crate::BitReader<LINEOUTREN_A>;
170#[doc = "Right Channel LINEOUT Enable\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172pub enum LINEOUTREN_A {
173    #[doc = "0: `0`"]
174    DISABLE = 0,
175    #[doc = "1: `1`"]
176    ENABLE = 1,
177}
178impl From<LINEOUTREN_A> for bool {
179    #[inline(always)]
180    fn from(variant: LINEOUTREN_A) -> Self {
181        variant as u8 != 0
182    }
183}
184impl LINEOUTREN_R {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> LINEOUTREN_A {
188        match self.bits {
189            false => LINEOUTREN_A::DISABLE,
190            true => LINEOUTREN_A::ENABLE,
191        }
192    }
193    #[doc = "`0`"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == LINEOUTREN_A::DISABLE
197    }
198    #[doc = "`1`"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == LINEOUTREN_A::ENABLE
202    }
203}
204#[doc = "Field `lineoutren` writer - Right Channel LINEOUT Enable"]
205pub type LINEOUTREN_W<'a, REG> = crate::BitWriter<'a, REG, LINEOUTREN_A>;
206impl<'a, REG> LINEOUTREN_W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "`0`"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(LINEOUTREN_A::DISABLE)
214    }
215    #[doc = "`1`"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(LINEOUTREN_A::ENABLE)
219    }
220}
221#[doc = "Field `lmute` reader - DACL to Left Channel LINEOUT Mute Control"]
222pub type LMUTE_R = crate::BitReader<LMUTE_A>;
223#[doc = "DACL to Left Channel LINEOUT Mute Control\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225pub enum LMUTE_A {
226    #[doc = "0: `0`"]
227    MUTE = 0,
228    #[doc = "1: `1`"]
229    UNMUTE = 1,
230}
231impl From<LMUTE_A> for bool {
232    #[inline(always)]
233    fn from(variant: LMUTE_A) -> Self {
234        variant as u8 != 0
235    }
236}
237impl LMUTE_R {
238    #[doc = "Get enumerated values variant"]
239    #[inline(always)]
240    pub const fn variant(&self) -> LMUTE_A {
241        match self.bits {
242            false => LMUTE_A::MUTE,
243            true => LMUTE_A::UNMUTE,
244        }
245    }
246    #[doc = "`0`"]
247    #[inline(always)]
248    pub fn is_mute(&self) -> bool {
249        *self == LMUTE_A::MUTE
250    }
251    #[doc = "`1`"]
252    #[inline(always)]
253    pub fn is_unmute(&self) -> bool {
254        *self == LMUTE_A::UNMUTE
255    }
256}
257#[doc = "Field `lmute` writer - DACL to Left Channel LINEOUT Mute Control"]
258pub type LMUTE_W<'a, REG> = crate::BitWriter<'a, REG, LMUTE_A>;
259impl<'a, REG> LMUTE_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    #[doc = "`0`"]
264    #[inline(always)]
265    pub fn mute(self) -> &'a mut crate::W<REG> {
266        self.variant(LMUTE_A::MUTE)
267    }
268    #[doc = "`1`"]
269    #[inline(always)]
270    pub fn unmute(self) -> &'a mut crate::W<REG> {
271        self.variant(LMUTE_A::UNMUTE)
272    }
273}
274#[doc = "Field `lineoutlen` reader - Left Channel LINEOUT Enable"]
275pub type LINEOUTLEN_R = crate::BitReader<LINEOUTLEN_A>;
276#[doc = "Left Channel LINEOUT Enable\n\nValue on reset: 0"]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum LINEOUTLEN_A {
279    #[doc = "0: `0`"]
280    DISABLE = 0,
281    #[doc = "1: `1`"]
282    ENABLE = 1,
283}
284impl From<LINEOUTLEN_A> for bool {
285    #[inline(always)]
286    fn from(variant: LINEOUTLEN_A) -> Self {
287        variant as u8 != 0
288    }
289}
290impl LINEOUTLEN_R {
291    #[doc = "Get enumerated values variant"]
292    #[inline(always)]
293    pub const fn variant(&self) -> LINEOUTLEN_A {
294        match self.bits {
295            false => LINEOUTLEN_A::DISABLE,
296            true => LINEOUTLEN_A::ENABLE,
297        }
298    }
299    #[doc = "`0`"]
300    #[inline(always)]
301    pub fn is_disable(&self) -> bool {
302        *self == LINEOUTLEN_A::DISABLE
303    }
304    #[doc = "`1`"]
305    #[inline(always)]
306    pub fn is_enable(&self) -> bool {
307        *self == LINEOUTLEN_A::ENABLE
308    }
309}
310#[doc = "Field `lineoutlen` writer - Left Channel LINEOUT Enable"]
311pub type LINEOUTLEN_W<'a, REG> = crate::BitWriter<'a, REG, LINEOUTLEN_A>;
312impl<'a, REG> LINEOUTLEN_W<'a, REG>
313where
314    REG: crate::Writable + crate::RegisterSpec,
315{
316    #[doc = "`0`"]
317    #[inline(always)]
318    pub fn disable(self) -> &'a mut crate::W<REG> {
319        self.variant(LINEOUTLEN_A::DISABLE)
320    }
321    #[doc = "`1`"]
322    #[inline(always)]
323    pub fn enable(self) -> &'a mut crate::W<REG> {
324        self.variant(LINEOUTLEN_A::ENABLE)
325    }
326}
327#[doc = "Field `dacr_en` reader - DACR Enable"]
328pub type DACR_EN_R = crate::BitReader<DACR_EN_A>;
329#[doc = "DACR Enable\n\nValue on reset: 0"]
330#[derive(Clone, Copy, Debug, PartialEq, Eq)]
331pub enum DACR_EN_A {
332    #[doc = "0: `0`"]
333    DISABLE = 0,
334    #[doc = "1: `1`"]
335    ENABLE = 1,
336}
337impl From<DACR_EN_A> for bool {
338    #[inline(always)]
339    fn from(variant: DACR_EN_A) -> Self {
340        variant as u8 != 0
341    }
342}
343impl DACR_EN_R {
344    #[doc = "Get enumerated values variant"]
345    #[inline(always)]
346    pub const fn variant(&self) -> DACR_EN_A {
347        match self.bits {
348            false => DACR_EN_A::DISABLE,
349            true => DACR_EN_A::ENABLE,
350        }
351    }
352    #[doc = "`0`"]
353    #[inline(always)]
354    pub fn is_disable(&self) -> bool {
355        *self == DACR_EN_A::DISABLE
356    }
357    #[doc = "`1`"]
358    #[inline(always)]
359    pub fn is_enable(&self) -> bool {
360        *self == DACR_EN_A::ENABLE
361    }
362}
363#[doc = "Field `dacr_en` writer - DACR Enable"]
364pub type DACR_EN_W<'a, REG> = crate::BitWriter<'a, REG, DACR_EN_A>;
365impl<'a, REG> DACR_EN_W<'a, REG>
366where
367    REG: crate::Writable + crate::RegisterSpec,
368{
369    #[doc = "`0`"]
370    #[inline(always)]
371    pub fn disable(self) -> &'a mut crate::W<REG> {
372        self.variant(DACR_EN_A::DISABLE)
373    }
374    #[doc = "`1`"]
375    #[inline(always)]
376    pub fn enable(self) -> &'a mut crate::W<REG> {
377        self.variant(DACR_EN_A::ENABLE)
378    }
379}
380#[doc = "Field `dacl_en` reader - DACL Enable"]
381pub type DACL_EN_R = crate::BitReader<DACL_EN_A>;
382#[doc = "DACL Enable\n\nValue on reset: 0"]
383#[derive(Clone, Copy, Debug, PartialEq, Eq)]
384pub enum DACL_EN_A {
385    #[doc = "0: `0`"]
386    DISABLE = 0,
387    #[doc = "1: `1`"]
388    ENABLE = 1,
389}
390impl From<DACL_EN_A> for bool {
391    #[inline(always)]
392    fn from(variant: DACL_EN_A) -> Self {
393        variant as u8 != 0
394    }
395}
396impl DACL_EN_R {
397    #[doc = "Get enumerated values variant"]
398    #[inline(always)]
399    pub const fn variant(&self) -> DACL_EN_A {
400        match self.bits {
401            false => DACL_EN_A::DISABLE,
402            true => DACL_EN_A::ENABLE,
403        }
404    }
405    #[doc = "`0`"]
406    #[inline(always)]
407    pub fn is_disable(&self) -> bool {
408        *self == DACL_EN_A::DISABLE
409    }
410    #[doc = "`1`"]
411    #[inline(always)]
412    pub fn is_enable(&self) -> bool {
413        *self == DACL_EN_A::ENABLE
414    }
415}
416#[doc = "Field `dacl_en` writer - DACL Enable"]
417pub type DACL_EN_W<'a, REG> = crate::BitWriter<'a, REG, DACL_EN_A>;
418impl<'a, REG> DACL_EN_W<'a, REG>
419where
420    REG: crate::Writable + crate::RegisterSpec,
421{
422    #[doc = "`0`"]
423    #[inline(always)]
424    pub fn disable(self) -> &'a mut crate::W<REG> {
425        self.variant(DACL_EN_A::DISABLE)
426    }
427    #[doc = "`1`"]
428    #[inline(always)]
429    pub fn enable(self) -> &'a mut crate::W<REG> {
430        self.variant(DACL_EN_A::ENABLE)
431    }
432}
433#[doc = "Field `iopdacs` reader - OPDAC L/R Bias Current Select"]
434pub type IOPDACS_R = crate::FieldReader<IOPDACS_A>;
435#[doc = "OPDAC L/R Bias Current Select\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq, Eq)]
437#[repr(u8)]
438pub enum IOPDACS_A {
439    #[doc = "0: `0`"]
440    C6U = 0,
441    #[doc = "1: `1`"]
442    C7U = 1,
443    #[doc = "2: `10`"]
444    C8U = 2,
445    #[doc = "3: `11`"]
446    C9U = 3,
447}
448impl From<IOPDACS_A> for u8 {
449    #[inline(always)]
450    fn from(variant: IOPDACS_A) -> Self {
451        variant as _
452    }
453}
454impl crate::FieldSpec for IOPDACS_A {
455    type Ux = u8;
456}
457impl IOPDACS_R {
458    #[doc = "Get enumerated values variant"]
459    #[inline(always)]
460    pub const fn variant(&self) -> IOPDACS_A {
461        match self.bits {
462            0 => IOPDACS_A::C6U,
463            1 => IOPDACS_A::C7U,
464            2 => IOPDACS_A::C8U,
465            3 => IOPDACS_A::C9U,
466            _ => unreachable!(),
467        }
468    }
469    #[doc = "`0`"]
470    #[inline(always)]
471    pub fn is_c6u(&self) -> bool {
472        *self == IOPDACS_A::C6U
473    }
474    #[doc = "`1`"]
475    #[inline(always)]
476    pub fn is_c7u(&self) -> bool {
477        *self == IOPDACS_A::C7U
478    }
479    #[doc = "`10`"]
480    #[inline(always)]
481    pub fn is_c8u(&self) -> bool {
482        *self == IOPDACS_A::C8U
483    }
484    #[doc = "`11`"]
485    #[inline(always)]
486    pub fn is_c9u(&self) -> bool {
487        *self == IOPDACS_A::C9U
488    }
489}
490#[doc = "Field `iopdacs` writer - OPDAC L/R Bias Current Select"]
491pub type IOPDACS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IOPDACS_A>;
492impl<'a, REG> IOPDACS_W<'a, REG>
493where
494    REG: crate::Writable + crate::RegisterSpec,
495    REG::Ux: From<u8>,
496{
497    #[doc = "`0`"]
498    #[inline(always)]
499    pub fn c6u(self) -> &'a mut crate::W<REG> {
500        self.variant(IOPDACS_A::C6U)
501    }
502    #[doc = "`1`"]
503    #[inline(always)]
504    pub fn c7u(self) -> &'a mut crate::W<REG> {
505        self.variant(IOPDACS_A::C7U)
506    }
507    #[doc = "`10`"]
508    #[inline(always)]
509    pub fn c8u(self) -> &'a mut crate::W<REG> {
510        self.variant(IOPDACS_A::C8U)
511    }
512    #[doc = "`11`"]
513    #[inline(always)]
514    pub fn c9u(self) -> &'a mut crate::W<REG> {
515        self.variant(IOPDACS_A::C9U)
516    }
517}
518#[doc = "Field `ilineoutamps` reader - LINEOUT L/R AMP Bias Current Select"]
519pub type ILINEOUTAMPS_R = crate::FieldReader<ILINEOUTAMPS_A>;
520#[doc = "LINEOUT L/R AMP Bias Current Select\n\nValue on reset: 0"]
521#[derive(Clone, Copy, Debug, PartialEq, Eq)]
522#[repr(u8)]
523pub enum ILINEOUTAMPS_A {
524    #[doc = "0: `0`"]
525    C6U = 0,
526    #[doc = "1: `1`"]
527    C7U = 1,
528    #[doc = "2: `10`"]
529    C8U = 2,
530    #[doc = "3: `11`"]
531    C9U = 3,
532}
533impl From<ILINEOUTAMPS_A> for u8 {
534    #[inline(always)]
535    fn from(variant: ILINEOUTAMPS_A) -> Self {
536        variant as _
537    }
538}
539impl crate::FieldSpec for ILINEOUTAMPS_A {
540    type Ux = u8;
541}
542impl ILINEOUTAMPS_R {
543    #[doc = "Get enumerated values variant"]
544    #[inline(always)]
545    pub const fn variant(&self) -> ILINEOUTAMPS_A {
546        match self.bits {
547            0 => ILINEOUTAMPS_A::C6U,
548            1 => ILINEOUTAMPS_A::C7U,
549            2 => ILINEOUTAMPS_A::C8U,
550            3 => ILINEOUTAMPS_A::C9U,
551            _ => unreachable!(),
552        }
553    }
554    #[doc = "`0`"]
555    #[inline(always)]
556    pub fn is_c6u(&self) -> bool {
557        *self == ILINEOUTAMPS_A::C6U
558    }
559    #[doc = "`1`"]
560    #[inline(always)]
561    pub fn is_c7u(&self) -> bool {
562        *self == ILINEOUTAMPS_A::C7U
563    }
564    #[doc = "`10`"]
565    #[inline(always)]
566    pub fn is_c8u(&self) -> bool {
567        *self == ILINEOUTAMPS_A::C8U
568    }
569    #[doc = "`11`"]
570    #[inline(always)]
571    pub fn is_c9u(&self) -> bool {
572        *self == ILINEOUTAMPS_A::C9U
573    }
574}
575#[doc = "Field `ilineoutamps` writer - LINEOUT L/R AMP Bias Current Select"]
576pub type ILINEOUTAMPS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ILINEOUTAMPS_A>;
577impl<'a, REG> ILINEOUTAMPS_W<'a, REG>
578where
579    REG: crate::Writable + crate::RegisterSpec,
580    REG::Ux: From<u8>,
581{
582    #[doc = "`0`"]
583    #[inline(always)]
584    pub fn c6u(self) -> &'a mut crate::W<REG> {
585        self.variant(ILINEOUTAMPS_A::C6U)
586    }
587    #[doc = "`1`"]
588    #[inline(always)]
589    pub fn c7u(self) -> &'a mut crate::W<REG> {
590        self.variant(ILINEOUTAMPS_A::C7U)
591    }
592    #[doc = "`10`"]
593    #[inline(always)]
594    pub fn c8u(self) -> &'a mut crate::W<REG> {
595        self.variant(ILINEOUTAMPS_A::C8U)
596    }
597    #[doc = "`11`"]
598    #[inline(always)]
599    pub fn c9u(self) -> &'a mut crate::W<REG> {
600        self.variant(ILINEOUTAMPS_A::C9U)
601    }
602}
603#[doc = "Field `iopvrs` reader - VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current Select"]
604pub type IOPVRS_R = crate::FieldReader<IOPVRS_A>;
605#[doc = "VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current Select\n\nValue on reset: 0"]
606#[derive(Clone, Copy, Debug, PartialEq, Eq)]
607#[repr(u8)]
608pub enum IOPVRS_A {
609    #[doc = "0: `0`"]
610    C6U = 0,
611    #[doc = "1: `1`"]
612    C7U = 1,
613    #[doc = "2: `10`"]
614    C8U = 2,
615    #[doc = "3: `11`"]
616    C9U = 3,
617}
618impl From<IOPVRS_A> for u8 {
619    #[inline(always)]
620    fn from(variant: IOPVRS_A) -> Self {
621        variant as _
622    }
623}
624impl crate::FieldSpec for IOPVRS_A {
625    type Ux = u8;
626}
627impl IOPVRS_R {
628    #[doc = "Get enumerated values variant"]
629    #[inline(always)]
630    pub const fn variant(&self) -> IOPVRS_A {
631        match self.bits {
632            0 => IOPVRS_A::C6U,
633            1 => IOPVRS_A::C7U,
634            2 => IOPVRS_A::C8U,
635            3 => IOPVRS_A::C9U,
636            _ => unreachable!(),
637        }
638    }
639    #[doc = "`0`"]
640    #[inline(always)]
641    pub fn is_c6u(&self) -> bool {
642        *self == IOPVRS_A::C6U
643    }
644    #[doc = "`1`"]
645    #[inline(always)]
646    pub fn is_c7u(&self) -> bool {
647        *self == IOPVRS_A::C7U
648    }
649    #[doc = "`10`"]
650    #[inline(always)]
651    pub fn is_c8u(&self) -> bool {
652        *self == IOPVRS_A::C8U
653    }
654    #[doc = "`11`"]
655    #[inline(always)]
656    pub fn is_c9u(&self) -> bool {
657        *self == IOPVRS_A::C9U
658    }
659}
660#[doc = "Field `iopvrs` writer - VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current Select"]
661pub type IOPVRS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IOPVRS_A>;
662impl<'a, REG> IOPVRS_W<'a, REG>
663where
664    REG: crate::Writable + crate::RegisterSpec,
665    REG::Ux: From<u8>,
666{
667    #[doc = "`0`"]
668    #[inline(always)]
669    pub fn c6u(self) -> &'a mut crate::W<REG> {
670        self.variant(IOPVRS_A::C6U)
671    }
672    #[doc = "`1`"]
673    #[inline(always)]
674    pub fn c7u(self) -> &'a mut crate::W<REG> {
675        self.variant(IOPVRS_A::C7U)
676    }
677    #[doc = "`10`"]
678    #[inline(always)]
679    pub fn c8u(self) -> &'a mut crate::W<REG> {
680        self.variant(IOPVRS_A::C8U)
681    }
682    #[doc = "`11`"]
683    #[inline(always)]
684    pub fn c9u(self) -> &'a mut crate::W<REG> {
685        self.variant(IOPVRS_A::C9U)
686    }
687}
688#[doc = "Field `current_test_select` reader - Internal Current Sink Test Enable (from MICIN3P pin)"]
689pub type CURRENT_TEST_SELECT_R = crate::BitReader<CURRENT_TEST_SELECT_A>;
690#[doc = "Internal Current Sink Test Enable (from MICIN3P pin)\n\nValue on reset: 0"]
691#[derive(Clone, Copy, Debug, PartialEq, Eq)]
692pub enum CURRENT_TEST_SELECT_A {
693    #[doc = "0: `0`"]
694    NORMAL = 0,
695    #[doc = "1: `1`"]
696    DEBUG = 1,
697}
698impl From<CURRENT_TEST_SELECT_A> for bool {
699    #[inline(always)]
700    fn from(variant: CURRENT_TEST_SELECT_A) -> Self {
701        variant as u8 != 0
702    }
703}
704impl CURRENT_TEST_SELECT_R {
705    #[doc = "Get enumerated values variant"]
706    #[inline(always)]
707    pub const fn variant(&self) -> CURRENT_TEST_SELECT_A {
708        match self.bits {
709            false => CURRENT_TEST_SELECT_A::NORMAL,
710            true => CURRENT_TEST_SELECT_A::DEBUG,
711        }
712    }
713    #[doc = "`0`"]
714    #[inline(always)]
715    pub fn is_normal(&self) -> bool {
716        *self == CURRENT_TEST_SELECT_A::NORMAL
717    }
718    #[doc = "`1`"]
719    #[inline(always)]
720    pub fn is_debug(&self) -> bool {
721        *self == CURRENT_TEST_SELECT_A::DEBUG
722    }
723}
724#[doc = "Field `current_test_select` writer - Internal Current Sink Test Enable (from MICIN3P pin)"]
725pub type CURRENT_TEST_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, CURRENT_TEST_SELECT_A>;
726impl<'a, REG> CURRENT_TEST_SELECT_W<'a, REG>
727where
728    REG: crate::Writable + crate::RegisterSpec,
729{
730    #[doc = "`0`"]
731    #[inline(always)]
732    pub fn normal(self) -> &'a mut crate::W<REG> {
733        self.variant(CURRENT_TEST_SELECT_A::NORMAL)
734    }
735    #[doc = "`1`"]
736    #[inline(always)]
737    pub fn debug(self) -> &'a mut crate::W<REG> {
738        self.variant(CURRENT_TEST_SELECT_A::DEBUG)
739    }
740}
741impl R {
742    #[doc = "Bits 0:4 - LINEOUT Volume Control.\n\nTotal 30 level from 0x1F to 0x02 with the volume 0 dB to -43.5 dB, -1.5 dB/step, mute when 00000 or 00001"]
743    #[inline(always)]
744    pub fn lineout_vol_ctrl(&self) -> LINEOUT_VOL_CTRL_R {
745        LINEOUT_VOL_CTRL_R::new((self.bits & 0x1f) as u8)
746    }
747    #[doc = "Bit 5 - Right Channel LINEOUT Output Control"]
748    #[inline(always)]
749    pub fn lineoutr_diffen(&self) -> LINEOUTR_DIFFEN_R {
750        LINEOUTR_DIFFEN_R::new(((self.bits >> 5) & 1) != 0)
751    }
752    #[doc = "Bit 6 - Left Channel LINEOUT Output Control"]
753    #[inline(always)]
754    pub fn lineoutl_diffen(&self) -> LINEOUTL_DIFFEN_R {
755        LINEOUTL_DIFFEN_R::new(((self.bits >> 6) & 1) != 0)
756    }
757    #[doc = "Bit 10 - DACR to Right Channel LINEOUT Mute Control"]
758    #[inline(always)]
759    pub fn rmute(&self) -> RMUTE_R {
760        RMUTE_R::new(((self.bits >> 10) & 1) != 0)
761    }
762    #[doc = "Bit 11 - Right Channel LINEOUT Enable"]
763    #[inline(always)]
764    pub fn lineoutren(&self) -> LINEOUTREN_R {
765        LINEOUTREN_R::new(((self.bits >> 11) & 1) != 0)
766    }
767    #[doc = "Bit 12 - DACL to Left Channel LINEOUT Mute Control"]
768    #[inline(always)]
769    pub fn lmute(&self) -> LMUTE_R {
770        LMUTE_R::new(((self.bits >> 12) & 1) != 0)
771    }
772    #[doc = "Bit 13 - Left Channel LINEOUT Enable"]
773    #[inline(always)]
774    pub fn lineoutlen(&self) -> LINEOUTLEN_R {
775        LINEOUTLEN_R::new(((self.bits >> 13) & 1) != 0)
776    }
777    #[doc = "Bit 14 - DACR Enable"]
778    #[inline(always)]
779    pub fn dacr_en(&self) -> DACR_EN_R {
780        DACR_EN_R::new(((self.bits >> 14) & 1) != 0)
781    }
782    #[doc = "Bit 15 - DACL Enable"]
783    #[inline(always)]
784    pub fn dacl_en(&self) -> DACL_EN_R {
785        DACL_EN_R::new(((self.bits >> 15) & 1) != 0)
786    }
787    #[doc = "Bits 16:17 - OPDAC L/R Bias Current Select"]
788    #[inline(always)]
789    pub fn iopdacs(&self) -> IOPDACS_R {
790        IOPDACS_R::new(((self.bits >> 16) & 3) as u8)
791    }
792    #[doc = "Bits 18:19 - LINEOUT L/R AMP Bias Current Select"]
793    #[inline(always)]
794    pub fn ilineoutamps(&self) -> ILINEOUTAMPS_R {
795        ILINEOUTAMPS_R::new(((self.bits >> 18) & 3) as u8)
796    }
797    #[doc = "Bits 20:21 - VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current Select"]
798    #[inline(always)]
799    pub fn iopvrs(&self) -> IOPVRS_R {
800        IOPVRS_R::new(((self.bits >> 20) & 3) as u8)
801    }
802    #[doc = "Bit 23 - Internal Current Sink Test Enable (from MICIN3P pin)"]
803    #[inline(always)]
804    pub fn current_test_select(&self) -> CURRENT_TEST_SELECT_R {
805        CURRENT_TEST_SELECT_R::new(((self.bits >> 23) & 1) != 0)
806    }
807}
808impl W {
809    #[doc = "Bits 0:4 - LINEOUT Volume Control.\n\nTotal 30 level from 0x1F to 0x02 with the volume 0 dB to -43.5 dB, -1.5 dB/step, mute when 00000 or 00001"]
810    #[inline(always)]
811    #[must_use]
812    pub fn lineout_vol_ctrl(&mut self) -> LINEOUT_VOL_CTRL_W<DAC_SPEC> {
813        LINEOUT_VOL_CTRL_W::new(self, 0)
814    }
815    #[doc = "Bit 5 - Right Channel LINEOUT Output Control"]
816    #[inline(always)]
817    #[must_use]
818    pub fn lineoutr_diffen(&mut self) -> LINEOUTR_DIFFEN_W<DAC_SPEC> {
819        LINEOUTR_DIFFEN_W::new(self, 5)
820    }
821    #[doc = "Bit 6 - Left Channel LINEOUT Output Control"]
822    #[inline(always)]
823    #[must_use]
824    pub fn lineoutl_diffen(&mut self) -> LINEOUTL_DIFFEN_W<DAC_SPEC> {
825        LINEOUTL_DIFFEN_W::new(self, 6)
826    }
827    #[doc = "Bit 10 - DACR to Right Channel LINEOUT Mute Control"]
828    #[inline(always)]
829    #[must_use]
830    pub fn rmute(&mut self) -> RMUTE_W<DAC_SPEC> {
831        RMUTE_W::new(self, 10)
832    }
833    #[doc = "Bit 11 - Right Channel LINEOUT Enable"]
834    #[inline(always)]
835    #[must_use]
836    pub fn lineoutren(&mut self) -> LINEOUTREN_W<DAC_SPEC> {
837        LINEOUTREN_W::new(self, 11)
838    }
839    #[doc = "Bit 12 - DACL to Left Channel LINEOUT Mute Control"]
840    #[inline(always)]
841    #[must_use]
842    pub fn lmute(&mut self) -> LMUTE_W<DAC_SPEC> {
843        LMUTE_W::new(self, 12)
844    }
845    #[doc = "Bit 13 - Left Channel LINEOUT Enable"]
846    #[inline(always)]
847    #[must_use]
848    pub fn lineoutlen(&mut self) -> LINEOUTLEN_W<DAC_SPEC> {
849        LINEOUTLEN_W::new(self, 13)
850    }
851    #[doc = "Bit 14 - DACR Enable"]
852    #[inline(always)]
853    #[must_use]
854    pub fn dacr_en(&mut self) -> DACR_EN_W<DAC_SPEC> {
855        DACR_EN_W::new(self, 14)
856    }
857    #[doc = "Bit 15 - DACL Enable"]
858    #[inline(always)]
859    #[must_use]
860    pub fn dacl_en(&mut self) -> DACL_EN_W<DAC_SPEC> {
861        DACL_EN_W::new(self, 15)
862    }
863    #[doc = "Bits 16:17 - OPDAC L/R Bias Current Select"]
864    #[inline(always)]
865    #[must_use]
866    pub fn iopdacs(&mut self) -> IOPDACS_W<DAC_SPEC> {
867        IOPDACS_W::new(self, 16)
868    }
869    #[doc = "Bits 18:19 - LINEOUT L/R AMP Bias Current Select"]
870    #[inline(always)]
871    #[must_use]
872    pub fn ilineoutamps(&mut self) -> ILINEOUTAMPS_W<DAC_SPEC> {
873        ILINEOUTAMPS_W::new(self, 18)
874    }
875    #[doc = "Bits 20:21 - VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current Select"]
876    #[inline(always)]
877    #[must_use]
878    pub fn iopvrs(&mut self) -> IOPVRS_W<DAC_SPEC> {
879        IOPVRS_W::new(self, 20)
880    }
881    #[doc = "Bit 23 - Internal Current Sink Test Enable (from MICIN3P pin)"]
882    #[inline(always)]
883    #[must_use]
884    pub fn current_test_select(&mut self) -> CURRENT_TEST_SELECT_W<DAC_SPEC> {
885        CURRENT_TEST_SELECT_W::new(self, 23)
886    }
887    #[doc = r" Writes raw bits to the register."]
888    #[doc = r""]
889    #[doc = r" # Safety"]
890    #[doc = r""]
891    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
892    #[inline(always)]
893    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
894        self.bits = bits;
895        self
896    }
897}
898#[doc = "DAC Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
899pub struct DAC_SPEC;
900impl crate::RegisterSpec for DAC_SPEC {
901    type Ux = u32;
902}
903#[doc = "`read()` method returns [`dac::R`](R) reader structure"]
904impl crate::Readable for DAC_SPEC {}
905#[doc = "`write(|w| ..)` method takes [`dac::W`](W) writer structure"]
906impl crate::Writable for DAC_SPEC {
907    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
908    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
909}
910#[doc = "`reset()` method sets dac to value 0"]
911impl crate::Resettable for DAC_SPEC {
912    const RESET_VALUE: Self::Ux = 0;
913}
d1_pac/audio_codec/dac.rs

d1_pac/audio_codec/
dac.rs
