d1_pac/audio_codec/
adc.rs

1#[doc = "Register `adc%s` reader"]
2pub type R = crate::R<ADC_SPEC>;
3#[doc = "Register `adc%s` writer"]
4pub type W = crate::W<ADC_SPEC>;
5#[doc = "Field `adc_iopmic` reader - ADC OP MIC Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
6pub type ADC_IOPMIC_R = crate::FieldReader<ADC_IOPMIC_A>;
7#[doc = "ADC OP MIC Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum ADC_IOPMIC_A {
11    #[doc = "0: 1.50*IOPADC"]
12    _1_50 = 0,
13    #[doc = "1: 1.75*IOPADC"]
14    _1_75 = 1,
15    #[doc = "2: 2.00*IOPADC"]
16    _2_00 = 2,
17    #[doc = "3: 2.25*IOPADC"]
18    _2_25 = 3,
19}
20impl From<ADC_IOPMIC_A> for u8 {
21    #[inline(always)]
22    fn from(variant: ADC_IOPMIC_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for ADC_IOPMIC_A {
27    type Ux = u8;
28}
29impl ADC_IOPMIC_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> ADC_IOPMIC_A {
33        match self.bits {
34            0 => ADC_IOPMIC_A::_1_50,
35            1 => ADC_IOPMIC_A::_1_75,
36            2 => ADC_IOPMIC_A::_2_00,
37            3 => ADC_IOPMIC_A::_2_25,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "1.50*IOPADC"]
42    #[inline(always)]
43    pub fn is_1_50(&self) -> bool {
44        *self == ADC_IOPMIC_A::_1_50
45    }
46    #[doc = "1.75*IOPADC"]
47    #[inline(always)]
48    pub fn is_1_75(&self) -> bool {
49        *self == ADC_IOPMIC_A::_1_75
50    }
51    #[doc = "2.00*IOPADC"]
52    #[inline(always)]
53    pub fn is_2_00(&self) -> bool {
54        *self == ADC_IOPMIC_A::_2_00
55    }
56    #[doc = "2.25*IOPADC"]
57    #[inline(always)]
58    pub fn is_2_25(&self) -> bool {
59        *self == ADC_IOPMIC_A::_2_25
60    }
61}
62#[doc = "Field `adc_iopmic` writer - ADC OP MIC Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
63pub type ADC_IOPMIC_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_IOPMIC_A>;
64impl<'a, REG> ADC_IOPMIC_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "1.50*IOPADC"]
70    #[inline(always)]
71    pub fn _1_50(self) -> &'a mut crate::W<REG> {
72        self.variant(ADC_IOPMIC_A::_1_50)
73    }
74    #[doc = "1.75*IOPADC"]
75    #[inline(always)]
76    pub fn _1_75(self) -> &'a mut crate::W<REG> {
77        self.variant(ADC_IOPMIC_A::_1_75)
78    }
79    #[doc = "2.00*IOPADC"]
80    #[inline(always)]
81    pub fn _2_00(self) -> &'a mut crate::W<REG> {
82        self.variant(ADC_IOPMIC_A::_2_00)
83    }
84    #[doc = "2.25*IOPADC"]
85    #[inline(always)]
86    pub fn _2_25(self) -> &'a mut crate::W<REG> {
87        self.variant(ADC_IOPMIC_A::_2_25)
88    }
89}
90#[doc = "Field `adc_iopsdm[2,1]` reader - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
91pub type ADC_IOPSDM_R = crate::FieldReader<ADC_IOPSDM_A>;
92#[doc = "ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nValue on reset: 1"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94#[repr(u8)]
95pub enum ADC_IOPSDM_A {
96    #[doc = "0: 1.50*IOPADC"]
97    _1_50 = 0,
98    #[doc = "1: 1.75*IOPADC"]
99    _1_75 = 1,
100    #[doc = "2: 2.00*IOPADC"]
101    _2_00 = 2,
102    #[doc = "3: 2.25*IOPADC"]
103    _2_25 = 3,
104}
105impl From<ADC_IOPSDM_A> for u8 {
106    #[inline(always)]
107    fn from(variant: ADC_IOPSDM_A) -> Self {
108        variant as _
109    }
110}
111impl crate::FieldSpec for ADC_IOPSDM_A {
112    type Ux = u8;
113}
114impl ADC_IOPSDM_R {
115    #[doc = "Get enumerated values variant"]
116    #[inline(always)]
117    pub const fn variant(&self) -> ADC_IOPSDM_A {
118        match self.bits {
119            0 => ADC_IOPSDM_A::_1_50,
120            1 => ADC_IOPSDM_A::_1_75,
121            2 => ADC_IOPSDM_A::_2_00,
122            3 => ADC_IOPSDM_A::_2_25,
123            _ => unreachable!(),
124        }
125    }
126    #[doc = "1.50*IOPADC"]
127    #[inline(always)]
128    pub fn is_1_50(&self) -> bool {
129        *self == ADC_IOPSDM_A::_1_50
130    }
131    #[doc = "1.75*IOPADC"]
132    #[inline(always)]
133    pub fn is_1_75(&self) -> bool {
134        *self == ADC_IOPSDM_A::_1_75
135    }
136    #[doc = "2.00*IOPADC"]
137    #[inline(always)]
138    pub fn is_2_00(&self) -> bool {
139        *self == ADC_IOPSDM_A::_2_00
140    }
141    #[doc = "2.25*IOPADC"]
142    #[inline(always)]
143    pub fn is_2_25(&self) -> bool {
144        *self == ADC_IOPSDM_A::_2_25
145    }
146}
147#[doc = "Field `adc_iopsdm[2,1]` writer - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
148pub type ADC_IOPSDM_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_IOPSDM_A>;
149impl<'a, REG> ADC_IOPSDM_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152    REG::Ux: From<u8>,
153{
154    #[doc = "1.50*IOPADC"]
155    #[inline(always)]
156    pub fn _1_50(self) -> &'a mut crate::W<REG> {
157        self.variant(ADC_IOPSDM_A::_1_50)
158    }
159    #[doc = "1.75*IOPADC"]
160    #[inline(always)]
161    pub fn _1_75(self) -> &'a mut crate::W<REG> {
162        self.variant(ADC_IOPSDM_A::_1_75)
163    }
164    #[doc = "2.00*IOPADC"]
165    #[inline(always)]
166    pub fn _2_00(self) -> &'a mut crate::W<REG> {
167        self.variant(ADC_IOPSDM_A::_2_00)
168    }
169    #[doc = "2.25*IOPADC"]
170    #[inline(always)]
171    pub fn _2_25(self) -> &'a mut crate::W<REG> {
172        self.variant(ADC_IOPSDM_A::_2_25)
173    }
174}
175#[doc = "Field `adc_iopaaf` reader - ADC OP AAF Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nFor example: ADC_REG&lt;15:14> = 11, IOPADC = 4 uA \n\n00: 1.50*4 uA = 6 uA \n\n01: 1.75*4 uA = 7 uA \n\n10: 2.00*4 uA = 8 uA \n\n11: 2.25*4 uA = 9 uA"]
176pub type ADC_IOPAAF_R = crate::FieldReader<ADC_IOPAAF_A>;
177#[doc = "ADC OP AAF Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nFor example: ADC_REG&lt;15:14> = 11, IOPADC = 4 uA \n\n00: 1.50*4 uA = 6 uA \n\n01: 1.75*4 uA = 7 uA \n\n10: 2.00*4 uA = 8 uA \n\n11: 2.25*4 uA = 9 uA\n\nValue on reset: 1"]
178#[derive(Clone, Copy, Debug, PartialEq, Eq)]
179#[repr(u8)]
180pub enum ADC_IOPAAF_A {
181    #[doc = "0: 1.50*IOPADC"]
182    _1_50 = 0,
183    #[doc = "1: 1.75*IOPADC"]
184    _1_75 = 1,
185    #[doc = "2: 2.00*IOPADC"]
186    _2_00 = 2,
187    #[doc = "3: 2.25*IOPADC"]
188    _2_25 = 3,
189}
190impl From<ADC_IOPAAF_A> for u8 {
191    #[inline(always)]
192    fn from(variant: ADC_IOPAAF_A) -> Self {
193        variant as _
194    }
195}
196impl crate::FieldSpec for ADC_IOPAAF_A {
197    type Ux = u8;
198}
199impl ADC_IOPAAF_R {
200    #[doc = "Get enumerated values variant"]
201    #[inline(always)]
202    pub const fn variant(&self) -> ADC_IOPAAF_A {
203        match self.bits {
204            0 => ADC_IOPAAF_A::_1_50,
205            1 => ADC_IOPAAF_A::_1_75,
206            2 => ADC_IOPAAF_A::_2_00,
207            3 => ADC_IOPAAF_A::_2_25,
208            _ => unreachable!(),
209        }
210    }
211    #[doc = "1.50*IOPADC"]
212    #[inline(always)]
213    pub fn is_1_50(&self) -> bool {
214        *self == ADC_IOPAAF_A::_1_50
215    }
216    #[doc = "1.75*IOPADC"]
217    #[inline(always)]
218    pub fn is_1_75(&self) -> bool {
219        *self == ADC_IOPAAF_A::_1_75
220    }
221    #[doc = "2.00*IOPADC"]
222    #[inline(always)]
223    pub fn is_2_00(&self) -> bool {
224        *self == ADC_IOPAAF_A::_2_00
225    }
226    #[doc = "2.25*IOPADC"]
227    #[inline(always)]
228    pub fn is_2_25(&self) -> bool {
229        *self == ADC_IOPAAF_A::_2_25
230    }
231}
232#[doc = "Field `adc_iopaaf` writer - ADC OP AAF Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nFor example: ADC_REG&lt;15:14> = 11, IOPADC = 4 uA \n\n00: 1.50*4 uA = 6 uA \n\n01: 1.75*4 uA = 7 uA \n\n10: 2.00*4 uA = 8 uA \n\n11: 2.25*4 uA = 9 uA"]
233pub type ADC_IOPAAF_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_IOPAAF_A>;
234impl<'a, REG> ADC_IOPAAF_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237    REG::Ux: From<u8>,
238{
239    #[doc = "1.50*IOPADC"]
240    #[inline(always)]
241    pub fn _1_50(self) -> &'a mut crate::W<REG> {
242        self.variant(ADC_IOPAAF_A::_1_50)
243    }
244    #[doc = "1.75*IOPADC"]
245    #[inline(always)]
246    pub fn _1_75(self) -> &'a mut crate::W<REG> {
247        self.variant(ADC_IOPAAF_A::_1_75)
248    }
249    #[doc = "2.00*IOPADC"]
250    #[inline(always)]
251    pub fn _2_00(self) -> &'a mut crate::W<REG> {
252        self.variant(ADC_IOPAAF_A::_2_00)
253    }
254    #[doc = "2.25*IOPADC"]
255    #[inline(always)]
256    pub fn _2_25(self) -> &'a mut crate::W<REG> {
257        self.variant(ADC_IOPAAF_A::_2_25)
258    }
259}
260#[doc = "Field `adc_pga_gain_ctrl` reader - ADC PGA gain settings:\n\n\n\n0x0: 0 dB \\t0x10: 21 dB \n\n0x1: 6 dB \\t0x11: 22 dB \n\n0x2: 6 dB \\t0x12: 23 dB \n\n0x3: 6 dB \\t0x13: 24 dB \n\n0x4: 9 dB \\t0x14: 25 dB \n\n0x5: 10 dB\\t0x15: 26 dB \n\n0x6: 11 dB\\t0x16: 27 dB \n\n0x7: 12 dB\\t0x17: 28 dB \n\n0x8: 13 dB\\t0x18: 29 dB \n\n0x9: 14 dB\\t0x19: 30 dB \n\n0xA: 15 dB\\t0x1A: 31 dB \n\n0xB: 16 dB\\t0x1B: 32 dB \n\n0xC: 17 dB\\t0x1C: 33 dB \n\n0xD: 18 dB\\t0x1D: 34 dB \n\n0xE: 19 dB\\t0x1E: 35 dB \n\n0xF: 20 dB\\t0x1F: 36 dB"]
261pub type ADC_PGA_GAIN_CTRL_R = crate::FieldReader;
262#[doc = "Field `adc_pga_gain_ctrl` writer - ADC PGA gain settings:\n\n\n\n0x0: 0 dB \\t0x10: 21 dB \n\n0x1: 6 dB \\t0x11: 22 dB \n\n0x2: 6 dB \\t0x12: 23 dB \n\n0x3: 6 dB \\t0x13: 24 dB \n\n0x4: 9 dB \\t0x14: 25 dB \n\n0x5: 10 dB\\t0x15: 26 dB \n\n0x6: 11 dB\\t0x16: 27 dB \n\n0x7: 12 dB\\t0x17: 28 dB \n\n0x8: 13 dB\\t0x18: 29 dB \n\n0x9: 14 dB\\t0x19: 30 dB \n\n0xA: 15 dB\\t0x1A: 31 dB \n\n0xB: 16 dB\\t0x1B: 32 dB \n\n0xC: 17 dB\\t0x1C: 33 dB \n\n0xD: 18 dB\\t0x1D: 34 dB \n\n0xE: 19 dB\\t0x1E: 35 dB \n\n0xF: 20 dB\\t0x1F: 36 dB"]
263pub type ADC_PGA_GAIN_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
264#[doc = "Field `iopadc` reader - ADC1-ADC3 Bias Current Select"]
265pub type IOPADC_R = crate::FieldReader<IOPADC_A>;
266#[doc = "ADC1-ADC3 Bias Current Select\n\nValue on reset: 3"]
267#[derive(Clone, Copy, Debug, PartialEq, Eq)]
268#[repr(u8)]
269pub enum IOPADC_A {
270    #[doc = "0: 1 uA"]
271    _1U = 0,
272    #[doc = "1: 2 uA"]
273    _2U = 1,
274    #[doc = "2: 3 uA"]
275    _3U = 2,
276    #[doc = "3: 4 uA"]
277    _4U = 3,
278}
279impl From<IOPADC_A> for u8 {
280    #[inline(always)]
281    fn from(variant: IOPADC_A) -> Self {
282        variant as _
283    }
284}
285impl crate::FieldSpec for IOPADC_A {
286    type Ux = u8;
287}
288impl IOPADC_R {
289    #[doc = "Get enumerated values variant"]
290    #[inline(always)]
291    pub const fn variant(&self) -> IOPADC_A {
292        match self.bits {
293            0 => IOPADC_A::_1U,
294            1 => IOPADC_A::_2U,
295            2 => IOPADC_A::_3U,
296            3 => IOPADC_A::_4U,
297            _ => unreachable!(),
298        }
299    }
300    #[doc = "1 uA"]
301    #[inline(always)]
302    pub fn is_1u(&self) -> bool {
303        *self == IOPADC_A::_1U
304    }
305    #[doc = "2 uA"]
306    #[inline(always)]
307    pub fn is_2u(&self) -> bool {
308        *self == IOPADC_A::_2U
309    }
310    #[doc = "3 uA"]
311    #[inline(always)]
312    pub fn is_3u(&self) -> bool {
313        *self == IOPADC_A::_3U
314    }
315    #[doc = "4 uA"]
316    #[inline(always)]
317    pub fn is_4u(&self) -> bool {
318        *self == IOPADC_A::_4U
319    }
320}
321#[doc = "Field `iopadc` writer - ADC1-ADC3 Bias Current Select"]
322pub type IOPADC_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IOPADC_A>;
323impl<'a, REG> IOPADC_W<'a, REG>
324where
325    REG: crate::Writable + crate::RegisterSpec,
326    REG::Ux: From<u8>,
327{
328    #[doc = "1 uA"]
329    #[inline(always)]
330    pub fn _1u(self) -> &'a mut crate::W<REG> {
331        self.variant(IOPADC_A::_1U)
332    }
333    #[doc = "2 uA"]
334    #[inline(always)]
335    pub fn _2u(self) -> &'a mut crate::W<REG> {
336        self.variant(IOPADC_A::_2U)
337    }
338    #[doc = "3 uA"]
339    #[inline(always)]
340    pub fn _3u(self) -> &'a mut crate::W<REG> {
341        self.variant(IOPADC_A::_3U)
342    }
343    #[doc = "4 uA"]
344    #[inline(always)]
345    pub fn _4u(self) -> &'a mut crate::W<REG> {
346        self.variant(IOPADC_A::_4U)
347    }
348}
349#[doc = "Field `adc_pga_in_vcm_ctrl` reader - ADC PGA Common-Mode Voltage Control"]
350pub type ADC_PGA_IN_VCM_CTRL_R = crate::FieldReader<ADC_PGA_IN_VCM_CTRL_A>;
351#[doc = "ADC PGA Common-Mode Voltage Control\n\nValue on reset: 0"]
352#[derive(Clone, Copy, Debug, PartialEq, Eq)]
353#[repr(u8)]
354pub enum ADC_PGA_IN_VCM_CTRL_A {
355    #[doc = "0: 900 mV"]
356    _900M = 0,
357    #[doc = "1: 800 mV"]
358    _800M = 1,
359    #[doc = "2: 750 mV"]
360    _750M = 2,
361    #[doc = "3: 700 mV"]
362    _700M = 3,
363}
364impl From<ADC_PGA_IN_VCM_CTRL_A> for u8 {
365    #[inline(always)]
366    fn from(variant: ADC_PGA_IN_VCM_CTRL_A) -> Self {
367        variant as _
368    }
369}
370impl crate::FieldSpec for ADC_PGA_IN_VCM_CTRL_A {
371    type Ux = u8;
372}
373impl ADC_PGA_IN_VCM_CTRL_R {
374    #[doc = "Get enumerated values variant"]
375    #[inline(always)]
376    pub const fn variant(&self) -> ADC_PGA_IN_VCM_CTRL_A {
377        match self.bits {
378            0 => ADC_PGA_IN_VCM_CTRL_A::_900M,
379            1 => ADC_PGA_IN_VCM_CTRL_A::_800M,
380            2 => ADC_PGA_IN_VCM_CTRL_A::_750M,
381            3 => ADC_PGA_IN_VCM_CTRL_A::_700M,
382            _ => unreachable!(),
383        }
384    }
385    #[doc = "900 mV"]
386    #[inline(always)]
387    pub fn is_900m(&self) -> bool {
388        *self == ADC_PGA_IN_VCM_CTRL_A::_900M
389    }
390    #[doc = "800 mV"]
391    #[inline(always)]
392    pub fn is_800m(&self) -> bool {
393        *self == ADC_PGA_IN_VCM_CTRL_A::_800M
394    }
395    #[doc = "750 mV"]
396    #[inline(always)]
397    pub fn is_750m(&self) -> bool {
398        *self == ADC_PGA_IN_VCM_CTRL_A::_750M
399    }
400    #[doc = "700 mV"]
401    #[inline(always)]
402    pub fn is_700m(&self) -> bool {
403        *self == ADC_PGA_IN_VCM_CTRL_A::_700M
404    }
405}
406#[doc = "Field `adc_pga_in_vcm_ctrl` writer - ADC PGA Common-Mode Voltage Control"]
407pub type ADC_PGA_IN_VCM_CTRL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_PGA_IN_VCM_CTRL_A>;
408impl<'a, REG> ADC_PGA_IN_VCM_CTRL_W<'a, REG>
409where
410    REG: crate::Writable + crate::RegisterSpec,
411    REG::Ux: From<u8>,
412{
413    #[doc = "900 mV"]
414    #[inline(always)]
415    pub fn _900m(self) -> &'a mut crate::W<REG> {
416        self.variant(ADC_PGA_IN_VCM_CTRL_A::_900M)
417    }
418    #[doc = "800 mV"]
419    #[inline(always)]
420    pub fn _800m(self) -> &'a mut crate::W<REG> {
421        self.variant(ADC_PGA_IN_VCM_CTRL_A::_800M)
422    }
423    #[doc = "750 mV"]
424    #[inline(always)]
425    pub fn _750m(self) -> &'a mut crate::W<REG> {
426        self.variant(ADC_PGA_IN_VCM_CTRL_A::_750M)
427    }
428    #[doc = "700 mV"]
429    #[inline(always)]
430    pub fn _700m(self) -> &'a mut crate::W<REG> {
431        self.variant(ADC_PGA_IN_VCM_CTRL_A::_700M)
432    }
433}
434#[doc = "Field `adc_pga_ctrl_rcm` reader - ADC PGA Common Mode Input Impedance Control for MICIN"]
435pub type ADC_PGA_CTRL_RCM_R = crate::FieldReader<ADC_PGA_CTRL_RCM_A>;
436#[doc = "ADC PGA Common Mode Input Impedance Control for MICIN\n\nValue on reset: 3"]
437#[derive(Clone, Copy, Debug, PartialEq, Eq)]
438#[repr(u8)]
439pub enum ADC_PGA_CTRL_RCM_A {
440    #[doc = "0: 100 kΩ"]
441    _100K = 0,
442    #[doc = "1: 75 kΩ"]
443    _75K = 1,
444    #[doc = "2: 50 kΩ"]
445    _50K = 2,
446    #[doc = "3: 25 kΩ"]
447    _25K = 3,
448}
449impl From<ADC_PGA_CTRL_RCM_A> for u8 {
450    #[inline(always)]
451    fn from(variant: ADC_PGA_CTRL_RCM_A) -> Self {
452        variant as _
453    }
454}
455impl crate::FieldSpec for ADC_PGA_CTRL_RCM_A {
456    type Ux = u8;
457}
458impl ADC_PGA_CTRL_RCM_R {
459    #[doc = "Get enumerated values variant"]
460    #[inline(always)]
461    pub const fn variant(&self) -> ADC_PGA_CTRL_RCM_A {
462        match self.bits {
463            0 => ADC_PGA_CTRL_RCM_A::_100K,
464            1 => ADC_PGA_CTRL_RCM_A::_75K,
465            2 => ADC_PGA_CTRL_RCM_A::_50K,
466            3 => ADC_PGA_CTRL_RCM_A::_25K,
467            _ => unreachable!(),
468        }
469    }
470    #[doc = "100 kΩ"]
471    #[inline(always)]
472    pub fn is_100k(&self) -> bool {
473        *self == ADC_PGA_CTRL_RCM_A::_100K
474    }
475    #[doc = "75 kΩ"]
476    #[inline(always)]
477    pub fn is_75k(&self) -> bool {
478        *self == ADC_PGA_CTRL_RCM_A::_75K
479    }
480    #[doc = "50 kΩ"]
481    #[inline(always)]
482    pub fn is_50k(&self) -> bool {
483        *self == ADC_PGA_CTRL_RCM_A::_50K
484    }
485    #[doc = "25 kΩ"]
486    #[inline(always)]
487    pub fn is_25k(&self) -> bool {
488        *self == ADC_PGA_CTRL_RCM_A::_25K
489    }
490}
491#[doc = "Field `adc_pga_ctrl_rcm` writer - ADC PGA Common Mode Input Impedance Control for MICIN"]
492pub type ADC_PGA_CTRL_RCM_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADC_PGA_CTRL_RCM_A>;
493impl<'a, REG> ADC_PGA_CTRL_RCM_W<'a, REG>
494where
495    REG: crate::Writable + crate::RegisterSpec,
496    REG::Ux: From<u8>,
497{
498    #[doc = "100 kΩ"]
499    #[inline(always)]
500    pub fn _100k(self) -> &'a mut crate::W<REG> {
501        self.variant(ADC_PGA_CTRL_RCM_A::_100K)
502    }
503    #[doc = "75 kΩ"]
504    #[inline(always)]
505    pub fn _75k(self) -> &'a mut crate::W<REG> {
506        self.variant(ADC_PGA_CTRL_RCM_A::_75K)
507    }
508    #[doc = "50 kΩ"]
509    #[inline(always)]
510    pub fn _50k(self) -> &'a mut crate::W<REG> {
511        self.variant(ADC_PGA_CTRL_RCM_A::_50K)
512    }
513    #[doc = "25 kΩ"]
514    #[inline(always)]
515    pub fn _25k(self) -> &'a mut crate::W<REG> {
516        self.variant(ADC_PGA_CTRL_RCM_A::_25K)
517    }
518}
519#[doc = "Field `iopbuffer` reader - PGA Vcm Buffer OP Bias Current Select"]
520pub type IOPBUFFER_R = crate::FieldReader<IOPBUFFER_A>;
521#[doc = "PGA Vcm Buffer OP Bias Current Select\n\nValue on reset: 1"]
522#[derive(Clone, Copy, Debug, PartialEq, Eq)]
523#[repr(u8)]
524pub enum IOPBUFFER_A {
525    #[doc = "0: 6 uA"]
526    _6UA = 0,
527    #[doc = "1: 7 uA"]
528    _7UA = 1,
529    #[doc = "2: 8 uA"]
530    _8UA = 2,
531    #[doc = "3: 9 uA"]
532    _9UA = 3,
533}
534impl From<IOPBUFFER_A> for u8 {
535    #[inline(always)]
536    fn from(variant: IOPBUFFER_A) -> Self {
537        variant as _
538    }
539}
540impl crate::FieldSpec for IOPBUFFER_A {
541    type Ux = u8;
542}
543impl IOPBUFFER_R {
544    #[doc = "Get enumerated values variant"]
545    #[inline(always)]
546    pub const fn variant(&self) -> IOPBUFFER_A {
547        match self.bits {
548            0 => IOPBUFFER_A::_6UA,
549            1 => IOPBUFFER_A::_7UA,
550            2 => IOPBUFFER_A::_8UA,
551            3 => IOPBUFFER_A::_9UA,
552            _ => unreachable!(),
553        }
554    }
555    #[doc = "6 uA"]
556    #[inline(always)]
557    pub fn is_6ua(&self) -> bool {
558        *self == IOPBUFFER_A::_6UA
559    }
560    #[doc = "7 uA"]
561    #[inline(always)]
562    pub fn is_7ua(&self) -> bool {
563        *self == IOPBUFFER_A::_7UA
564    }
565    #[doc = "8 uA"]
566    #[inline(always)]
567    pub fn is_8ua(&self) -> bool {
568        *self == IOPBUFFER_A::_8UA
569    }
570    #[doc = "9 uA"]
571    #[inline(always)]
572    pub fn is_9ua(&self) -> bool {
573        *self == IOPBUFFER_A::_9UA
574    }
575}
576#[doc = "Field `iopbuffer` writer - PGA Vcm Buffer OP Bias Current Select"]
577pub type IOPBUFFER_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, IOPBUFFER_A>;
578impl<'a, REG> IOPBUFFER_W<'a, REG>
579where
580    REG: crate::Writable + crate::RegisterSpec,
581    REG::Ux: From<u8>,
582{
583    #[doc = "6 uA"]
584    #[inline(always)]
585    pub fn _6ua(self) -> &'a mut crate::W<REG> {
586        self.variant(IOPBUFFER_A::_6UA)
587    }
588    #[doc = "7 uA"]
589    #[inline(always)]
590    pub fn _7ua(self) -> &'a mut crate::W<REG> {
591        self.variant(IOPBUFFER_A::_7UA)
592    }
593    #[doc = "8 uA"]
594    #[inline(always)]
595    pub fn _8ua(self) -> &'a mut crate::W<REG> {
596        self.variant(IOPBUFFER_A::_8UA)
597    }
598    #[doc = "9 uA"]
599    #[inline(always)]
600    pub fn _9ua(self) -> &'a mut crate::W<REG> {
601        self.variant(IOPBUFFER_A::_9UA)
602    }
603}
604#[doc = "Field `lineinlg` reader - LINEINL Gain Control"]
605pub type LINEINLG_R = crate::BitReader<LINEINLG_A>;
606#[doc = "LINEINL Gain Control\n\nValue on reset: 0"]
607#[derive(Clone, Copy, Debug, PartialEq, Eq)]
608pub enum LINEINLG_A {
609    #[doc = "0: 0 dB"]
610    _0DB = 0,
611    #[doc = "1: 6 dB"]
612    _6DB = 1,
613}
614impl From<LINEINLG_A> for bool {
615    #[inline(always)]
616    fn from(variant: LINEINLG_A) -> Self {
617        variant as u8 != 0
618    }
619}
620impl LINEINLG_R {
621    #[doc = "Get enumerated values variant"]
622    #[inline(always)]
623    pub const fn variant(&self) -> LINEINLG_A {
624        match self.bits {
625            false => LINEINLG_A::_0DB,
626            true => LINEINLG_A::_6DB,
627        }
628    }
629    #[doc = "0 dB"]
630    #[inline(always)]
631    pub fn is_0db(&self) -> bool {
632        *self == LINEINLG_A::_0DB
633    }
634    #[doc = "6 dB"]
635    #[inline(always)]
636    pub fn is_6db(&self) -> bool {
637        *self == LINEINLG_A::_6DB
638    }
639}
640#[doc = "Field `lineinlg` writer - LINEINL Gain Control"]
641pub type LINEINLG_W<'a, REG> = crate::BitWriter<'a, REG, LINEINLG_A>;
642impl<'a, REG> LINEINLG_W<'a, REG>
643where
644    REG: crate::Writable + crate::RegisterSpec,
645{
646    #[doc = "0 dB"]
647    #[inline(always)]
648    pub fn _0db(self) -> &'a mut crate::W<REG> {
649        self.variant(LINEINLG_A::_0DB)
650    }
651    #[doc = "6 dB"]
652    #[inline(always)]
653    pub fn _6db(self) -> &'a mut crate::W<REG> {
654        self.variant(LINEINLG_A::_6DB)
655    }
656}
657#[doc = "Field `lineinlen` reader - LINEINL Enable"]
658pub type LINEINLEN_R = crate::BitReader<LINEINLEN_A>;
659#[doc = "LINEINL Enable\n\nValue on reset: 0"]
660#[derive(Clone, Copy, Debug, PartialEq, Eq)]
661pub enum LINEINLEN_A {
662    #[doc = "0: Disable"]
663    DISABLE = 0,
664    #[doc = "1: Enable"]
665    ENABLE = 1,
666}
667impl From<LINEINLEN_A> for bool {
668    #[inline(always)]
669    fn from(variant: LINEINLEN_A) -> Self {
670        variant as u8 != 0
671    }
672}
673impl LINEINLEN_R {
674    #[doc = "Get enumerated values variant"]
675    #[inline(always)]
676    pub const fn variant(&self) -> LINEINLEN_A {
677        match self.bits {
678            false => LINEINLEN_A::DISABLE,
679            true => LINEINLEN_A::ENABLE,
680        }
681    }
682    #[doc = "Disable"]
683    #[inline(always)]
684    pub fn is_disable(&self) -> bool {
685        *self == LINEINLEN_A::DISABLE
686    }
687    #[doc = "Enable"]
688    #[inline(always)]
689    pub fn is_enable(&self) -> bool {
690        *self == LINEINLEN_A::ENABLE
691    }
692}
693#[doc = "Field `lineinlen` writer - LINEINL Enable"]
694pub type LINEINLEN_W<'a, REG> = crate::BitWriter<'a, REG, LINEINLEN_A>;
695impl<'a, REG> LINEINLEN_W<'a, REG>
696where
697    REG: crate::Writable + crate::RegisterSpec,
698{
699    #[doc = "Disable"]
700    #[inline(always)]
701    pub fn disable(self) -> &'a mut crate::W<REG> {
702        self.variant(LINEINLEN_A::DISABLE)
703    }
704    #[doc = "Enable"]
705    #[inline(always)]
706    pub fn enable(self) -> &'a mut crate::W<REG> {
707        self.variant(LINEINLEN_A::ENABLE)
708    }
709}
710#[doc = "Field `dsm_dither_lvl` reader - Dither Level Control (Dither level is positive ralated to the ctrl bits)"]
711pub type DSM_DITHER_LVL_R = crate::FieldReader<DSM_DITHER_LVL_A>;
712#[doc = "Dither Level Control (Dither level is positive ralated to the ctrl bits)\n\nValue on reset: 0"]
713#[derive(Clone, Copy, Debug, PartialEq, Eq)]
714#[repr(u8)]
715pub enum DSM_DITHER_LVL_A {
716    #[doc = "0: No Level"]
717    N_O = 0,
718    #[doc = "1: Min Level"]
719    M_IN = 1,
720    #[doc = "2: Middle Level"]
721    M_IDDLE = 2,
722    #[doc = "3: Max Level"]
723    M_AX = 3,
724}
725impl From<DSM_DITHER_LVL_A> for u8 {
726    #[inline(always)]
727    fn from(variant: DSM_DITHER_LVL_A) -> Self {
728        variant as _
729    }
730}
731impl crate::FieldSpec for DSM_DITHER_LVL_A {
732    type Ux = u8;
733}
734impl DSM_DITHER_LVL_R {
735    #[doc = "Get enumerated values variant"]
736    #[inline(always)]
737    pub const fn variant(&self) -> DSM_DITHER_LVL_A {
738        match self.bits {
739            0 => DSM_DITHER_LVL_A::N_O,
740            1 => DSM_DITHER_LVL_A::M_IN,
741            2 => DSM_DITHER_LVL_A::M_IDDLE,
742            3 => DSM_DITHER_LVL_A::M_AX,
743            _ => unreachable!(),
744        }
745    }
746    #[doc = "No Level"]
747    #[inline(always)]
748    pub fn is_n_o(&self) -> bool {
749        *self == DSM_DITHER_LVL_A::N_O
750    }
751    #[doc = "Min Level"]
752    #[inline(always)]
753    pub fn is_m_in(&self) -> bool {
754        *self == DSM_DITHER_LVL_A::M_IN
755    }
756    #[doc = "Middle Level"]
757    #[inline(always)]
758    pub fn is_m_iddle(&self) -> bool {
759        *self == DSM_DITHER_LVL_A::M_IDDLE
760    }
761    #[doc = "Max Level"]
762    #[inline(always)]
763    pub fn is_m_ax(&self) -> bool {
764        *self == DSM_DITHER_LVL_A::M_AX
765    }
766}
767#[doc = "Field `dsm_dither_lvl` writer - Dither Level Control (Dither level is positive ralated to the ctrl bits)"]
768pub type DSM_DITHER_LVL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DSM_DITHER_LVL_A>;
769impl<'a, REG> DSM_DITHER_LVL_W<'a, REG>
770where
771    REG: crate::Writable + crate::RegisterSpec,
772    REG::Ux: From<u8>,
773{
774    #[doc = "No Level"]
775    #[inline(always)]
776    pub fn n_o(self) -> &'a mut crate::W<REG> {
777        self.variant(DSM_DITHER_LVL_A::N_O)
778    }
779    #[doc = "Min Level"]
780    #[inline(always)]
781    pub fn m_in(self) -> &'a mut crate::W<REG> {
782        self.variant(DSM_DITHER_LVL_A::M_IN)
783    }
784    #[doc = "Middle Level"]
785    #[inline(always)]
786    pub fn m_iddle(self) -> &'a mut crate::W<REG> {
787        self.variant(DSM_DITHER_LVL_A::M_IDDLE)
788    }
789    #[doc = "Max Level"]
790    #[inline(always)]
791    pub fn m_ax(self) -> &'a mut crate::W<REG> {
792        self.variant(DSM_DITHER_LVL_A::M_AX)
793    }
794}
795#[doc = "Field `fminlg` reader - FMINL Gain Control"]
796pub type FMINLG_R = crate::BitReader<FMINLG_A>;
797#[doc = "FMINL Gain Control\n\nValue on reset: 0"]
798#[derive(Clone, Copy, Debug, PartialEq, Eq)]
799pub enum FMINLG_A {
800    #[doc = "0: 0 dB"]
801    _0DB = 0,
802    #[doc = "1: 6 dB"]
803    _6DB = 1,
804}
805impl From<FMINLG_A> for bool {
806    #[inline(always)]
807    fn from(variant: FMINLG_A) -> Self {
808        variant as u8 != 0
809    }
810}
811impl FMINLG_R {
812    #[doc = "Get enumerated values variant"]
813    #[inline(always)]
814    pub const fn variant(&self) -> FMINLG_A {
815        match self.bits {
816            false => FMINLG_A::_0DB,
817            true => FMINLG_A::_6DB,
818        }
819    }
820    #[doc = "0 dB"]
821    #[inline(always)]
822    pub fn is_0db(&self) -> bool {
823        *self == FMINLG_A::_0DB
824    }
825    #[doc = "6 dB"]
826    #[inline(always)]
827    pub fn is_6db(&self) -> bool {
828        *self == FMINLG_A::_6DB
829    }
830}
831#[doc = "Field `fminlg` writer - FMINL Gain Control"]
832pub type FMINLG_W<'a, REG> = crate::BitWriter<'a, REG, FMINLG_A>;
833impl<'a, REG> FMINLG_W<'a, REG>
834where
835    REG: crate::Writable + crate::RegisterSpec,
836{
837    #[doc = "0 dB"]
838    #[inline(always)]
839    pub fn _0db(self) -> &'a mut crate::W<REG> {
840        self.variant(FMINLG_A::_0DB)
841    }
842    #[doc = "6 dB"]
843    #[inline(always)]
844    pub fn _6db(self) -> &'a mut crate::W<REG> {
845        self.variant(FMINLG_A::_6DB)
846    }
847}
848#[doc = "Field `fminlen` reader - FMINL Enable"]
849pub type FMINLEN_R = crate::BitReader<FMINLEN_A>;
850#[doc = "FMINL Enable\n\nValue on reset: 0"]
851#[derive(Clone, Copy, Debug, PartialEq, Eq)]
852pub enum FMINLEN_A {
853    #[doc = "0: Disable"]
854    DISABLE = 0,
855    #[doc = "1: Enable"]
856    ENABLE = 1,
857}
858impl From<FMINLEN_A> for bool {
859    #[inline(always)]
860    fn from(variant: FMINLEN_A) -> Self {
861        variant as u8 != 0
862    }
863}
864impl FMINLEN_R {
865    #[doc = "Get enumerated values variant"]
866    #[inline(always)]
867    pub const fn variant(&self) -> FMINLEN_A {
868        match self.bits {
869            false => FMINLEN_A::DISABLE,
870            true => FMINLEN_A::ENABLE,
871        }
872    }
873    #[doc = "Disable"]
874    #[inline(always)]
875    pub fn is_disable(&self) -> bool {
876        *self == FMINLEN_A::DISABLE
877    }
878    #[doc = "Enable"]
879    #[inline(always)]
880    pub fn is_enable(&self) -> bool {
881        *self == FMINLEN_A::ENABLE
882    }
883}
884#[doc = "Field `fminlen` writer - FMINL Enable"]
885pub type FMINLEN_W<'a, REG> = crate::BitWriter<'a, REG, FMINLEN_A>;
886impl<'a, REG> FMINLEN_W<'a, REG>
887where
888    REG: crate::Writable + crate::RegisterSpec,
889{
890    #[doc = "Disable"]
891    #[inline(always)]
892    pub fn disable(self) -> &'a mut crate::W<REG> {
893        self.variant(FMINLEN_A::DISABLE)
894    }
895    #[doc = "Enable"]
896    #[inline(always)]
897    pub fn enable(self) -> &'a mut crate::W<REG> {
898        self.variant(FMINLEN_A::ENABLE)
899    }
900}
901#[doc = "Field `mic_sin_en` reader - MIC Single Input Enable"]
902pub type MIC_SIN_EN_R = crate::BitReader<MIC_SIN_EN_A>;
903#[doc = "MIC Single Input Enable\n\nValue on reset: 0"]
904#[derive(Clone, Copy, Debug, PartialEq, Eq)]
905pub enum MIC_SIN_EN_A {
906    #[doc = "0: Disable"]
907    DISABLE = 0,
908    #[doc = "1: Enable"]
909    ENABLE = 1,
910}
911impl From<MIC_SIN_EN_A> for bool {
912    #[inline(always)]
913    fn from(variant: MIC_SIN_EN_A) -> Self {
914        variant as u8 != 0
915    }
916}
917impl MIC_SIN_EN_R {
918    #[doc = "Get enumerated values variant"]
919    #[inline(always)]
920    pub const fn variant(&self) -> MIC_SIN_EN_A {
921        match self.bits {
922            false => MIC_SIN_EN_A::DISABLE,
923            true => MIC_SIN_EN_A::ENABLE,
924        }
925    }
926    #[doc = "Disable"]
927    #[inline(always)]
928    pub fn is_disable(&self) -> bool {
929        *self == MIC_SIN_EN_A::DISABLE
930    }
931    #[doc = "Enable"]
932    #[inline(always)]
933    pub fn is_enable(&self) -> bool {
934        *self == MIC_SIN_EN_A::ENABLE
935    }
936}
937#[doc = "Field `mic_sin_en` writer - MIC Single Input Enable"]
938pub type MIC_SIN_EN_W<'a, REG> = crate::BitWriter<'a, REG, MIC_SIN_EN_A>;
939impl<'a, REG> MIC_SIN_EN_W<'a, REG>
940where
941    REG: crate::Writable + crate::RegisterSpec,
942{
943    #[doc = "Disable"]
944    #[inline(always)]
945    pub fn disable(self) -> &'a mut crate::W<REG> {
946        self.variant(MIC_SIN_EN_A::DISABLE)
947    }
948    #[doc = "Enable"]
949    #[inline(always)]
950    pub fn enable(self) -> &'a mut crate::W<REG> {
951        self.variant(MIC_SIN_EN_A::ENABLE)
952    }
953}
954#[doc = "Field `adc_d_itcher_c_ontrol` reader - Dither Control"]
955pub type ADC_D_ITCHER_C_ONTROL_R = crate::BitReader<ADC_D_ITCHER_C_ONTROL_A>;
956#[doc = "Dither Control\n\nValue on reset: 0"]
957#[derive(Clone, Copy, Debug, PartialEq, Eq)]
958pub enum ADC_D_ITCHER_C_ONTROL_A {
959    #[doc = "0: New Dither Off"]
960    N_EW_D_ITHER_O_FF = 0,
961    #[doc = "1: New Dither On"]
962    N_EW_D_ITHER_O_N = 1,
963}
964impl From<ADC_D_ITCHER_C_ONTROL_A> for bool {
965    #[inline(always)]
966    fn from(variant: ADC_D_ITCHER_C_ONTROL_A) -> Self {
967        variant as u8 != 0
968    }
969}
970impl ADC_D_ITCHER_C_ONTROL_R {
971    #[doc = "Get enumerated values variant"]
972    #[inline(always)]
973    pub const fn variant(&self) -> ADC_D_ITCHER_C_ONTROL_A {
974        match self.bits {
975            false => ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_FF,
976            true => ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_N,
977        }
978    }
979    #[doc = "New Dither Off"]
980    #[inline(always)]
981    pub fn is_n_ew_d_ither_o_ff(&self) -> bool {
982        *self == ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_FF
983    }
984    #[doc = "New Dither On"]
985    #[inline(always)]
986    pub fn is_n_ew_d_ither_o_n(&self) -> bool {
987        *self == ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_N
988    }
989}
990#[doc = "Field `adc_d_itcher_c_ontrol` writer - Dither Control"]
991pub type ADC_D_ITCHER_C_ONTROL_W<'a, REG> = crate::BitWriter<'a, REG, ADC_D_ITCHER_C_ONTROL_A>;
992impl<'a, REG> ADC_D_ITCHER_C_ONTROL_W<'a, REG>
993where
994    REG: crate::Writable + crate::RegisterSpec,
995{
996    #[doc = "New Dither Off"]
997    #[inline(always)]
998    pub fn n_ew_d_ither_o_ff(self) -> &'a mut crate::W<REG> {
999        self.variant(ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_FF)
1000    }
1001    #[doc = "New Dither On"]
1002    #[inline(always)]
1003    pub fn n_ew_d_ither_o_n(self) -> &'a mut crate::W<REG> {
1004        self.variant(ADC_D_ITCHER_C_ONTROL_A::N_EW_D_ITHER_O_N)
1005    }
1006}
1007#[doc = "Field `mic_pga_en` reader - MIC PGA Enable"]
1008pub type MIC_PGA_EN_R = crate::BitReader<MIC_PGA_EN_A>;
1009#[doc = "MIC PGA Enable\n\nValue on reset: 0"]
1010#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1011pub enum MIC_PGA_EN_A {
1012    #[doc = "0: Disabled"]
1013    DISABLED = 0,
1014    #[doc = "1: Enabled"]
1015    ENABLED = 1,
1016}
1017impl From<MIC_PGA_EN_A> for bool {
1018    #[inline(always)]
1019    fn from(variant: MIC_PGA_EN_A) -> Self {
1020        variant as u8 != 0
1021    }
1022}
1023impl MIC_PGA_EN_R {
1024    #[doc = "Get enumerated values variant"]
1025    #[inline(always)]
1026    pub const fn variant(&self) -> MIC_PGA_EN_A {
1027        match self.bits {
1028            false => MIC_PGA_EN_A::DISABLED,
1029            true => MIC_PGA_EN_A::ENABLED,
1030        }
1031    }
1032    #[doc = "Disabled"]
1033    #[inline(always)]
1034    pub fn is_disabled(&self) -> bool {
1035        *self == MIC_PGA_EN_A::DISABLED
1036    }
1037    #[doc = "Enabled"]
1038    #[inline(always)]
1039    pub fn is_enabled(&self) -> bool {
1040        *self == MIC_PGA_EN_A::ENABLED
1041    }
1042}
1043#[doc = "Field `mic_pga_en` writer - MIC PGA Enable"]
1044pub type MIC_PGA_EN_W<'a, REG> = crate::BitWriter<'a, REG, MIC_PGA_EN_A>;
1045impl<'a, REG> MIC_PGA_EN_W<'a, REG>
1046where
1047    REG: crate::Writable + crate::RegisterSpec,
1048{
1049    #[doc = "Disabled"]
1050    #[inline(always)]
1051    pub fn disabled(self) -> &'a mut crate::W<REG> {
1052        self.variant(MIC_PGA_EN_A::DISABLED)
1053    }
1054    #[doc = "Enabled"]
1055    #[inline(always)]
1056    pub fn enabled(self) -> &'a mut crate::W<REG> {
1057        self.variant(MIC_PGA_EN_A::ENABLED)
1058    }
1059}
1060#[doc = "Field `adc_en` reader - ADC Channel Enable"]
1061pub type ADC_EN_R = crate::BitReader<ADC_EN_A>;
1062#[doc = "ADC Channel Enable\n\nValue on reset: 0"]
1063#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1064pub enum ADC_EN_A {
1065    #[doc = "0: Disabled"]
1066    DISABLED = 0,
1067    #[doc = "1: Enabled"]
1068    ENABLED = 1,
1069}
1070impl From<ADC_EN_A> for bool {
1071    #[inline(always)]
1072    fn from(variant: ADC_EN_A) -> Self {
1073        variant as u8 != 0
1074    }
1075}
1076impl ADC_EN_R {
1077    #[doc = "Get enumerated values variant"]
1078    #[inline(always)]
1079    pub const fn variant(&self) -> ADC_EN_A {
1080        match self.bits {
1081            false => ADC_EN_A::DISABLED,
1082            true => ADC_EN_A::ENABLED,
1083        }
1084    }
1085    #[doc = "Disabled"]
1086    #[inline(always)]
1087    pub fn is_disabled(&self) -> bool {
1088        *self == ADC_EN_A::DISABLED
1089    }
1090    #[doc = "Enabled"]
1091    #[inline(always)]
1092    pub fn is_enabled(&self) -> bool {
1093        *self == ADC_EN_A::ENABLED
1094    }
1095}
1096#[doc = "Field `adc_en` writer - ADC Channel Enable"]
1097pub type ADC_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC_EN_A>;
1098impl<'a, REG> ADC_EN_W<'a, REG>
1099where
1100    REG: crate::Writable + crate::RegisterSpec,
1101{
1102    #[doc = "Disabled"]
1103    #[inline(always)]
1104    pub fn disabled(self) -> &'a mut crate::W<REG> {
1105        self.variant(ADC_EN_A::DISABLED)
1106    }
1107    #[doc = "Enabled"]
1108    #[inline(always)]
1109    pub fn enabled(self) -> &'a mut crate::W<REG> {
1110        self.variant(ADC_EN_A::ENABLED)
1111    }
1112}
1113impl R {
1114    #[doc = "Bits 0:1 - ADC OP MIC Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1115    #[inline(always)]
1116    pub fn adc_iopmic(&self) -> ADC_IOPMIC_R {
1117        ADC_IOPMIC_R::new((self.bits & 3) as u8)
1118    }
1119    #[doc = "ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_iopsdm2` field"]
1120    #[inline(always)]
1121    pub fn adc_iopsdm(&self, n: u8) -> ADC_IOPSDM_R {
1122        #[allow(clippy::no_effect)]
1123        [(); 2][n as usize];
1124        ADC_IOPSDM_R::new(((self.bits >> (n * 2 + 4)) & 3) as u8)
1125    }
1126    #[doc = "Bits 4:5 - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1127    #[inline(always)]
1128    pub fn adc_iopsdm2(&self) -> ADC_IOPSDM_R {
1129        ADC_IOPSDM_R::new(((self.bits >> 4) & 3) as u8)
1130    }
1131    #[doc = "Bits 6:7 - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1132    #[inline(always)]
1133    pub fn adc_iopsdm1(&self) -> ADC_IOPSDM_R {
1134        ADC_IOPSDM_R::new(((self.bits >> 6) & 3) as u8)
1135    }
1136    #[doc = "Bits 6:7 - ADC OP AAF Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nFor example: ADC_REG&lt;15:14> = 11, IOPADC = 4 uA \n\n00: 1.50*4 uA = 6 uA \n\n01: 1.75*4 uA = 7 uA \n\n10: 2.00*4 uA = 8 uA \n\n11: 2.25*4 uA = 9 uA"]
1137    #[inline(always)]
1138    pub fn adc_iopaaf(&self) -> ADC_IOPAAF_R {
1139        ADC_IOPAAF_R::new(((self.bits >> 6) & 3) as u8)
1140    }
1141    #[doc = "Bits 8:12 - ADC PGA gain settings:\n\n\n\n0x0: 0 dB \\t0x10: 21 dB \n\n0x1: 6 dB \\t0x11: 22 dB \n\n0x2: 6 dB \\t0x12: 23 dB \n\n0x3: 6 dB \\t0x13: 24 dB \n\n0x4: 9 dB \\t0x14: 25 dB \n\n0x5: 10 dB\\t0x15: 26 dB \n\n0x6: 11 dB\\t0x16: 27 dB \n\n0x7: 12 dB\\t0x17: 28 dB \n\n0x8: 13 dB\\t0x18: 29 dB \n\n0x9: 14 dB\\t0x19: 30 dB \n\n0xA: 15 dB\\t0x1A: 31 dB \n\n0xB: 16 dB\\t0x1B: 32 dB \n\n0xC: 17 dB\\t0x1C: 33 dB \n\n0xD: 18 dB\\t0x1D: 34 dB \n\n0xE: 19 dB\\t0x1E: 35 dB \n\n0xF: 20 dB\\t0x1F: 36 dB"]
1142    #[inline(always)]
1143    pub fn adc_pga_gain_ctrl(&self) -> ADC_PGA_GAIN_CTRL_R {
1144        ADC_PGA_GAIN_CTRL_R::new(((self.bits >> 8) & 0x1f) as u8)
1145    }
1146    #[doc = "Bits 14:15 - ADC1-ADC3 Bias Current Select"]
1147    #[inline(always)]
1148    pub fn iopadc(&self) -> IOPADC_R {
1149        IOPADC_R::new(((self.bits >> 14) & 3) as u8)
1150    }
1151    #[doc = "Bits 16:17 - ADC PGA Common-Mode Voltage Control"]
1152    #[inline(always)]
1153    pub fn adc_pga_in_vcm_ctrl(&self) -> ADC_PGA_IN_VCM_CTRL_R {
1154        ADC_PGA_IN_VCM_CTRL_R::new(((self.bits >> 16) & 3) as u8)
1155    }
1156    #[doc = "Bits 18:19 - ADC PGA Common Mode Input Impedance Control for MICIN"]
1157    #[inline(always)]
1158    pub fn adc_pga_ctrl_rcm(&self) -> ADC_PGA_CTRL_RCM_R {
1159        ADC_PGA_CTRL_RCM_R::new(((self.bits >> 18) & 3) as u8)
1160    }
1161    #[doc = "Bits 20:21 - PGA Vcm Buffer OP Bias Current Select"]
1162    #[inline(always)]
1163    pub fn iopbuffer(&self) -> IOPBUFFER_R {
1164        IOPBUFFER_R::new(((self.bits >> 20) & 3) as u8)
1165    }
1166    #[doc = "Bit 22 - LINEINL Gain Control"]
1167    #[inline(always)]
1168    pub fn lineinlg(&self) -> LINEINLG_R {
1169        LINEINLG_R::new(((self.bits >> 22) & 1) != 0)
1170    }
1171    #[doc = "Bit 23 - LINEINL Enable"]
1172    #[inline(always)]
1173    pub fn lineinlen(&self) -> LINEINLEN_R {
1174        LINEINLEN_R::new(((self.bits >> 23) & 1) != 0)
1175    }
1176    #[doc = "Bits 24:25 - Dither Level Control (Dither level is positive ralated to the ctrl bits)"]
1177    #[inline(always)]
1178    pub fn dsm_dither_lvl(&self) -> DSM_DITHER_LVL_R {
1179        DSM_DITHER_LVL_R::new(((self.bits >> 24) & 3) as u8)
1180    }
1181    #[doc = "Bit 26 - FMINL Gain Control"]
1182    #[inline(always)]
1183    pub fn fminlg(&self) -> FMINLG_R {
1184        FMINLG_R::new(((self.bits >> 26) & 1) != 0)
1185    }
1186    #[doc = "Bit 27 - FMINL Enable"]
1187    #[inline(always)]
1188    pub fn fminlen(&self) -> FMINLEN_R {
1189        FMINLEN_R::new(((self.bits >> 27) & 1) != 0)
1190    }
1191    #[doc = "Bit 28 - MIC Single Input Enable"]
1192    #[inline(always)]
1193    pub fn mic_sin_en(&self) -> MIC_SIN_EN_R {
1194        MIC_SIN_EN_R::new(((self.bits >> 28) & 1) != 0)
1195    }
1196    #[doc = "Bit 29 - Dither Control"]
1197    #[inline(always)]
1198    pub fn adc_d_itcher_c_ontrol(&self) -> ADC_D_ITCHER_C_ONTROL_R {
1199        ADC_D_ITCHER_C_ONTROL_R::new(((self.bits >> 29) & 1) != 0)
1200    }
1201    #[doc = "Bit 30 - MIC PGA Enable"]
1202    #[inline(always)]
1203    pub fn mic_pga_en(&self) -> MIC_PGA_EN_R {
1204        MIC_PGA_EN_R::new(((self.bits >> 30) & 1) != 0)
1205    }
1206    #[doc = "Bit 31 - ADC Channel Enable"]
1207    #[inline(always)]
1208    pub fn adc_en(&self) -> ADC_EN_R {
1209        ADC_EN_R::new(((self.bits >> 31) & 1) != 0)
1210    }
1211}
1212impl W {
1213    #[doc = "Bits 0:1 - ADC OP MIC Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1214    #[inline(always)]
1215    #[must_use]
1216    pub fn adc_iopmic(&mut self) -> ADC_IOPMIC_W<ADC_SPEC> {
1217        ADC_IOPMIC_W::new(self, 0)
1218    }
1219    #[doc = "ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_iopsdm2` field"]
1220    #[inline(always)]
1221    #[must_use]
1222    pub fn adc_iopsdm(&mut self, n: u8) -> ADC_IOPSDM_W<ADC_SPEC> {
1223        #[allow(clippy::no_effect)]
1224        [(); 2][n as usize];
1225        ADC_IOPSDM_W::new(self, n * 2 + 4)
1226    }
1227    #[doc = "Bits 4:5 - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1228    #[inline(always)]
1229    #[must_use]
1230    pub fn adc_iopsdm2(&mut self) -> ADC_IOPSDM_W<ADC_SPEC> {
1231        ADC_IOPSDM_W::new(self, 4)
1232    }
1233    #[doc = "Bits 6:7 - ADC OP SDM Bias Current Select \\[i\\]\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA."]
1234    #[inline(always)]
1235    #[must_use]
1236    pub fn adc_iopsdm1(&mut self) -> ADC_IOPSDM_W<ADC_SPEC> {
1237        ADC_IOPSDM_W::new(self, 6)
1238    }
1239    #[doc = "Bits 6:7 - ADC OP AAF Bias Current Select\n\nIOPADC is defined by ADC_REG&lt;15:14> from 1 uA to 4 uA.\n\nFor example: ADC_REG&lt;15:14> = 11, IOPADC = 4 uA \n\n00: 1.50*4 uA = 6 uA \n\n01: 1.75*4 uA = 7 uA \n\n10: 2.00*4 uA = 8 uA \n\n11: 2.25*4 uA = 9 uA"]
1240    #[inline(always)]
1241    #[must_use]
1242    pub fn adc_iopaaf(&mut self) -> ADC_IOPAAF_W<ADC_SPEC> {
1243        ADC_IOPAAF_W::new(self, 6)
1244    }
1245    #[doc = "Bits 8:12 - ADC PGA gain settings:\n\n\n\n0x0: 0 dB \\t0x10: 21 dB \n\n0x1: 6 dB \\t0x11: 22 dB \n\n0x2: 6 dB \\t0x12: 23 dB \n\n0x3: 6 dB \\t0x13: 24 dB \n\n0x4: 9 dB \\t0x14: 25 dB \n\n0x5: 10 dB\\t0x15: 26 dB \n\n0x6: 11 dB\\t0x16: 27 dB \n\n0x7: 12 dB\\t0x17: 28 dB \n\n0x8: 13 dB\\t0x18: 29 dB \n\n0x9: 14 dB\\t0x19: 30 dB \n\n0xA: 15 dB\\t0x1A: 31 dB \n\n0xB: 16 dB\\t0x1B: 32 dB \n\n0xC: 17 dB\\t0x1C: 33 dB \n\n0xD: 18 dB\\t0x1D: 34 dB \n\n0xE: 19 dB\\t0x1E: 35 dB \n\n0xF: 20 dB\\t0x1F: 36 dB"]
1246    #[inline(always)]
1247    #[must_use]
1248    pub fn adc_pga_gain_ctrl(&mut self) -> ADC_PGA_GAIN_CTRL_W<ADC_SPEC> {
1249        ADC_PGA_GAIN_CTRL_W::new(self, 8)
1250    }
1251    #[doc = "Bits 14:15 - ADC1-ADC3 Bias Current Select"]
1252    #[inline(always)]
1253    #[must_use]
1254    pub fn iopadc(&mut self) -> IOPADC_W<ADC_SPEC> {
1255        IOPADC_W::new(self, 14)
1256    }
1257    #[doc = "Bits 16:17 - ADC PGA Common-Mode Voltage Control"]
1258    #[inline(always)]
1259    #[must_use]
1260    pub fn adc_pga_in_vcm_ctrl(&mut self) -> ADC_PGA_IN_VCM_CTRL_W<ADC_SPEC> {
1261        ADC_PGA_IN_VCM_CTRL_W::new(self, 16)
1262    }
1263    #[doc = "Bits 18:19 - ADC PGA Common Mode Input Impedance Control for MICIN"]
1264    #[inline(always)]
1265    #[must_use]
1266    pub fn adc_pga_ctrl_rcm(&mut self) -> ADC_PGA_CTRL_RCM_W<ADC_SPEC> {
1267        ADC_PGA_CTRL_RCM_W::new(self, 18)
1268    }
1269    #[doc = "Bits 20:21 - PGA Vcm Buffer OP Bias Current Select"]
1270    #[inline(always)]
1271    #[must_use]
1272    pub fn iopbuffer(&mut self) -> IOPBUFFER_W<ADC_SPEC> {
1273        IOPBUFFER_W::new(self, 20)
1274    }
1275    #[doc = "Bit 22 - LINEINL Gain Control"]
1276    #[inline(always)]
1277    #[must_use]
1278    pub fn lineinlg(&mut self) -> LINEINLG_W<ADC_SPEC> {
1279        LINEINLG_W::new(self, 22)
1280    }
1281    #[doc = "Bit 23 - LINEINL Enable"]
1282    #[inline(always)]
1283    #[must_use]
1284    pub fn lineinlen(&mut self) -> LINEINLEN_W<ADC_SPEC> {
1285        LINEINLEN_W::new(self, 23)
1286    }
1287    #[doc = "Bits 24:25 - Dither Level Control (Dither level is positive ralated to the ctrl bits)"]
1288    #[inline(always)]
1289    #[must_use]
1290    pub fn dsm_dither_lvl(&mut self) -> DSM_DITHER_LVL_W<ADC_SPEC> {
1291        DSM_DITHER_LVL_W::new(self, 24)
1292    }
1293    #[doc = "Bit 26 - FMINL Gain Control"]
1294    #[inline(always)]
1295    #[must_use]
1296    pub fn fminlg(&mut self) -> FMINLG_W<ADC_SPEC> {
1297        FMINLG_W::new(self, 26)
1298    }
1299    #[doc = "Bit 27 - FMINL Enable"]
1300    #[inline(always)]
1301    #[must_use]
1302    pub fn fminlen(&mut self) -> FMINLEN_W<ADC_SPEC> {
1303        FMINLEN_W::new(self, 27)
1304    }
1305    #[doc = "Bit 28 - MIC Single Input Enable"]
1306    #[inline(always)]
1307    #[must_use]
1308    pub fn mic_sin_en(&mut self) -> MIC_SIN_EN_W<ADC_SPEC> {
1309        MIC_SIN_EN_W::new(self, 28)
1310    }
1311    #[doc = "Bit 29 - Dither Control"]
1312    #[inline(always)]
1313    #[must_use]
1314    pub fn adc_d_itcher_c_ontrol(&mut self) -> ADC_D_ITCHER_C_ONTROL_W<ADC_SPEC> {
1315        ADC_D_ITCHER_C_ONTROL_W::new(self, 29)
1316    }
1317    #[doc = "Bit 30 - MIC PGA Enable"]
1318    #[inline(always)]
1319    #[must_use]
1320    pub fn mic_pga_en(&mut self) -> MIC_PGA_EN_W<ADC_SPEC> {
1321        MIC_PGA_EN_W::new(self, 30)
1322    }
1323    #[doc = "Bit 31 - ADC Channel Enable"]
1324    #[inline(always)]
1325    #[must_use]
1326    pub fn adc_en(&mut self) -> ADC_EN_W<ADC_SPEC> {
1327        ADC_EN_W::new(self, 31)
1328    }
1329    #[doc = r" Writes raw bits to the register."]
1330    #[doc = r""]
1331    #[doc = r" # Safety"]
1332    #[doc = r""]
1333    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1334    #[inline(always)]
1335    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1336        self.bits = bits;
1337        self
1338    }
1339}
1340#[doc = "ADC\\[i\\] Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1341pub struct ADC_SPEC;
1342impl crate::RegisterSpec for ADC_SPEC {
1343    type Ux = u32;
1344}
1345#[doc = "`read()` method returns [`adc::R`](R) reader structure"]
1346impl crate::Readable for ADC_SPEC {}
1347#[doc = "`write(|w| ..)` method takes [`adc::W`](W) writer structure"]
1348impl crate::Writable for ADC_SPEC {
1349    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1350    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1351}
1352#[doc = "`reset()` method sets adc%s to value 0x001c_c055"]
1353impl crate::Resettable for ADC_SPEC {
1354    const RESET_VALUE: Self::Ux = 0x001c_c055;
1355}
d1_pac/audio_codec/adc.rs

d1_pac/audio_codec/
adc.rs
