d1_pac/audio_codec/
ac_dac_fifos.rs

1#[doc = "Register `ac_dac_fifos` reader"]
2pub type R = crate::R<AC_DAC_FIFOS_SPEC>;
3#[doc = "Register `ac_dac_fifos` writer"]
4pub type W = crate::W<AC_DAC_FIFOS_SPEC>;
5#[doc = "Field `txo_int` reader - TX FIFO Overrun Pending Interrupt"]
6pub type TXO_INT_R = crate::BitReader<TXO_INT_A>;
7#[doc = "TX FIFO Overrun Pending Interrupt\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TXO_INT_A {
10    #[doc = "0: `0`"]
11    NO_PENDING = 0,
12    #[doc = "1: `1`"]
13    PENDING = 1,
14}
15impl From<TXO_INT_A> for bool {
16    #[inline(always)]
17    fn from(variant: TXO_INT_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TXO_INT_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TXO_INT_A {
25        match self.bits {
26            false => TXO_INT_A::NO_PENDING,
27            true => TXO_INT_A::PENDING,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_pending(&self) -> bool {
33        *self == TXO_INT_A::NO_PENDING
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == TXO_INT_A::PENDING
39    }
40}
41#[doc = "Field `txo_int` writer - TX FIFO Overrun Pending Interrupt"]
42pub type TXO_INT_W<'a, REG> = crate::BitWriter<'a, REG, TXO_INT_A>;
43impl<'a, REG> TXO_INT_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_pending(self) -> &'a mut crate::W<REG> {
50        self.variant(TXO_INT_A::NO_PENDING)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(TXO_INT_A::PENDING)
56    }
57}
58#[doc = "Field `txu_int` reader - TX FIFO Underrun Pending Interrupt"]
59pub type TXU_INT_R = crate::BitReader<TXU_INT_A>;
60#[doc = "TX FIFO Underrun Pending Interrupt\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TXU_INT_A {
63    #[doc = "0: `0`"]
64    NO_PENDING = 0,
65    #[doc = "1: `1`"]
66    PENDING = 1,
67}
68impl From<TXU_INT_A> for bool {
69    #[inline(always)]
70    fn from(variant: TXU_INT_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TXU_INT_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TXU_INT_A {
78        match self.bits {
79            false => TXU_INT_A::NO_PENDING,
80            true => TXU_INT_A::PENDING,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_no_pending(&self) -> bool {
86        *self == TXU_INT_A::NO_PENDING
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_pending(&self) -> bool {
91        *self == TXU_INT_A::PENDING
92    }
93}
94#[doc = "Field `txu_int` writer - TX FIFO Underrun Pending Interrupt"]
95pub type TXU_INT_W<'a, REG> = crate::BitWriter<'a, REG, TXU_INT_A>;
96impl<'a, REG> TXU_INT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn no_pending(self) -> &'a mut crate::W<REG> {
103        self.variant(TXU_INT_A::NO_PENDING)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn pending(self) -> &'a mut crate::W<REG> {
108        self.variant(TXU_INT_A::PENDING)
109    }
110}
111#[doc = "Field `txe_int` reader - TX FIFO Empty Pending Interrupt"]
112pub type TXE_INT_R = crate::BitReader<TXE_INT_A>;
113#[doc = "TX FIFO Empty Pending Interrupt\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TXE_INT_A {
116    #[doc = "0: `0`"]
117    NO_PENDING = 0,
118    #[doc = "1: `1`"]
119    PENDING = 1,
120}
121impl From<TXE_INT_A> for bool {
122    #[inline(always)]
123    fn from(variant: TXE_INT_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TXE_INT_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TXE_INT_A {
131        match self.bits {
132            false => TXE_INT_A::NO_PENDING,
133            true => TXE_INT_A::PENDING,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_no_pending(&self) -> bool {
139        *self == TXE_INT_A::NO_PENDING
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_pending(&self) -> bool {
144        *self == TXE_INT_A::PENDING
145    }
146}
147#[doc = "Field `txe_int` writer - TX FIFO Empty Pending Interrupt"]
148pub type TXE_INT_W<'a, REG> = crate::BitWriter<'a, REG, TXE_INT_A>;
149impl<'a, REG> TXE_INT_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn no_pending(self) -> &'a mut crate::W<REG> {
156        self.variant(TXE_INT_A::NO_PENDING)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn pending(self) -> &'a mut crate::W<REG> {
161        self.variant(TXE_INT_A::PENDING)
162    }
163}
164#[doc = "Field `txe_cnt` reader - TX FIFO Empty Space Word Counter"]
165pub type TXE_CNT_R = crate::FieldReader<u16>;
166#[doc = "Field `tx_empty` reader - TX FIFO Empty"]
167pub type TX_EMPTY_R = crate::BitReader<TX_EMPTY_A>;
168#[doc = "TX FIFO Empty\n\nValue on reset: 0"]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum TX_EMPTY_A {
171    #[doc = "0: `0`"]
172    NO_ROOM = 0,
173    #[doc = "1: `1`"]
174    ROOM = 1,
175}
176impl From<TX_EMPTY_A> for bool {
177    #[inline(always)]
178    fn from(variant: TX_EMPTY_A) -> Self {
179        variant as u8 != 0
180    }
181}
182impl TX_EMPTY_R {
183    #[doc = "Get enumerated values variant"]
184    #[inline(always)]
185    pub const fn variant(&self) -> TX_EMPTY_A {
186        match self.bits {
187            false => TX_EMPTY_A::NO_ROOM,
188            true => TX_EMPTY_A::ROOM,
189        }
190    }
191    #[doc = "`0`"]
192    #[inline(always)]
193    pub fn is_no_room(&self) -> bool {
194        *self == TX_EMPTY_A::NO_ROOM
195    }
196    #[doc = "`1`"]
197    #[inline(always)]
198    pub fn is_room(&self) -> bool {
199        *self == TX_EMPTY_A::ROOM
200    }
201}
202impl R {
203    #[doc = "Bit 1 - TX FIFO Overrun Pending Interrupt"]
204    #[inline(always)]
205    pub fn txo_int(&self) -> TXO_INT_R {
206        TXO_INT_R::new(((self.bits >> 1) & 1) != 0)
207    }
208    #[doc = "Bit 2 - TX FIFO Underrun Pending Interrupt"]
209    #[inline(always)]
210    pub fn txu_int(&self) -> TXU_INT_R {
211        TXU_INT_R::new(((self.bits >> 2) & 1) != 0)
212    }
213    #[doc = "Bit 3 - TX FIFO Empty Pending Interrupt"]
214    #[inline(always)]
215    pub fn txe_int(&self) -> TXE_INT_R {
216        TXE_INT_R::new(((self.bits >> 3) & 1) != 0)
217    }
218    #[doc = "Bits 8:22 - TX FIFO Empty Space Word Counter"]
219    #[inline(always)]
220    pub fn txe_cnt(&self) -> TXE_CNT_R {
221        TXE_CNT_R::new(((self.bits >> 8) & 0x7fff) as u16)
222    }
223    #[doc = "Bit 23 - TX FIFO Empty"]
224    #[inline(always)]
225    pub fn tx_empty(&self) -> TX_EMPTY_R {
226        TX_EMPTY_R::new(((self.bits >> 23) & 1) != 0)
227    }
228}
229impl W {
230    #[doc = "Bit 1 - TX FIFO Overrun Pending Interrupt"]
231    #[inline(always)]
232    #[must_use]
233    pub fn txo_int(&mut self) -> TXO_INT_W<AC_DAC_FIFOS_SPEC> {
234        TXO_INT_W::new(self, 1)
235    }
236    #[doc = "Bit 2 - TX FIFO Underrun Pending Interrupt"]
237    #[inline(always)]
238    #[must_use]
239    pub fn txu_int(&mut self) -> TXU_INT_W<AC_DAC_FIFOS_SPEC> {
240        TXU_INT_W::new(self, 2)
241    }
242    #[doc = "Bit 3 - TX FIFO Empty Pending Interrupt"]
243    #[inline(always)]
244    #[must_use]
245    pub fn txe_int(&mut self) -> TXE_INT_W<AC_DAC_FIFOS_SPEC> {
246        TXE_INT_W::new(self, 3)
247    }
248    #[doc = r" Writes raw bits to the register."]
249    #[doc = r""]
250    #[doc = r" # Safety"]
251    #[doc = r""]
252    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
253    #[inline(always)]
254    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
255        self.bits = bits;
256        self
257    }
258}
259#[doc = "DAC FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_dac_fifos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_dac_fifos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
260pub struct AC_DAC_FIFOS_SPEC;
261impl crate::RegisterSpec for AC_DAC_FIFOS_SPEC {
262    type Ux = u32;
263}
264#[doc = "`read()` method returns [`ac_dac_fifos::R`](R) reader structure"]
265impl crate::Readable for AC_DAC_FIFOS_SPEC {}
266#[doc = "`write(|w| ..)` method takes [`ac_dac_fifos::W`](W) writer structure"]
267impl crate::Writable for AC_DAC_FIFOS_SPEC {
268    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
269    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
270}
271#[doc = "`reset()` method sets ac_dac_fifos to value 0"]
272impl crate::Resettable for AC_DAC_FIFOS_SPEC {
273    const RESET_VALUE: Self::Ux = 0;
274}
d1_pac/audio_codec/ac_dac_fifos.rs

d1_pac/audio_codec/
ac_dac_fifos.rs
