cyt6bj_a/m0/flashc1/flashcx/
flash_cmd.rs

1#[doc = "Register `FLASH_CMD` reader"]
2pub struct R(crate::R<FLASH_CMD_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FLASH_CMD_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FLASH_CMD_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FLASH_CMD_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FLASH_CMD` writer"]
17pub struct W(crate::W<FLASH_CMD_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FLASH_CMD_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FLASH_CMD_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FLASH_CMD_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `INV` reader - Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state."]
38pub type INV_R = crate::BitReader<bool>;
39#[doc = "Field `INV` writer - Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state."]
40pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLASH_CMD_SPEC, bool, O>;
41#[doc = "Field `BUFF_INV` reader - Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches."]
42pub type BUFF_INV_R = crate::BitReader<bool>;
43#[doc = "Field `BUFF_INV` writer - Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches."]
44pub type BUFF_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLASH_CMD_SPEC, bool, O>;
45impl R {
46    #[doc = "Bit 0 - Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state."]
47    #[inline(always)]
48    pub fn inv(&self) -> INV_R {
49        INV_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches."]
52    #[inline(always)]
53    pub fn buff_inv(&self) -> BUFF_INV_R {
54        BUFF_INV_R::new(((self.bits >> 1) & 1) != 0)
55    }
56}
57impl W {
58    #[doc = "Bit 0 - Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state."]
59    #[inline(always)]
60    #[must_use]
61    pub fn inv(&mut self) -> INV_W<0> {
62        INV_W::new(self)
63    }
64    #[doc = "Bit 1 - Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches."]
65    #[inline(always)]
66    #[must_use]
67    pub fn buff_inv(&mut self) -> BUFF_INV_W<1> {
68        BUFF_INV_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "Command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flash_cmd](index.html) module"]
78pub struct FLASH_CMD_SPEC;
79impl crate::RegisterSpec for FLASH_CMD_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [flash_cmd::R](R) reader structure"]
83impl crate::Readable for FLASH_CMD_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [flash_cmd::W](W) writer structure"]
87impl crate::Writable for FLASH_CMD_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets FLASH_CMD to value 0"]
93impl crate::Resettable for FLASH_CMD_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
cyt6bj_a/m0/flashc1/flashcx/flash_cmd.rs

cyt6bj_a/m0/flashc1/flashcx/
flash_cmd.rs
