cyt6bj_a/m0/flashc/flashcx/fm_ctl_ect/
intr_set.rs

1#[doc = "Register `INTR_SET` reader"]
2pub struct R(crate::R<INTR_SET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTR_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTR_SET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTR_SET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTR_SET` writer"]
17pub struct W(crate::W<INTR_SET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTR_SET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTR_SET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTR_SET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `INTR_SET` reader - Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."]
38pub type INTR_SET_R = crate::BitReader<bool>;
39#[doc = "Field `INTR_SET` writer - Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."]
40pub type INTR_SET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_SET_SPEC, bool, O>;
41impl R {
42    #[doc = "Bit 0 - Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."]
43    #[inline(always)]
44    pub fn intr_set(&self) -> INTR_SET_R {
45        INTR_SET_R::new((self.bits & 1) != 0)
46    }
47}
48impl W {
49    #[doc = "Bit 0 - Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."]
50    #[inline(always)]
51    #[must_use]
52    pub fn intr_set(&mut self) -> INTR_SET_W<0> {
53        INTR_SET_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "Interrupt Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_set](index.html) module"]
63pub struct INTR_SET_SPEC;
64impl crate::RegisterSpec for INTR_SET_SPEC {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [intr_set::R](R) reader structure"]
68impl crate::Readable for INTR_SET_SPEC {
69    type Reader = R;
70}
71#[doc = "`write(|w| ..)` method takes [intr_set::W](W) writer structure"]
72impl crate::Writable for INTR_SET_SPEC {
73    type Writer = W;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
76}
77#[doc = "`reset()` method sets INTR_SET to value 0"]
78impl crate::Resettable for INTR_SET_SPEC {
79    const RESET_VALUE: Self::Ux = 0;
80}
cyt6bj_a/m0/flashc/flashcx/fm_ctl_ect/intr_set.rs

cyt6bj_a/m0/flashc/flashcx/fm_ctl_ect/
intr_set.rs
