cyt6bj_a/m0/flashc/flashcx/
dmac_buff_ctl.rs

1#[doc = "Register `DMAC_BUFF_CTL` reader"]
2pub struct R(crate::R<DMAC_BUFF_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMAC_BUFF_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMAC_BUFF_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMAC_BUFF_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMAC_BUFF_CTL` writer"]
17pub struct W(crate::W<DMAC_BUFF_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMAC_BUFF_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMAC_BUFF_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMAC_BUFF_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PREF_EN` reader - See CRYPTO_BUFF_CTL."]
38pub type PREF_EN_R = crate::BitReader<bool>;
39#[doc = "Field `PREF_EN` writer - See CRYPTO_BUFF_CTL."]
40pub type PREF_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_BUFF_CTL_SPEC, bool, O>;
41impl R {
42    #[doc = "Bit 30 - See CRYPTO_BUFF_CTL."]
43    #[inline(always)]
44    pub fn pref_en(&self) -> PREF_EN_R {
45        PREF_EN_R::new(((self.bits >> 30) & 1) != 0)
46    }
47}
48impl W {
49    #[doc = "Bit 30 - See CRYPTO_BUFF_CTL."]
50    #[inline(always)]
51    #[must_use]
52    pub fn pref_en(&mut self) -> PREF_EN_W<30> {
53        PREF_EN_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "DMA controller buffer control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac_buff_ctl](index.html) module"]
63pub struct DMAC_BUFF_CTL_SPEC;
64impl crate::RegisterSpec for DMAC_BUFF_CTL_SPEC {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [dmac_buff_ctl::R](R) reader structure"]
68impl crate::Readable for DMAC_BUFF_CTL_SPEC {
69    type Reader = R;
70}
71#[doc = "`write(|w| ..)` method takes [dmac_buff_ctl::W](W) writer structure"]
72impl crate::Writable for DMAC_BUFF_CTL_SPEC {
73    type Writer = W;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
76}
77#[doc = "`reset()` method sets DMAC_BUFF_CTL to value 0x4000_0000"]
78impl crate::Resettable for DMAC_BUFF_CTL_SPEC {
79    const RESET_VALUE: Self::Ux = 0x4000_0000;
80}
cyt6bj_a/m0/flashc/flashcx/dmac_buff_ctl.rs

cyt6bj_a/m0/flashc/flashcx/
dmac_buff_ctl.rs
