cyt4en_a/m0/lpddr40/lpddr4_core/
rtgc1.rs

1#[doc = "Register `RTGC1` reader"]
2pub struct R(crate::R<RTGC1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RTGC1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RTGC1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RTGC1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RTGC1` writer"]
17pub struct W(crate::W<RTGC1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RTGC1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RTGC1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RTGC1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FS1_TWREN` reader - Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the dfi_wrdata_en signal is asserted. LPDDR4: WL-1"]
38pub type FS1_TWREN_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `FS1_TWREN` writer - Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the dfi_wrdata_en signal is asserted. LPDDR4: WL-1"]
40pub type FS1_TWREN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTGC1_SPEC, u8, u8, 6, O>;
41#[doc = "Field `FS1_TRDEN` reader - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal LPDDR4: RL-1"]
42pub type FS1_TRDEN_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `FS1_TRDEN` writer - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal LPDDR4: RL-1"]
44pub type FS1_TRDEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTGC1_SPEC, u8, u8, 6, O>;
45#[doc = "Field `FS1_TRDENDBI` reader - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal in DBI mode"]
46pub type FS1_TRDENDBI_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `FS1_TRDENDBI` writer - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal in DBI mode"]
48pub type FS1_TRDENDBI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTGC1_SPEC, u8, u8, 7, O>;
49impl R {
50    #[doc = "Bits 0:5 - Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the dfi_wrdata_en signal is asserted. LPDDR4: WL-1"]
51    #[inline(always)]
52    pub fn fs1_twren(&self) -> FS1_TWREN_R {
53        FS1_TWREN_R::new((self.bits & 0x3f) as u8)
54    }
55    #[doc = "Bits 6:11 - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal LPDDR4: RL-1"]
56    #[inline(always)]
57    pub fn fs1_trden(&self) -> FS1_TRDEN_R {
58        FS1_TRDEN_R::new(((self.bits >> 6) & 0x3f) as u8)
59    }
60    #[doc = "Bits 12:18 - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal in DBI mode"]
61    #[inline(always)]
62    pub fn fs1_trdendbi(&self) -> FS1_TRDENDBI_R {
63        FS1_TRDENDBI_R::new(((self.bits >> 12) & 0x7f) as u8)
64    }
65}
66impl W {
67    #[doc = "Bits 0:5 - Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the dfi_wrdata_en signal is asserted. LPDDR4: WL-1"]
68    #[inline(always)]
69    #[must_use]
70    pub fn fs1_twren(&mut self) -> FS1_TWREN_W<0> {
71        FS1_TWREN_W::new(self)
72    }
73    #[doc = "Bits 6:11 - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal LPDDR4: RL-1"]
74    #[inline(always)]
75    #[must_use]
76    pub fn fs1_trden(&mut self) -> FS1_TRDEN_W<6> {
77        FS1_TRDEN_W::new(self)
78    }
79    #[doc = "Bits 12:18 - Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal in DBI mode"]
80    #[inline(always)]
81    #[must_use]
82    pub fn fs1_trdendbi(&mut self) -> FS1_TRDENDBI_W<12> {
83        FS1_TRDENDBI_W::new(self)
84    }
85    #[doc = "Writes raw bits to the register."]
86    #[inline(always)]
87    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
88        self.0.bits(bits);
89        self
90    }
91}
92#[doc = "PHY Read Training General Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtgc1](index.html) module"]
93pub struct RTGC1_SPEC;
94impl crate::RegisterSpec for RTGC1_SPEC {
95    type Ux = u32;
96}
97#[doc = "`read()` method returns [rtgc1::R](R) reader structure"]
98impl crate::Readable for RTGC1_SPEC {
99    type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [rtgc1::W](W) writer structure"]
102impl crate::Writable for RTGC1_SPEC {
103    type Writer = W;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets RTGC1 to value 0"]
108impl crate::Resettable for RTGC1_SPEC {
109    const RESET_VALUE: Self::Ux = 0;
110}
cyt4en_a/m0/lpddr40/lpddr4_core/rtgc1.rs

cyt4en_a/m0/lpddr40/lpddr4_core/
rtgc1.rs
