cyt4en_a/m0/crypto/
ctl.rs1#[doc = "Register `CTL` reader"]
2pub struct R(crate::R<CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTL` writer"]
17pub struct W(crate::W<CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `P` reader - User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot\\[1\\]')."]
38pub type P_R = crate::BitReader<bool>;
39#[doc = "Field `P` writer - User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot\\[1\\]')."]
40pub type P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
41#[doc = "Field `NS` reader - Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot\\[4\\]')."]
42pub type NS_R = crate::BitReader<bool>;
43#[doc = "Field `NS` writer - Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot\\[4\\]')."]
44pub type NS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
45#[doc = "Field `PC` reader - Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'."]
46pub type PC_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `PC` writer - Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'."]
48pub type PC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTL_SPEC, u8, u8, 4, O>;
49#[doc = "Field `ECC_EN` reader - Enable ECC checking: '0': Disabled. '1': Enabled."]
50pub type ECC_EN_R = crate::BitReader<bool>;
51#[doc = "Field `ECC_EN` writer - Enable ECC checking: '0': Disabled. '1': Enabled."]
52pub type ECC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
53#[doc = "Field `ECC_INJ_EN` reader - Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM."]
54pub type ECC_INJ_EN_R = crate::BitReader<bool>;
55#[doc = "Field `ECC_INJ_EN` writer - Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM."]
56pub type ECC_INJ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
57#[doc = "Field `ENABLED` reader - IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'."]
58pub type ENABLED_R = crate::BitReader<ENABLED_A>;
59#[doc = "IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'.\n\nValue on reset: 0"]
60#[derive(Clone, Copy, Debug, PartialEq, Eq)]
61pub enum ENABLED_A {
62 #[doc = "0: N/A"]
63 DISABLED = 0,
64 #[doc = "1: N/A"]
65 ENABLED = 1,
66}
67impl From<ENABLED_A> for bool {
68 #[inline(always)]
69 fn from(variant: ENABLED_A) -> Self {
70 variant as u8 != 0
71 }
72}
73impl ENABLED_R {
74 #[doc = "Get enumerated values variant"]
75 #[inline(always)]
76 pub fn variant(&self) -> ENABLED_A {
77 match self.bits {
78 false => ENABLED_A::DISABLED,
79 true => ENABLED_A::ENABLED,
80 }
81 }
82 #[doc = "Checks if the value of the field is `DISABLED`"]
83 #[inline(always)]
84 pub fn is_disabled(&self) -> bool {
85 *self == ENABLED_A::DISABLED
86 }
87 #[doc = "Checks if the value of the field is `ENABLED`"]
88 #[inline(always)]
89 pub fn is_enabled(&self) -> bool {
90 *self == ENABLED_A::ENABLED
91 }
92}
93#[doc = "Field `ENABLED` writer - IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'."]
94pub type ENABLED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, ENABLED_A, O>;
95impl<'a, const O: u8> ENABLED_W<'a, O> {
96 #[doc = "N/A"]
97 #[inline(always)]
98 pub fn disabled(self) -> &'a mut W {
99 self.variant(ENABLED_A::DISABLED)
100 }
101 #[doc = "N/A"]
102 #[inline(always)]
103 pub fn enabled(self) -> &'a mut W {
104 self.variant(ENABLED_A::ENABLED)
105 }
106}
107impl R {
108 #[doc = "Bit 0 - User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot\\[1\\]')."]
109 #[inline(always)]
110 pub fn p(&self) -> P_R {
111 P_R::new((self.bits & 1) != 0)
112 }
113 #[doc = "Bit 1 - Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot\\[4\\]')."]
114 #[inline(always)]
115 pub fn ns(&self) -> NS_R {
116 NS_R::new(((self.bits >> 1) & 1) != 0)
117 }
118 #[doc = "Bits 4:7 - Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'."]
119 #[inline(always)]
120 pub fn pc(&self) -> PC_R {
121 PC_R::new(((self.bits >> 4) & 0x0f) as u8)
122 }
123 #[doc = "Bit 16 - Enable ECC checking: '0': Disabled. '1': Enabled."]
124 #[inline(always)]
125 pub fn ecc_en(&self) -> ECC_EN_R {
126 ECC_EN_R::new(((self.bits >> 16) & 1) != 0)
127 }
128 #[doc = "Bit 17 - Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM."]
129 #[inline(always)]
130 pub fn ecc_inj_en(&self) -> ECC_INJ_EN_R {
131 ECC_INJ_EN_R::new(((self.bits >> 17) & 1) != 0)
132 }
133 #[doc = "Bit 31 - IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'."]
134 #[inline(always)]
135 pub fn enabled(&self) -> ENABLED_R {
136 ENABLED_R::new(((self.bits >> 31) & 1) != 0)
137 }
138}
139impl W {
140 #[doc = "Bit 0 - User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the P field for the user/privileged access control ('hprot\\[1\\]')."]
141 #[inline(always)]
142 #[must_use]
143 pub fn p(&mut self) -> P_W<0> {
144 P_W::new(self)
145 }
146 #[doc = "Bit 1 - Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the NS field for the secure/non-secure access control ('hprot\\[4\\]')."]
147 #[inline(always)]
148 #[must_use]
149 pub fn ns(&mut self) -> NS_W<1> {
150 NS_W::new(self)
151 }
152 #[doc = "Bits 4:7 - Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'."]
153 #[inline(always)]
154 #[must_use]
155 pub fn pc(&mut self) -> PC_W<4> {
156 PC_W::new(self)
157 }
158 #[doc = "Bit 16 - Enable ECC checking: '0': Disabled. '1': Enabled."]
159 #[inline(always)]
160 #[must_use]
161 pub fn ecc_en(&mut self) -> ECC_EN_W<16> {
162 ECC_EN_W::new(self)
163 }
164 #[doc = "Bit 17 - Enable parity injection for SRAM. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM."]
165 #[inline(always)]
166 #[must_use]
167 pub fn ecc_inj_en(&mut self) -> ECC_INJ_EN_W<17> {
168 ECC_INJ_EN_W::new(self)
169 }
170 #[doc = "Bit 31 - IP enable: '0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. When the IP is enabled, the IP register buffer is set to '0'."]
171 #[inline(always)]
172 #[must_use]
173 pub fn enabled(&mut self) -> ENABLED_W<31> {
174 ENABLED_W::new(self)
175 }
176 #[doc = "Writes raw bits to the register."]
177 #[inline(always)]
178 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
179 self.0.bits(bits);
180 self
181 }
182}
183#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
184pub struct CTL_SPEC;
185impl crate::RegisterSpec for CTL_SPEC {
186 type Ux = u32;
187}
188#[doc = "`read()` method returns [ctl::R](R) reader structure"]
189impl crate::Readable for CTL_SPEC {
190 type Reader = R;
191}
192#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
193impl crate::Writable for CTL_SPEC {
194 type Writer = W;
195 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
197}
198#[doc = "`reset()` method sets CTL to value 0x0001_0002"]
199impl crate::Resettable for CTL_SPEC {
200 const RESET_VALUE: Self::Ux = 0x0001_0002;
201}