Crate cyt4dn_c

source ·

Modules

  • axi_dmac
    AXI DMAC
  • backup
    SRSS Backup Domain (ver3p3)
  • canfd0
    CAN Controller
  • canfd1
    CAN Controller
  • cpuss
    CPU subsystem (CPUSS)
  • crypto
    Cryptography component
  • cxpi0
    CXPI
  • dac0
    DAC
  • dmac
    DMAC
  • dw0
    Datawire Controller
  • dw1
    Datawire Controller
  • efuse
    EFUSE MXS40 registers
  • efuse_data
    eFUSE memory
  • eth0
    Ethernet Interface
  • evtgen0
    Event generator
  • fault
    Fault structures
  • flashc
    Flash controller
  • generic
    Common register and bit access and modify traits
  • gpio
    GPIO port control/configuration
  • hsiom
    High Speed IO Matrix (HSIOM)
  • ipc
    IPC
  • jpegdec
    JPEGDEC
  • lin0
    LIN
  • mixer0
    MIXER
  • mixer1
    MIXER
  • pass0
    Programmable Analog Subsystem for S40E
  • pd
    Power Domain and Switch Block
  • peri
    Peripheral interconnect
  • peri_ms
    Peripheral interconnect, master interface
  • peri_pclk
    Peripheral PCLK groups
  • prot
    Protection
  • pwm0
    PWM
  • scb0
    Serial Communications Block (SPI/UART/I2C)
  • scb1
    Serial Communications Block (SPI/UART/I2C)
  • scb2
    Serial Communications Block (SPI/UART/I2C)
  • scb3
    Serial Communications Block (SPI/UART/I2C)
  • scb4
    Serial Communications Block (SPI/UART/I2C)
  • scb5
    Serial Communications Block (SPI/UART/I2C)
  • scb6
    Serial Communications Block (SPI/UART/I2C)
  • scb7
    Serial Communications Block (SPI/UART/I2C)
  • scb8
    Serial Communications Block (SPI/UART/I2C)
  • scb9
    Serial Communications Block (SPI/UART/I2C)
  • scb10
    Serial Communications Block (SPI/UART/I2C)
  • scb11
    Serial Communications Block (SPI/UART/I2C)
  • sg0
    SG
  • smartio
    Programmable IO configuration
  • smif0
    SMIF subsystem (bridge + 2 core SMIFs, OR no bridge and 1 core SMIF)
  • srss
    SRSS Core Registers (ver3p3)
  • tcpwm0
    Timer/Counter/PWM
  • tdm0
    TDM
  • videoss0
    Video and Graphics Subsystem IP

Structs

  • AXI_DMAC
    AXI DMAC
  • BACKUP
    SRSS Backup Domain (ver3p3)
  • CANFD0
    CAN Controller
  • CANFD1
    CAN Controller
  • CBP
    Cache and branch predictor maintenance operations
  • CPUID
    CPUID
  • CPUSS
    CPU subsystem (CPUSS)
  • CRYPTO
    Cryptography component
  • CXPI0
    CXPI
  • CorePeripherals
    Core peripherals
  • DAC0
    DAC
  • DCB
    Debug Control Block
  • DMAC
    DMAC
  • DW0
    Datawire Controller
  • DW1
    Datawire Controller
  • DWT
    Data Watchpoint and Trace unit
  • EFUSE
    EFUSE MXS40 registers
  • EFUSE_DATA
    eFUSE memory
  • ETH0
    Ethernet Interface
  • EVTGEN0
    Event generator
  • FAULT
    Fault structures
  • FLASHC
    Flash controller
  • FPB
    Flash Patch and Breakpoint unit
  • GPIO
    GPIO port control/configuration
  • HSIOM
    High Speed IO Matrix (HSIOM)
  • IPC
    IPC
  • ITM
    Instrumentation Trace Macrocell
  • JPEGDEC
    JPEGDEC
  • LIN0
    LIN
  • MIXER0
    MIXER
  • MIXER1
    MIXER
  • MPU
    Memory Protection Unit
  • NVIC
    Nested Vector Interrupt Controller
  • PASS0
    Programmable Analog Subsystem for S40E
  • PD
    Power Domain and Switch Block
  • PERI
    Peripheral interconnect
  • PERI_MS
    Peripheral interconnect, master interface
  • PERI_PCLK
    Peripheral PCLK groups
  • PROT
    Protection
  • PWM0
    PWM
  • Peripherals
    All the peripherals.
  • SCB
    System Control Block
  • SCB0
    Serial Communications Block (SPI/UART/I2C)
  • SCB1
    Serial Communications Block (SPI/UART/I2C)
  • SCB2
    Serial Communications Block (SPI/UART/I2C)
  • SCB3
    Serial Communications Block (SPI/UART/I2C)
  • SCB4
    Serial Communications Block (SPI/UART/I2C)
  • SCB5
    Serial Communications Block (SPI/UART/I2C)
  • SCB6
    Serial Communications Block (SPI/UART/I2C)
  • SCB7
    Serial Communications Block (SPI/UART/I2C)
  • SCB8
    Serial Communications Block (SPI/UART/I2C)
  • SCB9
    Serial Communications Block (SPI/UART/I2C)
  • SCB10
    Serial Communications Block (SPI/UART/I2C)
  • SCB11
    Serial Communications Block (SPI/UART/I2C)
  • SG0
    SG
  • SMARTIO
    Programmable IO configuration
  • SMIF0
    SMIF subsystem (bridge + 2 core SMIFs, OR no bridge and 1 core SMIF)
  • SRSS
    SRSS Core Registers (ver3p3)
  • SYST
    SysTick: System Timer
  • TCPWM0
    Timer/Counter/PWM
  • TDM0
    TDM
  • TPIU
    Trace Port Interface Unit
  • VIDEOSS0
    Video and Graphics Subsystem IP

Enums

Constants

Attribute Macros