1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Control"]
5 pub ctl: CTL,
6 _reserved1: [u8; 0x04],
7 #[doc = "0x08 - SRAM power control"]
8 pub ram_pwr_ctl: RAM_PWR_CTL,
9 #[doc = "0x0c - SRAM power delay control"]
10 pub ram_pwr_delay_ctl: RAM_PWR_DELAY_CTL,
11 #[doc = "0x10 - ECC control"]
12 pub ecc_ctl: ECC_CTL,
13 _reserved4: [u8; 0x0c],
14 #[doc = "0x20 - Error status 0"]
15 pub error_status0: ERROR_STATUS0,
16 #[doc = "0x24 - Error status 1"]
17 pub error_status1: ERROR_STATUS1,
18 _reserved6: [u8; 0xd8],
19 #[doc = "0x100 - Interrupt register"]
20 pub intr: INTR,
21 #[doc = "0x104 - Interrupt set register"]
22 pub intr_set: INTR_SET,
23 #[doc = "0x108 - Interrupt mask register"]
24 pub intr_mask: INTR_MASK,
25 #[doc = "0x10c - Interrupt masked register"]
26 pub intr_masked: INTR_MASKED,
27 _reserved10: [u8; 0xf0],
28 #[doc = "0x200 - Pseudo random LFSR control 0"]
29 pub pr_lfsr_ctl0: PR_LFSR_CTL0,
30 #[doc = "0x204 - Pseudo random LFSR control 1"]
31 pub pr_lfsr_ctl1: PR_LFSR_CTL1,
32 #[doc = "0x208 - Pseudo random LFSR control 2"]
33 pub pr_lfsr_ctl2: PR_LFSR_CTL2,
34 #[doc = "0x20c - Pseudo random maximum control"]
35 pub pr_max_ctl: PR_MAX_CTL,
36 #[doc = "0x210 - Pseudo random command"]
37 pub pr_cmd: PR_CMD,
38 _reserved15: [u8; 0x04],
39 #[doc = "0x218 - Pseudo random result"]
40 pub pr_result: PR_RESULT,
41 _reserved16: [u8; 0x64],
42 #[doc = "0x280 - True random control 0"]
43 pub tr_ctl0: TR_CTL0,
44 #[doc = "0x284 - True random control 1"]
45 pub tr_ctl1: TR_CTL1,
46 #[doc = "0x288 - True random control 2"]
47 pub tr_ctl2: TR_CTL2,
48 #[doc = "0x28c - True random status"]
49 pub tr_status: TR_STATUS,
50 #[doc = "0x290 - True random command"]
51 pub tr_cmd: TR_CMD,
52 _reserved21: [u8; 0x04],
53 #[doc = "0x298 - True random result"]
54 pub tr_result: TR_RESULT,
55 _reserved22: [u8; 0x04],
56 #[doc = "0x2a0 - True random GARO control"]
57 pub tr_garo_ctl: TR_GARO_CTL,
58 #[doc = "0x2a4 - True random FIRO control"]
59 pub tr_firo_ctl: TR_FIRO_CTL,
60 _reserved24: [u8; 0x18],
61 #[doc = "0x2c0 - True random monitor control"]
62 pub tr_mon_ctl: TR_MON_CTL,
63 _reserved25: [u8; 0x04],
64 #[doc = "0x2c8 - True random monitor command"]
65 pub tr_mon_cmd: TR_MON_CMD,
66 _reserved26: [u8; 0x04],
67 #[doc = "0x2d0 - True random monitor RC control"]
68 pub tr_mon_rc_ctl: TR_MON_RC_CTL,
69 _reserved27: [u8; 0x04],
70 #[doc = "0x2d8 - True random monitor RC status 0"]
71 pub tr_mon_rc_status0: TR_MON_RC_STATUS0,
72 #[doc = "0x2dc - True random monitor RC status 1"]
73 pub tr_mon_rc_status1: TR_MON_RC_STATUS1,
74 #[doc = "0x2e0 - True random monitor AP control"]
75 pub tr_mon_ap_ctl: TR_MON_AP_CTL,
76 _reserved30: [u8; 0x04],
77 #[doc = "0x2e8 - True random monitor AP status 0"]
78 pub tr_mon_ap_status0: TR_MON_AP_STATUS0,
79 #[doc = "0x2ec - True random monitor AP status 1"]
80 pub tr_mon_ap_status1: TR_MON_AP_STATUS1,
81 _reserved32: [u8; 0x0d14],
82 #[doc = "0x1004 - Status"]
83 pub status: STATUS,
84 _reserved33: [u8; 0x38],
85 #[doc = "0x1040 - Instruction FIFO control"]
86 pub instr_ff_ctl: INSTR_FF_CTL,
87 #[doc = "0x1044 - Instruction FIFO status"]
88 pub instr_ff_status: INSTR_FF_STATUS,
89 #[doc = "0x1048 - Instruction FIFO write"]
90 pub instr_ff_wr: INSTR_FF_WR,
91 _reserved36: [u8; 0x74],
92 #[doc = "0x10c0 - Load 0 FIFO status"]
93 pub load0_ff_status: LOAD0_FF_STATUS,
94 _reserved37: [u8; 0x0c],
95 #[doc = "0x10d0 - Load 1 FIFO status"]
96 pub load1_ff_status: LOAD1_FF_STATUS,
97 _reserved38: [u8; 0x1c],
98 #[doc = "0x10f0 - Store FIFO status"]
99 pub store_ff_status: STORE_FF_STATUS,
100 _reserved39: [u8; 0x0c],
101 #[doc = "0x1100 - AES control"]
102 pub aes_ctl: AES_CTL,
103 _reserved40: [u8; 0x7c],
104 #[doc = "0x1180 - Result"]
105 pub result: RESULT,
106 _reserved41: [u8; 0x027c],
107 #[doc = "0x1400 - CRC control"]
108 pub crc_ctl: CRC_CTL,
109 _reserved42: [u8; 0x0c],
110 #[doc = "0x1410 - CRC data control"]
111 pub crc_data_ctl: CRC_DATA_CTL,
112 _reserved43: [u8; 0x0c],
113 #[doc = "0x1420 - CRC polynomial control"]
114 pub crc_pol_ctl: CRC_POL_CTL,
115 _reserved44: [u8; 0x1c],
116 #[doc = "0x1440 - CRC remainder control"]
117 pub crc_rem_ctl: CRC_REM_CTL,
118 _reserved45: [u8; 0x04],
119 #[doc = "0x1448 - CRC remainder result"]
120 pub crc_rem_result: CRC_REM_RESULT,
121 _reserved46: [u8; 0x34],
122 #[doc = "0x1480 - Vector unit control 0"]
123 pub vu_ctl0: VU_CTL0,
124 #[doc = "0x1484 - Vector unit control 1"]
125 pub vu_ctl1: VU_CTL1,
126 #[doc = "0x1488 - Vector unit control 2"]
127 pub vu_ctl2: VU_CTL2,
128 _reserved49: [u8; 0x04],
129 #[doc = "0x1490 - Vector unit status"]
130 pub vu_status: VU_STATUS,
131 _reserved50: [u8; 0x2c],
132 #[doc = "0x14c0..0x1500 - Vector unit register-file"]
133 pub vu_rf_data: [VU_RF_DATA; 16],
134 _reserved51: [u8; 0x0b00],
135 #[doc = "0x2000 - Device key address 0 control"]
136 pub dev_key_addr0_ctl: DEV_KEY_ADDR0_CTL,
137 #[doc = "0x2004 - Device key address 0"]
138 pub dev_key_addr0: DEV_KEY_ADDR0,
139 _reserved53: [u8; 0x18],
140 #[doc = "0x2020 - Device key address 1 control"]
141 pub dev_key_addr1_ctl: DEV_KEY_ADDR1_CTL,
142 #[doc = "0x2024 - Device key address 1 control"]
143 pub dev_key_addr1: DEV_KEY_ADDR1,
144 _reserved55: [u8; 0x58],
145 #[doc = "0x2080 - Device key status"]
146 pub dev_key_status: DEV_KEY_STATUS,
147 _reserved56: [u8; 0x7c],
148 #[doc = "0x2100 - Device key control 0"]
149 pub dev_key_ctl0: DEV_KEY_CTL0,
150 _reserved57: [u8; 0x1c],
151 #[doc = "0x2120 - Device key control 1"]
152 pub dev_key_ctl1: DEV_KEY_CTL1,
153}
154#[doc = "CTL (rw) register accessor: an alias for `Reg<CTL_SPEC>`"]
155pub type CTL = crate::Reg<ctl::CTL_SPEC>;
156#[doc = "Control"]
157pub mod ctl;
158#[doc = "RAM_PWR_CTL (rw) register accessor: an alias for `Reg<RAM_PWR_CTL_SPEC>`"]
159pub type RAM_PWR_CTL = crate::Reg<ram_pwr_ctl::RAM_PWR_CTL_SPEC>;
160#[doc = "SRAM power control"]
161pub mod ram_pwr_ctl;
162#[doc = "RAM_PWR_DELAY_CTL (rw) register accessor: an alias for `Reg<RAM_PWR_DELAY_CTL_SPEC>`"]
163pub type RAM_PWR_DELAY_CTL = crate::Reg<ram_pwr_delay_ctl::RAM_PWR_DELAY_CTL_SPEC>;
164#[doc = "SRAM power delay control"]
165pub mod ram_pwr_delay_ctl;
166#[doc = "ECC_CTL (rw) register accessor: an alias for `Reg<ECC_CTL_SPEC>`"]
167pub type ECC_CTL = crate::Reg<ecc_ctl::ECC_CTL_SPEC>;
168#[doc = "ECC control"]
169pub mod ecc_ctl;
170#[doc = "ERROR_STATUS0 (r) register accessor: an alias for `Reg<ERROR_STATUS0_SPEC>`"]
171pub type ERROR_STATUS0 = crate::Reg<error_status0::ERROR_STATUS0_SPEC>;
172#[doc = "Error status 0"]
173pub mod error_status0;
174#[doc = "ERROR_STATUS1 (rw) register accessor: an alias for `Reg<ERROR_STATUS1_SPEC>`"]
175pub type ERROR_STATUS1 = crate::Reg<error_status1::ERROR_STATUS1_SPEC>;
176#[doc = "Error status 1"]
177pub mod error_status1;
178#[doc = "INTR (rw) register accessor: an alias for `Reg<INTR_SPEC>`"]
179pub type INTR = crate::Reg<intr::INTR_SPEC>;
180#[doc = "Interrupt register"]
181pub mod intr;
182#[doc = "INTR_SET (rw) register accessor: an alias for `Reg<INTR_SET_SPEC>`"]
183pub type INTR_SET = crate::Reg<intr_set::INTR_SET_SPEC>;
184#[doc = "Interrupt set register"]
185pub mod intr_set;
186#[doc = "INTR_MASK (rw) register accessor: an alias for `Reg<INTR_MASK_SPEC>`"]
187pub type INTR_MASK = crate::Reg<intr_mask::INTR_MASK_SPEC>;
188#[doc = "Interrupt mask register"]
189pub mod intr_mask;
190#[doc = "INTR_MASKED (r) register accessor: an alias for `Reg<INTR_MASKED_SPEC>`"]
191pub type INTR_MASKED = crate::Reg<intr_masked::INTR_MASKED_SPEC>;
192#[doc = "Interrupt masked register"]
193pub mod intr_masked;
194#[doc = "PR_LFSR_CTL0 (rw) register accessor: an alias for `Reg<PR_LFSR_CTL0_SPEC>`"]
195pub type PR_LFSR_CTL0 = crate::Reg<pr_lfsr_ctl0::PR_LFSR_CTL0_SPEC>;
196#[doc = "Pseudo random LFSR control 0"]
197pub mod pr_lfsr_ctl0;
198#[doc = "PR_LFSR_CTL1 (rw) register accessor: an alias for `Reg<PR_LFSR_CTL1_SPEC>`"]
199pub type PR_LFSR_CTL1 = crate::Reg<pr_lfsr_ctl1::PR_LFSR_CTL1_SPEC>;
200#[doc = "Pseudo random LFSR control 1"]
201pub mod pr_lfsr_ctl1;
202#[doc = "PR_LFSR_CTL2 (rw) register accessor: an alias for `Reg<PR_LFSR_CTL2_SPEC>`"]
203pub type PR_LFSR_CTL2 = crate::Reg<pr_lfsr_ctl2::PR_LFSR_CTL2_SPEC>;
204#[doc = "Pseudo random LFSR control 2"]
205pub mod pr_lfsr_ctl2;
206#[doc = "PR_MAX_CTL (rw) register accessor: an alias for `Reg<PR_MAX_CTL_SPEC>`"]
207pub type PR_MAX_CTL = crate::Reg<pr_max_ctl::PR_MAX_CTL_SPEC>;
208#[doc = "Pseudo random maximum control"]
209pub mod pr_max_ctl;
210#[doc = "PR_CMD (rw) register accessor: an alias for `Reg<PR_CMD_SPEC>`"]
211pub type PR_CMD = crate::Reg<pr_cmd::PR_CMD_SPEC>;
212#[doc = "Pseudo random command"]
213pub mod pr_cmd;
214#[doc = "PR_RESULT (rw) register accessor: an alias for `Reg<PR_RESULT_SPEC>`"]
215pub type PR_RESULT = crate::Reg<pr_result::PR_RESULT_SPEC>;
216#[doc = "Pseudo random result"]
217pub mod pr_result;
218#[doc = "TR_CTL0 (rw) register accessor: an alias for `Reg<TR_CTL0_SPEC>`"]
219pub type TR_CTL0 = crate::Reg<tr_ctl0::TR_CTL0_SPEC>;
220#[doc = "True random control 0"]
221pub mod tr_ctl0;
222#[doc = "TR_CTL1 (rw) register accessor: an alias for `Reg<TR_CTL1_SPEC>`"]
223pub type TR_CTL1 = crate::Reg<tr_ctl1::TR_CTL1_SPEC>;
224#[doc = "True random control 1"]
225pub mod tr_ctl1;
226#[doc = "TR_CTL2 (rw) register accessor: an alias for `Reg<TR_CTL2_SPEC>`"]
227pub type TR_CTL2 = crate::Reg<tr_ctl2::TR_CTL2_SPEC>;
228#[doc = "True random control 2"]
229pub mod tr_ctl2;
230#[doc = "TR_STATUS (r) register accessor: an alias for `Reg<TR_STATUS_SPEC>`"]
231pub type TR_STATUS = crate::Reg<tr_status::TR_STATUS_SPEC>;
232#[doc = "True random status"]
233pub mod tr_status;
234#[doc = "TR_CMD (rw) register accessor: an alias for `Reg<TR_CMD_SPEC>`"]
235pub type TR_CMD = crate::Reg<tr_cmd::TR_CMD_SPEC>;
236#[doc = "True random command"]
237pub mod tr_cmd;
238#[doc = "TR_RESULT (rw) register accessor: an alias for `Reg<TR_RESULT_SPEC>`"]
239pub type TR_RESULT = crate::Reg<tr_result::TR_RESULT_SPEC>;
240#[doc = "True random result"]
241pub mod tr_result;
242#[doc = "TR_GARO_CTL (rw) register accessor: an alias for `Reg<TR_GARO_CTL_SPEC>`"]
243pub type TR_GARO_CTL = crate::Reg<tr_garo_ctl::TR_GARO_CTL_SPEC>;
244#[doc = "True random GARO control"]
245pub mod tr_garo_ctl;
246#[doc = "TR_FIRO_CTL (rw) register accessor: an alias for `Reg<TR_FIRO_CTL_SPEC>`"]
247pub type TR_FIRO_CTL = crate::Reg<tr_firo_ctl::TR_FIRO_CTL_SPEC>;
248#[doc = "True random FIRO control"]
249pub mod tr_firo_ctl;
250#[doc = "TR_MON_CTL (rw) register accessor: an alias for `Reg<TR_MON_CTL_SPEC>`"]
251pub type TR_MON_CTL = crate::Reg<tr_mon_ctl::TR_MON_CTL_SPEC>;
252#[doc = "True random monitor control"]
253pub mod tr_mon_ctl;
254#[doc = "TR_MON_CMD (rw) register accessor: an alias for `Reg<TR_MON_CMD_SPEC>`"]
255pub type TR_MON_CMD = crate::Reg<tr_mon_cmd::TR_MON_CMD_SPEC>;
256#[doc = "True random monitor command"]
257pub mod tr_mon_cmd;
258#[doc = "TR_MON_RC_CTL (rw) register accessor: an alias for `Reg<TR_MON_RC_CTL_SPEC>`"]
259pub type TR_MON_RC_CTL = crate::Reg<tr_mon_rc_ctl::TR_MON_RC_CTL_SPEC>;
260#[doc = "True random monitor RC control"]
261pub mod tr_mon_rc_ctl;
262#[doc = "TR_MON_RC_STATUS0 (r) register accessor: an alias for `Reg<TR_MON_RC_STATUS0_SPEC>`"]
263pub type TR_MON_RC_STATUS0 = crate::Reg<tr_mon_rc_status0::TR_MON_RC_STATUS0_SPEC>;
264#[doc = "True random monitor RC status 0"]
265pub mod tr_mon_rc_status0;
266#[doc = "TR_MON_RC_STATUS1 (r) register accessor: an alias for `Reg<TR_MON_RC_STATUS1_SPEC>`"]
267pub type TR_MON_RC_STATUS1 = crate::Reg<tr_mon_rc_status1::TR_MON_RC_STATUS1_SPEC>;
268#[doc = "True random monitor RC status 1"]
269pub mod tr_mon_rc_status1;
270#[doc = "TR_MON_AP_CTL (rw) register accessor: an alias for `Reg<TR_MON_AP_CTL_SPEC>`"]
271pub type TR_MON_AP_CTL = crate::Reg<tr_mon_ap_ctl::TR_MON_AP_CTL_SPEC>;
272#[doc = "True random monitor AP control"]
273pub mod tr_mon_ap_ctl;
274#[doc = "TR_MON_AP_STATUS0 (r) register accessor: an alias for `Reg<TR_MON_AP_STATUS0_SPEC>`"]
275pub type TR_MON_AP_STATUS0 = crate::Reg<tr_mon_ap_status0::TR_MON_AP_STATUS0_SPEC>;
276#[doc = "True random monitor AP status 0"]
277pub mod tr_mon_ap_status0;
278#[doc = "TR_MON_AP_STATUS1 (r) register accessor: an alias for `Reg<TR_MON_AP_STATUS1_SPEC>`"]
279pub type TR_MON_AP_STATUS1 = crate::Reg<tr_mon_ap_status1::TR_MON_AP_STATUS1_SPEC>;
280#[doc = "True random monitor AP status 1"]
281pub mod tr_mon_ap_status1;
282#[doc = "STATUS (r) register accessor: an alias for `Reg<STATUS_SPEC>`"]
283pub type STATUS = crate::Reg<status::STATUS_SPEC>;
284#[doc = "Status"]
285pub mod status;
286#[doc = "INSTR_FF_CTL (rw) register accessor: an alias for `Reg<INSTR_FF_CTL_SPEC>`"]
287pub type INSTR_FF_CTL = crate::Reg<instr_ff_ctl::INSTR_FF_CTL_SPEC>;
288#[doc = "Instruction FIFO control"]
289pub mod instr_ff_ctl;
290#[doc = "INSTR_FF_STATUS (r) register accessor: an alias for `Reg<INSTR_FF_STATUS_SPEC>`"]
291pub type INSTR_FF_STATUS = crate::Reg<instr_ff_status::INSTR_FF_STATUS_SPEC>;
292#[doc = "Instruction FIFO status"]
293pub mod instr_ff_status;
294#[doc = "INSTR_FF_WR (w) register accessor: an alias for `Reg<INSTR_FF_WR_SPEC>`"]
295pub type INSTR_FF_WR = crate::Reg<instr_ff_wr::INSTR_FF_WR_SPEC>;
296#[doc = "Instruction FIFO write"]
297pub mod instr_ff_wr;
298#[doc = "LOAD0_FF_STATUS (r) register accessor: an alias for `Reg<LOAD0_FF_STATUS_SPEC>`"]
299pub type LOAD0_FF_STATUS = crate::Reg<load0_ff_status::LOAD0_FF_STATUS_SPEC>;
300#[doc = "Load 0 FIFO status"]
301pub mod load0_ff_status;
302#[doc = "LOAD1_FF_STATUS (r) register accessor: an alias for `Reg<LOAD1_FF_STATUS_SPEC>`"]
303pub type LOAD1_FF_STATUS = crate::Reg<load1_ff_status::LOAD1_FF_STATUS_SPEC>;
304#[doc = "Load 1 FIFO status"]
305pub mod load1_ff_status;
306#[doc = "STORE_FF_STATUS (r) register accessor: an alias for `Reg<STORE_FF_STATUS_SPEC>`"]
307pub type STORE_FF_STATUS = crate::Reg<store_ff_status::STORE_FF_STATUS_SPEC>;
308#[doc = "Store FIFO status"]
309pub mod store_ff_status;
310#[doc = "AES_CTL (rw) register accessor: an alias for `Reg<AES_CTL_SPEC>`"]
311pub type AES_CTL = crate::Reg<aes_ctl::AES_CTL_SPEC>;
312#[doc = "AES control"]
313pub mod aes_ctl;
314#[doc = "RESULT (rw) register accessor: an alias for `Reg<RESULT_SPEC>`"]
315pub type RESULT = crate::Reg<result::RESULT_SPEC>;
316#[doc = "Result"]
317pub mod result;
318#[doc = "CRC_CTL (rw) register accessor: an alias for `Reg<CRC_CTL_SPEC>`"]
319pub type CRC_CTL = crate::Reg<crc_ctl::CRC_CTL_SPEC>;
320#[doc = "CRC control"]
321pub mod crc_ctl;
322#[doc = "CRC_DATA_CTL (rw) register accessor: an alias for `Reg<CRC_DATA_CTL_SPEC>`"]
323pub type CRC_DATA_CTL = crate::Reg<crc_data_ctl::CRC_DATA_CTL_SPEC>;
324#[doc = "CRC data control"]
325pub mod crc_data_ctl;
326#[doc = "CRC_POL_CTL (rw) register accessor: an alias for `Reg<CRC_POL_CTL_SPEC>`"]
327pub type CRC_POL_CTL = crate::Reg<crc_pol_ctl::CRC_POL_CTL_SPEC>;
328#[doc = "CRC polynomial control"]
329pub mod crc_pol_ctl;
330#[doc = "CRC_REM_CTL (rw) register accessor: an alias for `Reg<CRC_REM_CTL_SPEC>`"]
331pub type CRC_REM_CTL = crate::Reg<crc_rem_ctl::CRC_REM_CTL_SPEC>;
332#[doc = "CRC remainder control"]
333pub mod crc_rem_ctl;
334#[doc = "CRC_REM_RESULT (r) register accessor: an alias for `Reg<CRC_REM_RESULT_SPEC>`"]
335pub type CRC_REM_RESULT = crate::Reg<crc_rem_result::CRC_REM_RESULT_SPEC>;
336#[doc = "CRC remainder result"]
337pub mod crc_rem_result;
338#[doc = "VU_CTL0 (rw) register accessor: an alias for `Reg<VU_CTL0_SPEC>`"]
339pub type VU_CTL0 = crate::Reg<vu_ctl0::VU_CTL0_SPEC>;
340#[doc = "Vector unit control 0"]
341pub mod vu_ctl0;
342#[doc = "VU_CTL1 (rw) register accessor: an alias for `Reg<VU_CTL1_SPEC>`"]
343pub type VU_CTL1 = crate::Reg<vu_ctl1::VU_CTL1_SPEC>;
344#[doc = "Vector unit control 1"]
345pub mod vu_ctl1;
346#[doc = "VU_CTL2 (rw) register accessor: an alias for `Reg<VU_CTL2_SPEC>`"]
347pub type VU_CTL2 = crate::Reg<vu_ctl2::VU_CTL2_SPEC>;
348#[doc = "Vector unit control 2"]
349pub mod vu_ctl2;
350#[doc = "VU_STATUS (r) register accessor: an alias for `Reg<VU_STATUS_SPEC>`"]
351pub type VU_STATUS = crate::Reg<vu_status::VU_STATUS_SPEC>;
352#[doc = "Vector unit status"]
353pub mod vu_status;
354#[doc = "VU_RF_DATA (r) register accessor: an alias for `Reg<VU_RF_DATA_SPEC>`"]
355pub type VU_RF_DATA = crate::Reg<vu_rf_data::VU_RF_DATA_SPEC>;
356#[doc = "Vector unit register-file"]
357pub mod vu_rf_data;
358#[doc = "DEV_KEY_ADDR0_CTL (rw) register accessor: an alias for `Reg<DEV_KEY_ADDR0_CTL_SPEC>`"]
359pub type DEV_KEY_ADDR0_CTL = crate::Reg<dev_key_addr0_ctl::DEV_KEY_ADDR0_CTL_SPEC>;
360#[doc = "Device key address 0 control"]
361pub mod dev_key_addr0_ctl;
362#[doc = "DEV_KEY_ADDR0 (rw) register accessor: an alias for `Reg<DEV_KEY_ADDR0_SPEC>`"]
363pub type DEV_KEY_ADDR0 = crate::Reg<dev_key_addr0::DEV_KEY_ADDR0_SPEC>;
364#[doc = "Device key address 0"]
365pub mod dev_key_addr0;
366#[doc = "DEV_KEY_ADDR1_CTL (rw) register accessor: an alias for `Reg<DEV_KEY_ADDR1_CTL_SPEC>`"]
367pub type DEV_KEY_ADDR1_CTL = crate::Reg<dev_key_addr1_ctl::DEV_KEY_ADDR1_CTL_SPEC>;
368#[doc = "Device key address 1 control"]
369pub mod dev_key_addr1_ctl;
370#[doc = "DEV_KEY_ADDR1 (rw) register accessor: an alias for `Reg<DEV_KEY_ADDR1_SPEC>`"]
371pub type DEV_KEY_ADDR1 = crate::Reg<dev_key_addr1::DEV_KEY_ADDR1_SPEC>;
372#[doc = "Device key address 1 control"]
373pub mod dev_key_addr1;
374#[doc = "DEV_KEY_STATUS (r) register accessor: an alias for `Reg<DEV_KEY_STATUS_SPEC>`"]
375pub type DEV_KEY_STATUS = crate::Reg<dev_key_status::DEV_KEY_STATUS_SPEC>;
376#[doc = "Device key status"]
377pub mod dev_key_status;
378#[doc = "DEV_KEY_CTL0 (rw) register accessor: an alias for `Reg<DEV_KEY_CTL0_SPEC>`"]
379pub type DEV_KEY_CTL0 = crate::Reg<dev_key_ctl0::DEV_KEY_CTL0_SPEC>;
380#[doc = "Device key control 0"]
381pub mod dev_key_ctl0;
382#[doc = "DEV_KEY_CTL1 (rw) register accessor: an alias for `Reg<DEV_KEY_CTL1_SPEC>`"]
383pub type DEV_KEY_CTL1 = crate::Reg<dev_key_ctl1::DEV_KEY_CTL1_SPEC>;
384#[doc = "Device key control 1"]
385pub mod dev_key_ctl1;