cyt4bb_b/m0/eth0/
int_q1_enable.rs

1#[doc = "Register `INT_Q1_ENABLE` writer"]
2pub struct W(crate::W<INT_Q1_ENABLE_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<INT_Q1_ENABLE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<INT_Q1_ENABLE_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<INT_Q1_ENABLE_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ENABLE_RECEIVE_COMPLETE_INTERRUPT` writer - Enable Receive complete interrupt"]
23pub type ENABLE_RECEIVE_COMPLETE_INTERRUPT_W<'a, const O: u8> =
24    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
25#[doc = "Field `ENABLE_RX_USED_BIT_READ_INTERRUPT` writer - Enable RX used bit read interrupt"]
26pub type ENABLE_RX_USED_BIT_READ_INTERRUPT_W<'a, const O: u8> =
27    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
28#[doc = "Field `ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT` writer - Enable Retry limit exceeded or late collision interrupt"]
29pub type ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_W<'a, const O: u8> =
30    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
31#[doc = "Field `ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT` writer - Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt"]
32pub type ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_W<'a, const O: u8> =
33    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
34#[doc = "Field `ENABLE_TRANSMIT_COMPLETE_INTERRUPT` writer - Enable Transmit complete interrupt"]
35pub type ENABLE_TRANSMIT_COMPLETE_INTERRUPT_W<'a, const O: u8> =
36    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
37#[doc = "Field `ENABLE_RESP_NOT_OK_INTERRUPT` writer - Enable bresp not OK interrupt"]
38pub type ENABLE_RESP_NOT_OK_INTERRUPT_W<'a, const O: u8> =
39    crate::BitWriter<'a, u32, INT_Q1_ENABLE_SPEC, bool, O>;
40impl W {
41    #[doc = "Bit 1 - Enable Receive complete interrupt"]
42    #[inline(always)]
43    #[must_use]
44    pub fn enable_receive_complete_interrupt(&mut self) -> ENABLE_RECEIVE_COMPLETE_INTERRUPT_W<1> {
45        ENABLE_RECEIVE_COMPLETE_INTERRUPT_W::new(self)
46    }
47    #[doc = "Bit 2 - Enable RX used bit read interrupt"]
48    #[inline(always)]
49    #[must_use]
50    pub fn enable_rx_used_bit_read_interrupt(&mut self) -> ENABLE_RX_USED_BIT_READ_INTERRUPT_W<2> {
51        ENABLE_RX_USED_BIT_READ_INTERRUPT_W::new(self)
52    }
53    #[doc = "Bit 5 - Enable Retry limit exceeded or late collision interrupt"]
54    #[inline(always)]
55    #[must_use]
56    pub fn enable_retry_limit_exceeded_or_late_collision_interrupt(
57        &mut self,
58    ) -> ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_W<5> {
59        ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_W::new(self)
60    }
61    #[doc = "Bit 6 - Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt"]
62    #[inline(always)]
63    #[must_use]
64    pub fn enable_transmit_frame_corruption_due_to_amba_error_interrupt(
65        &mut self,
66    ) -> ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_W<6> {
67        ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT_W::new(self)
68    }
69    #[doc = "Bit 7 - Enable Transmit complete interrupt"]
70    #[inline(always)]
71    #[must_use]
72    pub fn enable_transmit_complete_interrupt(
73        &mut self,
74    ) -> ENABLE_TRANSMIT_COMPLETE_INTERRUPT_W<7> {
75        ENABLE_TRANSMIT_COMPLETE_INTERRUPT_W::new(self)
76    }
77    #[doc = "Bit 11 - Enable bresp not OK interrupt"]
78    #[inline(always)]
79    #[must_use]
80    pub fn enable_resp_not_ok_interrupt(&mut self) -> ENABLE_RESP_NOT_OK_INTERRUPT_W<11> {
81        ENABLE_RESP_NOT_OK_INTERRUPT_W::new(self)
82    }
83    #[doc = "Writes raw bits to the register."]
84    #[inline(always)]
85    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
86        self.0.bits(bits);
87        self
88    }
89}
90#[doc = "At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_q1_enable](index.html) module"]
91pub struct INT_Q1_ENABLE_SPEC;
92impl crate::RegisterSpec for INT_Q1_ENABLE_SPEC {
93    type Ux = u32;
94}
95#[doc = "`write(|w| ..)` method takes [int_q1_enable::W](W) writer structure"]
96impl crate::Writable for INT_Q1_ENABLE_SPEC {
97    type Writer = W;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100}
101#[doc = "`reset()` method sets INT_Q1_ENABLE to value 0"]
102impl crate::Resettable for INT_Q1_ENABLE_SPEC {
103    const RESET_VALUE: Self::Ux = 0;
104}
cyt4bb_b/m0/eth0/int_q1_enable.rs

cyt4bb_b/m0/eth0/
int_q1_enable.rs
