cyt3bb_b/m0/scb0/
spi_status.rs

1#[doc = "Register `SPI_STATUS` reader"]
2pub struct R(crate::R<SPI_STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPI_STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPI_STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPI_STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `BUS_BUSY` reader - SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted."]
17pub type BUS_BUSY_R = crate::BitReader<bool>;
18#[doc = "Field `SPI_EC_BUSY` reader - Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable."]
19pub type SPI_EC_BUSY_R = crate::BitReader<bool>;
20#[doc = "Field `CURR_EZ_ADDR` reader - SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design."]
21pub type CURR_EZ_ADDR_R = crate::FieldReader<u8, u8>;
22#[doc = "Field `BASE_EZ_ADDR` reader - SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design."]
23pub type BASE_EZ_ADDR_R = crate::FieldReader<u8, u8>;
24impl R {
25    #[doc = "Bit 0 - SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted."]
26    #[inline(always)]
27    pub fn bus_busy(&self) -> BUS_BUSY_R {
28        BUS_BUSY_R::new((self.bits & 1) != 0)
29    }
30    #[doc = "Bit 1 - Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable."]
31    #[inline(always)]
32    pub fn spi_ec_busy(&self) -> SPI_EC_BUSY_R {
33        SPI_EC_BUSY_R::new(((self.bits >> 1) & 1) != 0)
34    }
35    #[doc = "Bits 8:15 - SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design."]
36    #[inline(always)]
37    pub fn curr_ez_addr(&self) -> CURR_EZ_ADDR_R {
38        CURR_EZ_ADDR_R::new(((self.bits >> 8) & 0xff) as u8)
39    }
40    #[doc = "Bits 16:23 - SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design."]
41    #[inline(always)]
42    pub fn base_ez_addr(&self) -> BASE_EZ_ADDR_R {
43        BASE_EZ_ADDR_R::new(((self.bits >> 16) & 0xff) as u8)
44    }
45}
46#[doc = "SPI status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_status](index.html) module"]
47pub struct SPI_STATUS_SPEC;
48impl crate::RegisterSpec for SPI_STATUS_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [spi_status::R](R) reader structure"]
52impl crate::Readable for SPI_STATUS_SPEC {
53    type Reader = R;
54}
55#[doc = "`reset()` method sets SPI_STATUS to value 0"]
56impl crate::Resettable for SPI_STATUS_SPEC {
57    const RESET_VALUE: Self::Ux = 0;
58}
cyt3bb_b/m0/scb0/spi_status.rs

cyt3bb_b/m0/scb0/
spi_status.rs
