cyt3bb_b/m0/eth0/
designcfg_debug2.rs

1#[doc = "Register `DESIGNCFG_DEBUG2` reader"]
2pub struct R(crate::R<DESIGNCFG_DEBUG2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DESIGNCFG_DEBUG2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DESIGNCFG_DEBUG2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DESIGNCFG_DEBUG2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `JUMBO_MAX_LENGTH` reader - Takes the value of the `gem_jumbo_max_length DEFINE"]
17pub type JUMBO_MAX_LENGTH_R = crate::FieldReader<u16, u16>;
18#[doc = "Field `HPROT_VALUE` reader - Takes the value of the `gem_hprot_value DEFINE"]
19pub type HPROT_VALUE_R = crate::FieldReader<u8, u8>;
20#[doc = "Field `RX_PKT_BUFFER` reader - Takes the value of the `gem_rx_pkt_buffer DEFINE"]
21pub type RX_PKT_BUFFER_R = crate::BitReader<bool>;
22#[doc = "Field `TX_PKT_BUFFER` reader - Takes the value of the `gem_tx_pkt_buffer DEFINE"]
23pub type TX_PKT_BUFFER_R = crate::BitReader<bool>;
24#[doc = "Field `RX_PBUF_ADDR` reader - Takes the value of the `gem_rx_pbuf_addr DEFINE"]
25pub type RX_PBUF_ADDR_R = crate::FieldReader<u8, u8>;
26#[doc = "Field `TX_PBUF_ADDR` reader - Takes the value of the `gem_tx_pbuf_addr DEFINE"]
27pub type TX_PBUF_ADDR_R = crate::FieldReader<u8, u8>;
28#[doc = "Field `AXI` reader - Takes the value of the `gem_axi DEFINE"]
29pub type AXI_R = crate::BitReader<bool>;
30#[doc = "Field `SPRAM` reader - Takes the value of the `gem_spram DEFINE"]
31pub type SPRAM_R = crate::BitReader<bool>;
32impl R {
33    #[doc = "Bits 0:13 - Takes the value of the `gem_jumbo_max_length DEFINE"]
34    #[inline(always)]
35    pub fn jumbo_max_length(&self) -> JUMBO_MAX_LENGTH_R {
36        JUMBO_MAX_LENGTH_R::new((self.bits & 0x3fff) as u16)
37    }
38    #[doc = "Bits 16:19 - Takes the value of the `gem_hprot_value DEFINE"]
39    #[inline(always)]
40    pub fn hprot_value(&self) -> HPROT_VALUE_R {
41        HPROT_VALUE_R::new(((self.bits >> 16) & 0x0f) as u8)
42    }
43    #[doc = "Bit 20 - Takes the value of the `gem_rx_pkt_buffer DEFINE"]
44    #[inline(always)]
45    pub fn rx_pkt_buffer(&self) -> RX_PKT_BUFFER_R {
46        RX_PKT_BUFFER_R::new(((self.bits >> 20) & 1) != 0)
47    }
48    #[doc = "Bit 21 - Takes the value of the `gem_tx_pkt_buffer DEFINE"]
49    #[inline(always)]
50    pub fn tx_pkt_buffer(&self) -> TX_PKT_BUFFER_R {
51        TX_PKT_BUFFER_R::new(((self.bits >> 21) & 1) != 0)
52    }
53    #[doc = "Bits 22:25 - Takes the value of the `gem_rx_pbuf_addr DEFINE"]
54    #[inline(always)]
55    pub fn rx_pbuf_addr(&self) -> RX_PBUF_ADDR_R {
56        RX_PBUF_ADDR_R::new(((self.bits >> 22) & 0x0f) as u8)
57    }
58    #[doc = "Bits 26:29 - Takes the value of the `gem_tx_pbuf_addr DEFINE"]
59    #[inline(always)]
60    pub fn tx_pbuf_addr(&self) -> TX_PBUF_ADDR_R {
61        TX_PBUF_ADDR_R::new(((self.bits >> 26) & 0x0f) as u8)
62    }
63    #[doc = "Bit 30 - Takes the value of the `gem_axi DEFINE"]
64    #[inline(always)]
65    pub fn axi(&self) -> AXI_R {
66        AXI_R::new(((self.bits >> 30) & 1) != 0)
67    }
68    #[doc = "Bit 31 - Takes the value of the `gem_spram DEFINE"]
69    #[inline(always)]
70    pub fn spram(&self) -> SPRAM_R {
71        SPRAM_R::new(((self.bits >> 31) & 1) != 0)
72    }
73}
74#[doc = "Design Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [designcfg_debug2](index.html) module"]
75pub struct DESIGNCFG_DEBUG2_SPEC;
76impl crate::RegisterSpec for DESIGNCFG_DEBUG2_SPEC {
77    type Ux = u32;
78}
79#[doc = "`read()` method returns [designcfg_debug2::R](R) reader structure"]
80impl crate::Readable for DESIGNCFG_DEBUG2_SPEC {
81    type Reader = R;
82}
83#[doc = "`reset()` method sets DESIGNCFG_DEBUG2 to value 0xa631_0600"]
84impl crate::Resettable for DESIGNCFG_DEBUG2_SPEC {
85    const RESET_VALUE: Self::Ux = 0xa631_0600;
86}
cyt3bb_b/m0/eth0/designcfg_debug2.rs

cyt3bb_b/m0/eth0/
designcfg_debug2.rs
