1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - MXETH Control Register"]
5 pub ctl: CTL,
6 #[doc = "0x04 - MXETH Status Register"]
7 pub status: STATUS,
8 _reserved2: [u8; 0x0ff8],
9 #[doc = "0x1000 - The network control register contains general MAC control functions for both receiver and transmitter."]
10 pub network_control: NETWORK_CONTROL,
11 #[doc = "0x1004 - The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC."]
12 pub network_config: NETWORK_CONFIG,
13 #[doc = "0x1008 - The network status register returns status information with respect to the PHY management interface."]
14 pub network_status: NETWORK_STATUS,
15 #[doc = "0x100c - Not presents. Access to the register will return AHB error."]
16 pub user_io_register: USER_IO_REGISTER,
17 #[doc = "0x1010 - DMA Configuration Register"]
18 pub dma_config: DMA_CONFIG,
19 #[doc = "0x1014 - This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."]
20 pub transmit_status: TRANSMIT_STATUS,
21 #[doc = "0x1018 - This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AXI) operation, the receive descriptors are read from memory using a single 32bit AXI access. When the datapath is configured at 64bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AXI access."]
22 pub receive_q_ptr: RECEIVE_Q_PTR,
23 #[doc = "0x101c - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
24 pub transmit_q_ptr: TRANSMIT_Q_PTR,
25 #[doc = "0x1020 - This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."]
26 pub receive_status: RECEIVE_STATUS,
27 #[doc = "0x1024 - If not configured for priority queueing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no affect on the status of the bit."]
28 pub int_status: INT_STATUS,
29 #[doc = "0x1028 - At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
30 pub int_enable: INT_ENABLE,
31 #[doc = "0x102c - Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
32 pub int_disable: INT_DISABLE,
33 #[doc = "0x1030 - The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
34 pub int_mask: INT_MASK,
35 #[doc = "0x1034 - The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register."]
36 pub phy_management: PHY_MANAGEMENT,
37 #[doc = "0x1038 - Received Pause Quantum Register"]
38 pub pause_time: PAUSE_TIME,
39 #[doc = "0x103c - Transmit Pause Quantum Register"]
40 pub tx_pause_quantum: TX_PAUSE_QUANTUM,
41 #[doc = "0x1040 - Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward"]
42 pub pbuf_txcutthru: PBUF_TXCUTTHRU,
43 #[doc = "0x1044 - RX Partial Store and Forward"]
44 pub pbuf_rxcutthru: PBUF_RXCUTTHRU,
45 #[doc = "0x1048 - Maximum Jumbo Frame Size."]
46 pub jumbo_max_length: JUMBO_MAX_LENGTH,
47 #[doc = "0x104c - Not presents."]
48 pub external_fifo_interface: EXTERNAL_FIFO_INTERFACE,
49 _reserved22: [u8; 0x04],
50 #[doc = "0x1054 - Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)"]
51 pub axi_max_pipeline: AXI_MAX_PIPELINE,
52 #[doc = "0x1058 - Not presents. Access to the register will return AHB error."]
53 pub rsc_control: RSC_CONTROL,
54 #[doc = "0x105c - Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation."]
55 pub int_moderation: INT_MODERATION,
56 #[doc = "0x1060 - Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time."]
57 pub sys_wake_time: SYS_WAKE_TIME,
58 _reserved26: [u8; 0x1c],
59 #[doc = "0x1080 - The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits)"]
60 pub hash_bottom: HASH_BOTTOM,
61 #[doc = "0x1084 - Hash Register Top (63 to 32 bits)"]
62 pub hash_top: HASH_TOP,
63 #[doc = "0x1088 - The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
64 pub spec_add1_bottom: SPEC_ADD1_BOTTOM,
65 #[doc = "0x108c - Specific Address Top"]
66 pub spec_add1_top: SPEC_ADD1_TOP,
67 #[doc = "0x1090 - The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
68 pub spec_add2_bottom: SPEC_ADD2_BOTTOM,
69 #[doc = "0x1094 - Specific Address Top"]
70 pub spec_add2_top: SPEC_ADD2_TOP,
71 #[doc = "0x1098 - The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
72 pub spec_add3_bottom: SPEC_ADD3_BOTTOM,
73 #[doc = "0x109c - Specific Address Top"]
74 pub spec_add3_top: SPEC_ADD3_TOP,
75 #[doc = "0x10a0 - The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
76 pub spec_add4_bottom: SPEC_ADD4_BOTTOM,
77 #[doc = "0x10a4 - Specific Address Top"]
78 pub spec_add4_top: SPEC_ADD4_TOP,
79 #[doc = "0x10a8 - Type ID Match 1"]
80 pub spec_type1: SPEC_TYPE1,
81 #[doc = "0x10ac - Type ID Match 2"]
82 pub spec_type2: SPEC_TYPE2,
83 #[doc = "0x10b0 - Type ID Match 3"]
84 pub spec_type3: SPEC_TYPE3,
85 #[doc = "0x10b4 - Type ID Match 4"]
86 pub spec_type4: SPEC_TYPE4,
87 #[doc = "0x10b8 - Wake on LAN Register. Presents in design, but feature is not supported."]
88 pub wol_register: WOL_REGISTER,
89 #[doc = "0x10bc - IPG stretch register"]
90 pub stretch_ratio: STRETCH_RATIO,
91 #[doc = "0x10c0 - Stacked VLAN Register"]
92 pub stacked_vlan: STACKED_VLAN,
93 #[doc = "0x10c4 - Transmit PFC Pause Register"]
94 pub tx_pfc_pause: TX_PFC_PAUSE,
95 #[doc = "0x10c8 - Specific Address Mask 1 Bottom (31 to 0 bits)"]
96 pub mask_add1_bottom: MASK_ADD1_BOTTOM,
97 #[doc = "0x10cc - Specific Address Mask 1 Top (47 to 32 bits)"]
98 pub mask_add1_top: MASK_ADD1_TOP,
99 #[doc = "0x10d0 - Receive DMA Data Buffer Address Mask"]
100 pub dma_addr_or_mask: DMA_ADDR_OR_MASK,
101 #[doc = "0x10d4 - PTP RX unicast IP destination address"]
102 pub rx_ptp_unicast: RX_PTP_UNICAST,
103 #[doc = "0x10d8 - PTP TX unicast IP destination address"]
104 pub tx_ptp_unicast: TX_PTP_UNICAST,
105 #[doc = "0x10dc - TSU timer comparison value nanoseconds"]
106 pub tsu_nsec_cmp: TSU_NSEC_CMP,
107 #[doc = "0x10e0 - TSU timer comparison value seconds (31 to 0 bits)"]
108 pub tsu_sec_cmp: TSU_SEC_CMP,
109 #[doc = "0x10e4 - TSU timer comparison value seconds (47 to 32 bits)"]
110 pub tsu_msb_sec_cmp: TSU_MSB_SEC_CMP,
111 #[doc = "0x10e8 - PTP Event Frame Transmitted Seconds Register (47 to 32 bits)"]
112 pub tsu_ptp_tx_msb_sec: TSU_PTP_TX_MSB_SEC,
113 #[doc = "0x10ec - PTP Event Frame Received Seconds Register (47 to 32 bits)"]
114 pub tsu_ptp_rx_msb_sec: TSU_PTP_RX_MSB_SEC,
115 #[doc = "0x10f0 - PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)"]
116 pub tsu_peer_tx_msb_sec: TSU_PEER_TX_MSB_SEC,
117 #[doc = "0x10f4 - PTP Peer Event Frame Received Seconds Register (47 to 32 bits)"]
118 pub tsu_peer_rx_msb_sec: TSU_PEER_RX_MSB_SEC,
119 #[doc = "0x10f8 - The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction."]
120 pub dpram_fill_dbg: DPRAM_FILL_DBG,
121 #[doc = "0x10fc - This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value"]
122 pub revision_reg: REVISION_REG,
123 #[doc = "0x1100 - Octets Transmitted lower bits (31 to 0 bits)"]
124 pub octets_txed_bottom: OCTETS_TXED_BOTTOM,
125 #[doc = "0x1104 - Octets Transmitted higher bits (47 to 32 bits)"]
126 pub octets_txed_top: OCTETS_TXED_TOP,
127 #[doc = "0x1108 - Frames Transmitted"]
128 pub frames_txed_ok: FRAMES_TXED_OK,
129 #[doc = "0x110c - Broadcast Frames Transmitted"]
130 pub broadcast_txed: BROADCAST_TXED,
131 #[doc = "0x1110 - Multicast Frames Transmitted"]
132 pub multicast_txed: MULTICAST_TXED,
133 #[doc = "0x1114 - Pause Frames Transmitted"]
134 pub pause_frames_txed: PAUSE_FRAMES_TXED,
135 #[doc = "0x1118 - 64 Byte Frames Transmitted"]
136 pub frames_txed_64: FRAMES_TXED_64,
137 #[doc = "0x111c - 65 to 127 Byte Frames Transmitted"]
138 pub frames_txed_65: FRAMES_TXED_65,
139 #[doc = "0x1120 - 128 to 255 Byte Frames Transmitted"]
140 pub frames_txed_128: FRAMES_TXED_128,
141 #[doc = "0x1124 - 256 to 511 Byte Frames Transmitted"]
142 pub frames_txed_256: FRAMES_TXED_256,
143 #[doc = "0x1128 - 512 to 1023 Byte Frames Transmitted"]
144 pub frames_txed_512: FRAMES_TXED_512,
145 #[doc = "0x112c - 1024 to 1518 Byte Frames Transmitted"]
146 pub frames_txed_1024: FRAMES_TXED_1024,
147 #[doc = "0x1130 - Greater Than 1518 Byte Frames Transmitted"]
148 pub frames_txed_1519: FRAMES_TXED_1519,
149 #[doc = "0x1134 - Transmit Under Runs"]
150 pub tx_underruns: TX_UNDERRUNS,
151 #[doc = "0x1138 - Single Collision Frames. Presents in design but not support."]
152 pub single_collisions: SINGLE_COLLISIONS,
153 #[doc = "0x113c - Multiple Collision Frames. Presents in design but not support."]
154 pub multiple_collisions: MULTIPLE_COLLISIONS,
155 #[doc = "0x1140 - Excessive Collisions. Presents in design but not support."]
156 pub excessive_collisions: EXCESSIVE_COLLISIONS,
157 #[doc = "0x1144 - Late Collisions. Presents in design but not support."]
158 pub late_collisions: LATE_COLLISIONS,
159 #[doc = "0x1148 - Deferred Transmission Frames. Presents in design but not support."]
160 pub deferred_frames: DEFERRED_FRAMES,
161 #[doc = "0x114c - Carrier Sense Errors. Presents in design but not support."]
162 pub crs_errors: CRS_ERRORS,
163 #[doc = "0x1150 - Octets Received (31 to 0 bits)"]
164 pub octets_rxed_bottom: OCTETS_RXED_BOTTOM,
165 #[doc = "0x1154 - Octets Received (47 to 32 bits)"]
166 pub octets_rxed_top: OCTETS_RXED_TOP,
167 #[doc = "0x1158 - Frames Received"]
168 pub frames_rxed_ok: FRAMES_RXED_OK,
169 #[doc = "0x115c - Broadcast Frames Received"]
170 pub broadcast_rxed: BROADCAST_RXED,
171 #[doc = "0x1160 - Multicast Frames Received"]
172 pub multicast_rxed: MULTICAST_RXED,
173 #[doc = "0x1164 - Pause Frames Received"]
174 pub pause_frames_rxed: PAUSE_FRAMES_RXED,
175 #[doc = "0x1168 - 64 Byte Frames Received"]
176 pub frames_rxed_64: FRAMES_RXED_64,
177 #[doc = "0x116c - 65 to 127 Byte Frames Received"]
178 pub frames_rxed_65: FRAMES_RXED_65,
179 #[doc = "0x1170 - 128 to 255 Byte Frames Received"]
180 pub frames_rxed_128: FRAMES_RXED_128,
181 #[doc = "0x1174 - 256 to 511 Byte Frames Received"]
182 pub frames_rxed_256: FRAMES_RXED_256,
183 #[doc = "0x1178 - 512 to 1023 Byte Frames Received"]
184 pub frames_rxed_512: FRAMES_RXED_512,
185 #[doc = "0x117c - 1024 to 1518 Byte Frames Received"]
186 pub frames_rxed_1024: FRAMES_RXED_1024,
187 #[doc = "0x1180 - 1519 to maximum Byte Frames Received"]
188 pub frames_rxed_1519: FRAMES_RXED_1519,
189 #[doc = "0x1184 - Undersized Frames Received"]
190 pub undersize_frames: UNDERSIZE_FRAMES,
191 #[doc = "0x1188 - Oversize Frames Received"]
192 pub excessive_rx_length: EXCESSIVE_RX_LENGTH,
193 #[doc = "0x118c - Jabbers Received"]
194 pub rx_jabbers: RX_JABBERS,
195 #[doc = "0x1190 - Frame Check Sequence Errors"]
196 pub fcs_errors: FCS_ERRORS,
197 #[doc = "0x1194 - Length Field Frame Errors"]
198 pub rx_length_errors: RX_LENGTH_ERRORS,
199 #[doc = "0x1198 - Receive Symbol Errors"]
200 pub rx_symbol_errors: RX_SYMBOL_ERRORS,
201 #[doc = "0x119c - Alignment Errors"]
202 pub alignment_errors: ALIGNMENT_ERRORS,
203 #[doc = "0x11a0 - Receive Resource Errors"]
204 pub rx_resource_errors: RX_RESOURCE_ERRORS,
205 #[doc = "0x11a4 - Receive Overruns"]
206 pub rx_overruns: RX_OVERRUNS,
207 #[doc = "0x11a8 - IP Header Checksum Errors"]
208 pub rx_ip_ck_errors: RX_IP_CK_ERRORS,
209 #[doc = "0x11ac - TCP Checksum Errors"]
210 pub rx_tcp_ck_errors: RX_TCP_CK_ERRORS,
211 #[doc = "0x11b0 - UDP Checksum Errors"]
212 pub rx_udp_ck_errors: RX_UDP_CK_ERRORS,
213 #[doc = "0x11b4 - Receive DMA Flushed Packets"]
214 pub auto_flushed_pkts: AUTO_FLUSHED_PKTS,
215 _reserved104: [u8; 0x04],
216 #[doc = "0x11bc - 1588 Timer Increment Register sub nsec"]
217 pub tsu_timer_incr_sub_nsec: TSU_TIMER_INCR_SUB_NSEC,
218 #[doc = "0x11c0 - 1588 Timer Seconds Register (47 to 32 bits)"]
219 pub tsu_timer_msb_sec: TSU_TIMER_MSB_SEC,
220 #[doc = "0x11c4 - 1588 Timer Sync Strobe Seconds Register (47 to 32 bits)"]
221 pub tsu_strobe_msb_sec: TSU_STROBE_MSB_SEC,
222 #[doc = "0x11c8 - 1588 Timer Sync Strobe Seconds Register (31 to 0 bits)"]
223 pub tsu_strobe_sec: TSU_STROBE_SEC,
224 #[doc = "0x11cc - 1588 Timer Sync Strobe Nanoseconds Register"]
225 pub tsu_strobe_nsec: TSU_STROBE_NSEC,
226 #[doc = "0x11d0 - 1588 Timer Seconds Register (31 to 0 bits)"]
227 pub tsu_timer_sec: TSU_TIMER_SEC,
228 #[doc = "0x11d4 - 1588 Timer Nanoseconds Register"]
229 pub tsu_timer_nsec: TSU_TIMER_NSEC,
230 #[doc = "0x11d8 - This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read."]
231 pub tsu_timer_adjust: TSU_TIMER_ADJUST,
232 #[doc = "0x11dc - 1588 Timer Increment Register"]
233 pub tsu_timer_incr: TSU_TIMER_INCR,
234 #[doc = "0x11e0 - PTP Event Frame Transmitted Seconds Register (31 to 0 bits)"]
235 pub tsu_ptp_tx_sec: TSU_PTP_TX_SEC,
236 #[doc = "0x11e4 - PTP Event Frame Transmitted Nanoseconds Register"]
237 pub tsu_ptp_tx_nsec: TSU_PTP_TX_NSEC,
238 #[doc = "0x11e8 - PTP Event Frame Received Seconds Register (31 to 0 bits)"]
239 pub tsu_ptp_rx_sec: TSU_PTP_RX_SEC,
240 #[doc = "0x11ec - PTP Event Frame Received Nanoseconds Register"]
241 pub tsu_ptp_rx_nsec: TSU_PTP_RX_NSEC,
242 #[doc = "0x11f0 - PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)"]
243 pub tsu_peer_tx_sec: TSU_PEER_TX_SEC,
244 #[doc = "0x11f4 - PTP Peer Event Frame Transmitted Nanoseconds Register"]
245 pub tsu_peer_tx_nsec: TSU_PEER_TX_NSEC,
246 #[doc = "0x11f8 - PTP Peer Event Frame Received Seconds Register (31 to 0 bits)"]
247 pub tsu_peer_rx_sec: TSU_PEER_RX_SEC,
248 #[doc = "0x11fc - PTP Peer Event Frame Received Nanoseconds Register"]
249 pub tsu_peer_rx_nsec: TSU_PEER_RX_NSEC,
250 #[doc = "0x1200 - Not presents. Access to the register returns AHB error."]
251 pub pcs_control: PCS_CONTROL,
252 #[doc = "0x1204 - Not presents. Access to the register returns AHB error."]
253 pub pcs_status: PCS_STATUS,
254 _reserved123: [u8; 0x08],
255 #[doc = "0x1210 - Not presents. Access to the register returns AHB error."]
256 pub pcs_an_adv: PCS_AN_ADV,
257 #[doc = "0x1214 - Not presents. Access to the register returns AHB error."]
258 pub pcs_an_lp_base: PCS_AN_LP_BASE,
259 #[doc = "0x1218 - Not presents. Access to the register returns AHB error."]
260 pub pcs_an_exp: PCS_AN_EXP,
261 #[doc = "0x121c - Not presents. Access to the register returns AHB error."]
262 pub pcs_an_np_tx: PCS_AN_NP_TX,
263 #[doc = "0x1220 - Not presents. Access to the register returns AHB error."]
264 pub pcs_an_lp_np: PCS_AN_LP_NP,
265 _reserved128: [u8; 0x18],
266 #[doc = "0x123c - Not presents. Access to the register returns AHB error."]
267 pub pcs_an_ext_status: PCS_AN_EXT_STATUS,
268 _reserved129: [u8; 0x20],
269 #[doc = "0x1260 - Transmit Pause Quantum Register 1"]
270 pub tx_pause_quantum1: TX_PAUSE_QUANTUM1,
271 #[doc = "0x1264 - Transmit Pause Quantum Register 2"]
272 pub tx_pause_quantum2: TX_PAUSE_QUANTUM2,
273 #[doc = "0x1268 - Transmit Pause Quantum Register 3"]
274 pub tx_pause_quantum3: TX_PAUSE_QUANTUM3,
275 _reserved132: [u8; 0x04],
276 #[doc = "0x1270 - Received LPI transitions"]
277 pub rx_lpi: RX_LPI,
278 #[doc = "0x1274 - Received LPI time"]
279 pub rx_lpi_time: RX_LPI_TIME,
280 #[doc = "0x1278 - Transmit LPI transitions"]
281 pub tx_lpi: TX_LPI,
282 #[doc = "0x127c - Transmit LPI time"]
283 pub tx_lpi_time: TX_LPI_TIME,
284 #[doc = "0x1280 - The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v."]
285 pub designcfg_debug1: DESIGNCFG_DEBUG1,
286 #[doc = "0x1284 - Design Configuration Register 2"]
287 pub designcfg_debug2: DESIGNCFG_DEBUG2,
288 #[doc = "0x1288 - Design Configuration Register 3"]
289 pub designcfg_debug3: DESIGNCFG_DEBUG3,
290 #[doc = "0x128c - Design Configuration Register 4"]
291 pub designcfg_debug4: DESIGNCFG_DEBUG4,
292 #[doc = "0x1290 - Design Configuration Register 5"]
293 pub designcfg_debug5: DESIGNCFG_DEBUG5,
294 #[doc = "0x1294 - Design Configuration Register 6"]
295 pub designcfg_debug6: DESIGNCFG_DEBUG6,
296 #[doc = "0x1298 - Design Configuration Register 7"]
297 pub designcfg_debug7: DESIGNCFG_DEBUG7,
298 #[doc = "0x129c - Design Configuration Register 8"]
299 pub designcfg_debug8: DESIGNCFG_DEBUG8,
300 #[doc = "0x12a0 - Design Configuration Register 9"]
301 pub designcfg_debug9: DESIGNCFG_DEBUG9,
302 #[doc = "0x12a4 - Design Configuration Register 10"]
303 pub designcfg_debug10: DESIGNCFG_DEBUG10,
304 _reserved146: [u8; 0x58],
305 #[doc = "0x1300 - Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."]
306 pub spec_add5_bottom: SPEC_ADD5_BOTTOM,
307 #[doc = "0x1304 - Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."]
308 pub spec_add5_top: SPEC_ADD5_TOP,
309 _reserved148: [u8; 0xf0],
310 #[doc = "0x13f8 - Not presents."]
311 pub spec_add36_bottom: SPEC_ADD36_BOTTOM,
312 #[doc = "0x13fc - Not presents."]
313 pub spec_add36_top: SPEC_ADD36_TOP,
314 #[doc = "0x1400 - Priority queue Interrupt Status Register"]
315 pub int_q1_status: INT_Q1_STATUS,
316 #[doc = "0x1404 - Priority queue Interrupt Status Register"]
317 pub int_q2_status: INT_Q2_STATUS,
318 #[doc = "0x1408 - int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error."]
319 pub int_q3_status: INT_Q3_STATUS,
320 _reserved153: [u8; 0x2c],
321 #[doc = "0x1438 - Not presents."]
322 pub int_q15_status: INT_Q15_STATUS,
323 _reserved154: [u8; 0x04],
324 #[doc = "0x1440 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
325 pub transmit_q1_ptr: TRANSMIT_Q1_PTR,
326 #[doc = "0x1444 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
327 pub transmit_q2_ptr: TRANSMIT_Q2_PTR,
328 #[doc = "0x1448 - transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error."]
329 pub transmit_q3_ptr: TRANSMIT_Q3_PTR,
330 _reserved157: [u8; 0x2c],
331 #[doc = "0x1478 - Not presents."]
332 pub transmit_q15_ptr: TRANSMIT_Q15_PTR,
333 _reserved158: [u8; 0x04],
334 #[doc = "0x1480 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
335 pub receive_q1_ptr: RECEIVE_Q1_PTR,
336 #[doc = "0x1484 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
337 pub receive_q2_ptr: RECEIVE_Q2_PTR,
338 #[doc = "0x1488 - Not presents. Start address register doesn't present for queue3 ~ queue7."]
339 pub receive_q3_ptr: RECEIVE_Q3_PTR,
340 _reserved161: [u8; 0x0c],
341 #[doc = "0x1498 - Not presents."]
342 pub receive_q7_ptr: RECEIVE_Q7_PTR,
343 _reserved162: [u8; 0x04],
344 #[doc = "0x14a0 - Receive Buffer queue 1 Size"]
345 pub dma_rxbuf_size_q1: DMA_RXBUF_SIZE_Q1,
346 #[doc = "0x14a4 - Receive Buffer queue 2 Size"]
347 pub dma_rxbuf_size_q2: DMA_RXBUF_SIZE_Q2,
348 #[doc = "0x14a8 - dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present."]
349 pub dma_rxbuf_size_q3: DMA_RXBUF_SIZE_Q3,
350 _reserved165: [u8; 0x0c],
351 #[doc = "0x14b8 - Not presents."]
352 pub dma_rxbuf_size_q7: DMA_RXBUF_SIZE_Q7,
353 #[doc = "0x14bc - The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note that Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved."]
354 pub cbs_control: CBS_CONTROL,
355 #[doc = "0x14c0 - queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration."]
356 pub cbs_idleslope_q_a: CBS_IDLESLOPE_Q_A,
357 #[doc = "0x14c4 - queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration."]
358 pub cbs_idleslope_q_b: CBS_IDLESLOPE_Q_B,
359 #[doc = "0x14c8 - Upper 32 bits of transmit buffer descriptor queue base address."]
360 pub upper_tx_q_base_addr: UPPER_TX_Q_BASE_ADDR,
361 #[doc = "0x14cc - TX BD control register"]
362 pub tx_bd_control: TX_BD_CONTROL,
363 #[doc = "0x14d0 - RX BD control register"]
364 pub rx_bd_control: RX_BD_CONTROL,
365 #[doc = "0x14d4 - Upper 32 bits of receive buffer descriptor queue base address."]
366 pub upper_rx_q_base_addr: UPPER_RX_Q_BASE_ADDR,
367 _reserved173: [u8; 0x08],
368 #[doc = "0x14e0 - Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register."]
369 pub hidden_reg0: HIDDEN_REG0,
370 #[doc = "0x14e4 - Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***'"]
371 pub hidden_reg1: HIDDEN_REG1,
372 #[doc = "0x14e8 - Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***'"]
373 pub hidden_reg2: HIDDEN_REG2,
374 #[doc = "0x14ec - Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'."]
375 pub hidden_reg3: HIDDEN_REG3,
376 _reserved177: [u8; 0x08],
377 #[doc = "0x14f8 - Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width ( gem_dma_bus_width == 32 or bits 22 to 21 of the network_config register are set to 0) the AXI hidden registers (0x14F8 and 0x14FC) need to be updated (these registers are used for fine tuning AXI dma bursts and normally should not be touched)."]
378 pub hidden_reg4: HIDDEN_REG4,
379 #[doc = "0x14fc - Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'."]
380 pub hidden_reg5: HIDDEN_REG5,
381 #[doc = "0x1500 - Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11 to 4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27 to 12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 2 to 0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C."]
382 pub screening_type_1_register_0: SCREENING_TYPE_1_REGISTER_0,
383 #[doc = "0x1504 - screening type 1 register 1, same as screening_type_1_register_0"]
384 pub screening_type_1_register_1: SCREENING_TYPE_1_REGISTER_1,
385 #[doc = "0x1508 - screening type 1 register 2, same as screening_type_1_register_0"]
386 pub screening_type_1_register_2: SCREENING_TYPE_1_REGISTER_2,
387 #[doc = "0x150c - screening type 1 register 3, same as screening_type_1_register_0"]
388 pub screening_type_1_register_3: SCREENING_TYPE_1_REGISTER_3,
389 #[doc = "0x1510 - screening type 1 register 4, same as screening_type_1_register_0"]
390 pub screening_type_1_register_4: SCREENING_TYPE_1_REGISTER_4,
391 #[doc = "0x1514 - screening type 1 register 5, same as screening_type_1_register_0"]
392 pub screening_type_1_register_5: SCREENING_TYPE_1_REGISTER_5,
393 #[doc = "0x1518 - screening type 1 register 6, same as screening_type_1_register_0"]
394 pub screening_type_1_register_6: SCREENING_TYPE_1_REGISTER_6,
395 #[doc = "0x151c - screening type 1 register 7, same as screening_type_1_register_0"]
396 pub screening_type_1_register_7: SCREENING_TYPE_1_REGISTER_7,
397 #[doc = "0x1520 - screening type 1 register 8, same as screening_type_1_register_0"]
398 pub screening_type_1_register_8: SCREENING_TYPE_1_REGISTER_8,
399 #[doc = "0x1524 - screening type 1 register 9, same as screening_type_1_register_0"]
400 pub screening_type_1_register_9: SCREENING_TYPE_1_REGISTER_9,
401 #[doc = "0x1528 - screening type 1 register 10, same as screening_type_1_register_0"]
402 pub screening_type_1_register_10: SCREENING_TYPE_1_REGISTER_10,
403 #[doc = "0x152c - screening type 1 register 11, same as screening_type_1_register_0"]
404 pub screening_type_1_register_11: SCREENING_TYPE_1_REGISTER_11,
405 #[doc = "0x1530 - screening type 1 register 12, same as screening_type_1_register_0"]
406 pub screening_type_1_register_12: SCREENING_TYPE_1_REGISTER_12,
407 #[doc = "0x1534 - screening type 1 register 13, same as screening_type_1_register_0"]
408 pub screening_type_1_register_13: SCREENING_TYPE_1_REGISTER_13,
409 #[doc = "0x1538 - screening type 1 register 14, same as screening_type_1_register_0"]
410 pub screening_type_1_register_14: SCREENING_TYPE_1_REGISTER_14,
411 #[doc = "0x153c - screening type 1 register 15, same as screening_type_1_register_0"]
412 pub screening_type_1_register_15: SCREENING_TYPE_1_REGISTER_15,
413 #[doc = "0x1540 - Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities, extending the capabilities into vendor specific protocols."]
414 pub screening_type_2_register_0: SCREENING_TYPE_2_REGISTER_0,
415 #[doc = "0x1544 - screening type 2 register 1, same as screening_type_2_register_0"]
416 pub screening_type_2_register_1: SCREENING_TYPE_2_REGISTER_1,
417 #[doc = "0x1548 - screening type 2 register 2, same as screening_type_2_register_0"]
418 pub screening_type_2_register_2: SCREENING_TYPE_2_REGISTER_2,
419 #[doc = "0x154c - screening type 2 register 3, same as screening_type_2_register_0"]
420 pub screening_type_2_register_3: SCREENING_TYPE_2_REGISTER_3,
421 #[doc = "0x1550 - screening type 2 register 4, same as screening_type_2_register_0"]
422 pub screening_type_2_register_4: SCREENING_TYPE_2_REGISTER_4,
423 #[doc = "0x1554 - screening type 2 register 5, same as screening_type_2_register_0"]
424 pub screening_type_2_register_5: SCREENING_TYPE_2_REGISTER_5,
425 #[doc = "0x1558 - screening type 2 register 6, same as screening_type_2_register_0"]
426 pub screening_type_2_register_6: SCREENING_TYPE_2_REGISTER_6,
427 #[doc = "0x155c - screening type 2 register 7, same as screening_type_2_register_0"]
428 pub screening_type_2_register_7: SCREENING_TYPE_2_REGISTER_7,
429 #[doc = "0x1560 - screening type 2 register 8, same as screening_type_2_register_0"]
430 pub screening_type_2_register_8: SCREENING_TYPE_2_REGISTER_8,
431 #[doc = "0x1564 - screening type 2 register 9, same as screening_type_2_register_0"]
432 pub screening_type_2_register_9: SCREENING_TYPE_2_REGISTER_9,
433 #[doc = "0x1568 - screening type 2 register 10, same as screening_type_2_register_0"]
434 pub screening_type_2_register_10: SCREENING_TYPE_2_REGISTER_10,
435 #[doc = "0x156c - screening type 2 register 11, same as screening_type_2_register_0"]
436 pub screening_type_2_register_11: SCREENING_TYPE_2_REGISTER_11,
437 #[doc = "0x1570 - screening type 2 register 12, same as screening_type_2_register_0"]
438 pub screening_type_2_register_12: SCREENING_TYPE_2_REGISTER_12,
439 #[doc = "0x1574 - screening type 2 register 13, same as screening_type_2_register_0"]
440 pub screening_type_2_register_13: SCREENING_TYPE_2_REGISTER_13,
441 #[doc = "0x1578 - screening type 2 register 14, same as screening_type_2_register_0"]
442 pub screening_type_2_register_14: SCREENING_TYPE_2_REGISTER_14,
443 #[doc = "0x157c - screening type 2 register 15, same as screening_type_2_register_0"]
444 pub screening_type_2_register_15: SCREENING_TYPE_2_REGISTER_15,
445 #[doc = "0x1580 - This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority"]
446 pub tx_sched_ctrl: TX_SCHED_CTRL,
447 _reserved212: [u8; 0x0c],
448 #[doc = "0x1590 - This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3."]
449 pub bw_rate_limit_q0to3: BW_RATE_LIMIT_Q0TO3,
450 #[doc = "0x1594 - Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
451 pub bw_rate_limit_q4to7: BW_RATE_LIMIT_Q4TO7,
452 #[doc = "0x1598 - Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
453 pub bw_rate_limit_q8to11: BW_RATE_LIMIT_Q8TO11,
454 #[doc = "0x159c - Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
455 pub bw_rate_limit_q12to15: BW_RATE_LIMIT_Q12TO15,
456 #[doc = "0x15a0 - This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file."]
457 pub tx_q_seg_alloc_q0to7: TX_Q_SEG_ALLOC_Q0TO7,
458 #[doc = "0x15a4 - Not presents. Access to the register returns AHB error."]
459 pub tx_q_seg_alloc_q8to15: TX_Q_SEG_ALLOC_Q8TO15,
460 _reserved218: [u8; 0x18],
461 #[doc = "0x15c0 - receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error."]
462 pub receive_q8_ptr: RECEIVE_Q8_PTR,
463 _reserved219: [u8; 0x18],
464 #[doc = "0x15dc - Not presents."]
465 pub receive_q15_ptr: RECEIVE_Q15_PTR,
466 #[doc = "0x15e0 - dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error."]
467 pub dma_rxbuf_size_q8: DMA_RXBUF_SIZE_Q8,
468 _reserved221: [u8; 0x18],
469 #[doc = "0x15fc - Not presents."]
470 pub dma_rxbuf_size_q15: DMA_RXBUF_SIZE_Q15,
471 #[doc = "0x1600 - At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
472 pub int_q1_enable: INT_Q1_ENABLE,
473 #[doc = "0x1604 - At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
474 pub int_q2_enable: INT_Q2_ENABLE,
475 #[doc = "0x1608 - int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error."]
476 pub int_q3_enable: INT_Q3_ENABLE,
477 _reserved225: [u8; 0x0c],
478 #[doc = "0x1618 - Not presents."]
479 pub int_q7_enable: INT_Q7_ENABLE,
480 _reserved226: [u8; 0x04],
481 #[doc = "0x1620 - Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
482 pub int_q1_disable: INT_Q1_DISABLE,
483 #[doc = "0x1624 - Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
484 pub int_q2_disable: INT_Q2_DISABLE,
485 #[doc = "0x1628 - int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error."]
486 pub int_q3_disable: INT_Q3_DISABLE,
487 _reserved229: [u8; 0x0c],
488 #[doc = "0x1638 - Not presents."]
489 pub int_q7_disable: INT_Q7_DISABLE,
490 _reserved230: [u8; 0x04],
491 #[doc = "0x1640 - The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
492 pub int_q1_mask: INT_Q1_MASK,
493 #[doc = "0x1644 - The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
494 pub int_q2_mask: INT_Q2_MASK,
495 #[doc = "0x1648 - int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error."]
496 pub int_q3_mask: INT_Q3_MASK,
497 _reserved233: [u8; 0x0c],
498 #[doc = "0x1658 - Not presents."]
499 pub int_q7_mask: INT_Q7_MASK,
500 _reserved234: [u8; 0x04],
501 #[doc = "0x1660 - int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error."]
502 pub int_q8_enable: INT_Q8_ENABLE,
503 _reserved235: [u8; 0x18],
504 #[doc = "0x167c - Not presents."]
505 pub int_q15_enable: INT_Q15_ENABLE,
506 #[doc = "0x1680 - int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error."]
507 pub int_q8_disable: INT_Q8_DISABLE,
508 _reserved237: [u8; 0x18],
509 #[doc = "0x169c - Not presents."]
510 pub int_q15_disable: INT_Q15_DISABLE,
511 #[doc = "0x16a0 - int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error."]
512 pub int_q8_mask: INT_Q8_MASK,
513 _reserved239: [u8; 0x18],
514 #[doc = "0x16bc - Not presents."]
515 pub int_q15_mask: INT_Q15_MASK,
516 _reserved240: [u8; 0x20],
517 #[doc = "0x16e0 - Ethertype Register"]
518 pub screening_type_2_ethertype_reg_0: SCREENING_TYPE_2_ETHERTYPE_REG_0,
519 #[doc = "0x16e4 - Ethertype Register"]
520 pub screening_type_2_ethertype_reg_1: SCREENING_TYPE_2_ETHERTYPE_REG_1,
521 #[doc = "0x16e8 - Ethertype Register"]
522 pub screening_type_2_ethertype_reg_2: SCREENING_TYPE_2_ETHERTYPE_REG_2,
523 #[doc = "0x16ec - Ethertype Register"]
524 pub screening_type_2_ethertype_reg_3: SCREENING_TYPE_2_ETHERTYPE_REG_3,
525 #[doc = "0x16f0 - Ethertype Register"]
526 pub screening_type_2_ethertype_reg_4: SCREENING_TYPE_2_ETHERTYPE_REG_4,
527 #[doc = "0x16f4 - Ethertype Register"]
528 pub screening_type_2_ethertype_reg_5: SCREENING_TYPE_2_ETHERTYPE_REG_5,
529 #[doc = "0x16f8 - Ethertype Register"]
530 pub screening_type_2_ethertype_reg_6: SCREENING_TYPE_2_ETHERTYPE_REG_6,
531 #[doc = "0x16fc - Ethertype Register"]
532 pub screening_type_2_ethertype_reg_7: SCREENING_TYPE_2_ETHERTYPE_REG_7,
533 #[doc = "0x1700 - 'Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7 to 0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15 to 8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. '"]
534 pub type2_compare_0_word_0: TYPE2_COMPARE_0_WORD_0,
535 #[doc = "0x1704 - 'Type2 Compare Word 1'"]
536 pub type2_compare_0_word_1: TYPE2_COMPARE_0_WORD_1,
537 #[doc = "0x1708 - same as type2_compare_0_word_0"]
538 pub type2_compare_1_word_0: TYPE2_COMPARE_1_WORD_0,
539 #[doc = "0x170c - same as type2_compare_0_word_1"]
540 pub type2_compare_1_word_1: TYPE2_COMPARE_1_WORD_1,
541 #[doc = "0x1710 - same as type2_compare_0_word_0"]
542 pub type2_compare_2_word_0: TYPE2_COMPARE_2_WORD_0,
543 #[doc = "0x1714 - same as type2_compare_0_word_1"]
544 pub type2_compare_2_word_1: TYPE2_COMPARE_2_WORD_1,
545 #[doc = "0x1718 - same as type2_compare_0_word_0"]
546 pub type2_compare_3_word_0: TYPE2_COMPARE_3_WORD_0,
547 #[doc = "0x171c - same as type2_compare_0_word_1"]
548 pub type2_compare_3_word_1: TYPE2_COMPARE_3_WORD_1,
549 #[doc = "0x1720 - same as type2_compare_0_word_0"]
550 pub type2_compare_4_word_0: TYPE2_COMPARE_4_WORD_0,
551 #[doc = "0x1724 - same as type2_compare_0_word_1"]
552 pub type2_compare_4_word_1: TYPE2_COMPARE_4_WORD_1,
553 #[doc = "0x1728 - same as type2_compare_0_word_0"]
554 pub type2_compare_5_word_0: TYPE2_COMPARE_5_WORD_0,
555 #[doc = "0x172c - same as type2_compare_0_word_1"]
556 pub type2_compare_5_word_1: TYPE2_COMPARE_5_WORD_1,
557 #[doc = "0x1730 - same as type2_compare_0_word_0"]
558 pub type2_compare_6_word_0: TYPE2_COMPARE_6_WORD_0,
559 #[doc = "0x1734 - same as type2_compare_0_word_1"]
560 pub type2_compare_6_word_1: TYPE2_COMPARE_6_WORD_1,
561 #[doc = "0x1738 - same as type2_compare_0_word_0"]
562 pub type2_compare_7_word_0: TYPE2_COMPARE_7_WORD_0,
563 #[doc = "0x173c - same as type2_compare_0_word_1"]
564 pub type2_compare_7_word_1: TYPE2_COMPARE_7_WORD_1,
565 #[doc = "0x1740 - same as type2_compare_0_word_0"]
566 pub type2_compare_8_word_0: TYPE2_COMPARE_8_WORD_0,
567 #[doc = "0x1744 - same as type2_compare_0_word_1"]
568 pub type2_compare_8_word_1: TYPE2_COMPARE_8_WORD_1,
569 #[doc = "0x1748 - same as type2_compare_0_word_0"]
570 pub type2_compare_9_word_0: TYPE2_COMPARE_9_WORD_0,
571 #[doc = "0x174c - same as type2_compare_0_word_1"]
572 pub type2_compare_9_word_1: TYPE2_COMPARE_9_WORD_1,
573 #[doc = "0x1750 - same as type2_compare_0_word_0"]
574 pub type2_compare_10_word_0: TYPE2_COMPARE_10_WORD_0,
575 #[doc = "0x1754 - same as type2_compare_0_word_1"]
576 pub type2_compare_10_word_1: TYPE2_COMPARE_10_WORD_1,
577 #[doc = "0x1758 - same as type2_compare_0_word_0"]
578 pub type2_compare_11_word_0: TYPE2_COMPARE_11_WORD_0,
579 #[doc = "0x175c - same as type2_compare_0_word_1"]
580 pub type2_compare_11_word_1: TYPE2_COMPARE_11_WORD_1,
581 #[doc = "0x1760 - same as type2_compare_0_word_0"]
582 pub type2_compare_12_word_0: TYPE2_COMPARE_12_WORD_0,
583 #[doc = "0x1764 - same as type2_compare_0_word_1"]
584 pub type2_compare_12_word_1: TYPE2_COMPARE_12_WORD_1,
585 #[doc = "0x1768 - same as type2_compare_0_word_0"]
586 pub type2_compare_13_word_0: TYPE2_COMPARE_13_WORD_0,
587 #[doc = "0x176c - same as type2_compare_0_word_1"]
588 pub type2_compare_13_word_1: TYPE2_COMPARE_13_WORD_1,
589 #[doc = "0x1770 - same as type2_compare_0_word_0"]
590 pub type2_compare_14_word_0: TYPE2_COMPARE_14_WORD_0,
591 #[doc = "0x1774 - same as type2_compare_0_word_1"]
592 pub type2_compare_14_word_1: TYPE2_COMPARE_14_WORD_1,
593 #[doc = "0x1778 - same as type2_compare_0_word_0"]
594 pub type2_compare_15_word_0: TYPE2_COMPARE_15_WORD_0,
595 #[doc = "0x177c - same as type2_compare_0_word_1"]
596 pub type2_compare_15_word_1: TYPE2_COMPARE_15_WORD_1,
597 #[doc = "0x1780 - same as type2_compare_0_word_0"]
598 pub type2_compare_16_word_0: TYPE2_COMPARE_16_WORD_0,
599 #[doc = "0x1784 - same as type2_compare_0_word_1"]
600 pub type2_compare_16_word_1: TYPE2_COMPARE_16_WORD_1,
601 #[doc = "0x1788 - same as type2_compare_0_word_0"]
602 pub type2_compare_17_word_0: TYPE2_COMPARE_17_WORD_0,
603 #[doc = "0x178c - same as type2_compare_0_word_1"]
604 pub type2_compare_17_word_1: TYPE2_COMPARE_17_WORD_1,
605 #[doc = "0x1790 - same as type2_compare_0_word_0"]
606 pub type2_compare_18_word_0: TYPE2_COMPARE_18_WORD_0,
607 #[doc = "0x1794 - same as type2_compare_0_word_1"]
608 pub type2_compare_18_word_1: TYPE2_COMPARE_18_WORD_1,
609 #[doc = "0x1798 - same as type2_compare_0_word_0"]
610 pub type2_compare_19_word_0: TYPE2_COMPARE_19_WORD_0,
611 #[doc = "0x179c - same as type2_compare_0_word_1"]
612 pub type2_compare_19_word_1: TYPE2_COMPARE_19_WORD_1,
613 #[doc = "0x17a0 - same as type2_compare_0_word_0"]
614 pub type2_compare_20_word_0: TYPE2_COMPARE_20_WORD_0,
615 #[doc = "0x17a4 - same as type2_compare_0_word_1"]
616 pub type2_compare_20_word_1: TYPE2_COMPARE_20_WORD_1,
617 #[doc = "0x17a8 - same as type2_compare_0_word_0"]
618 pub type2_compare_21_word_0: TYPE2_COMPARE_21_WORD_0,
619 #[doc = "0x17ac - same as type2_compare_0_word_1"]
620 pub type2_compare_21_word_1: TYPE2_COMPARE_21_WORD_1,
621 #[doc = "0x17b0 - same as type2_compare_0_word_0"]
622 pub type2_compare_22_word_0: TYPE2_COMPARE_22_WORD_0,
623 #[doc = "0x17b4 - same as type2_compare_0_word_1"]
624 pub type2_compare_22_word_1: TYPE2_COMPARE_22_WORD_1,
625 #[doc = "0x17b8 - same as type2_compare_0_word_0"]
626 pub type2_compare_23_word_0: TYPE2_COMPARE_23_WORD_0,
627 #[doc = "0x17bc - same as type2_compare_0_word_1"]
628 pub type2_compare_23_word_1: TYPE2_COMPARE_23_WORD_1,
629 #[doc = "0x17c0 - same as type2_compare_0_word_0"]
630 pub type2_compare_24_word_0: TYPE2_COMPARE_24_WORD_0,
631 #[doc = "0x17c4 - same as type2_compare_0_word_1"]
632 pub type2_compare_24_word_1: TYPE2_COMPARE_24_WORD_1,
633 #[doc = "0x17c8 - same as type2_compare_0_word_0"]
634 pub type2_compare_25_word_0: TYPE2_COMPARE_25_WORD_0,
635 #[doc = "0x17cc - same as type2_compare_0_word_1"]
636 pub type2_compare_25_word_1: TYPE2_COMPARE_25_WORD_1,
637 #[doc = "0x17d0 - same as type2_compare_0_word_0"]
638 pub type2_compare_26_word_0: TYPE2_COMPARE_26_WORD_0,
639 #[doc = "0x17d4 - same as type2_compare_0_word_1"]
640 pub type2_compare_26_word_1: TYPE2_COMPARE_26_WORD_1,
641 #[doc = "0x17d8 - same as type2_compare_0_word_0"]
642 pub type2_compare_27_word_0: TYPE2_COMPARE_27_WORD_0,
643 #[doc = "0x17dc - same as type2_compare_0_word_1"]
644 pub type2_compare_27_word_1: TYPE2_COMPARE_27_WORD_1,
645 #[doc = "0x17e0 - same as type2_compare_0_word_0"]
646 pub type2_compare_28_word_0: TYPE2_COMPARE_28_WORD_0,
647 #[doc = "0x17e4 - same as type2_compare_0_word_1"]
648 pub type2_compare_28_word_1: TYPE2_COMPARE_28_WORD_1,
649 #[doc = "0x17e8 - same as type2_compare_0_word_0"]
650 pub type2_compare_29_word_0: TYPE2_COMPARE_29_WORD_0,
651 #[doc = "0x17ec - same as type2_compare_0_word_1"]
652 pub type2_compare_29_word_1: TYPE2_COMPARE_29_WORD_1,
653 #[doc = "0x17f0 - same as type2_compare_0_word_0"]
654 pub type2_compare_30_word_0: TYPE2_COMPARE_30_WORD_0,
655 #[doc = "0x17f4 - same as type2_compare_0_word_1"]
656 pub type2_compare_30_word_1: TYPE2_COMPARE_30_WORD_1,
657 #[doc = "0x17f8 - same as type2_compare_0_word_0"]
658 pub type2_compare_31_word_0: TYPE2_COMPARE_31_WORD_0,
659 #[doc = "0x17fc - same as type2_compare_0_word_1"]
660 pub type2_compare_31_word_1: TYPE2_COMPARE_31_WORD_1,
661}
662#[doc = "CTL (rw) register accessor: an alias for `Reg<CTL_SPEC>`"]
663pub type CTL = crate::Reg<ctl::CTL_SPEC>;
664#[doc = "MXETH Control Register"]
665pub mod ctl;
666#[doc = "STATUS (r) register accessor: an alias for `Reg<STATUS_SPEC>`"]
667pub type STATUS = crate::Reg<status::STATUS_SPEC>;
668#[doc = "MXETH Status Register"]
669pub mod status;
670#[doc = "NETWORK_CONTROL (rw) register accessor: an alias for `Reg<NETWORK_CONTROL_SPEC>`"]
671pub type NETWORK_CONTROL = crate::Reg<network_control::NETWORK_CONTROL_SPEC>;
672#[doc = "The network control register contains general MAC control functions for both receiver and transmitter."]
673pub mod network_control;
674#[doc = "NETWORK_CONFIG (rw) register accessor: an alias for `Reg<NETWORK_CONFIG_SPEC>`"]
675pub type NETWORK_CONFIG = crate::Reg<network_config::NETWORK_CONFIG_SPEC>;
676#[doc = "The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC."]
677pub mod network_config;
678#[doc = "NETWORK_STATUS (r) register accessor: an alias for `Reg<NETWORK_STATUS_SPEC>`"]
679pub type NETWORK_STATUS = crate::Reg<network_status::NETWORK_STATUS_SPEC>;
680#[doc = "The network status register returns status information with respect to the PHY management interface."]
681pub mod network_status;
682#[doc = "USER_IO_REGISTER (r) register accessor: an alias for `Reg<USER_IO_REGISTER_SPEC>`"]
683pub type USER_IO_REGISTER = crate::Reg<user_io_register::USER_IO_REGISTER_SPEC>;
684#[doc = "Not presents. Access to the register will return AHB error."]
685pub mod user_io_register;
686#[doc = "DMA_CONFIG (rw) register accessor: an alias for `Reg<DMA_CONFIG_SPEC>`"]
687pub type DMA_CONFIG = crate::Reg<dma_config::DMA_CONFIG_SPEC>;
688#[doc = "DMA Configuration Register"]
689pub mod dma_config;
690#[doc = "TRANSMIT_STATUS (rw) register accessor: an alias for `Reg<TRANSMIT_STATUS_SPEC>`"]
691pub type TRANSMIT_STATUS = crate::Reg<transmit_status::TRANSMIT_STATUS_SPEC>;
692#[doc = "This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."]
693pub mod transmit_status;
694#[doc = "RECEIVE_Q_PTR (rw) register accessor: an alias for `Reg<RECEIVE_Q_PTR_SPEC>`"]
695pub type RECEIVE_Q_PTR = crate::Reg<receive_q_ptr::RECEIVE_Q_PTR_SPEC>;
696#[doc = "This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AXI) operation, the receive descriptors are read from memory using a single 32bit AXI access. When the datapath is configured at 64bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AXI access."]
697pub mod receive_q_ptr;
698#[doc = "TRANSMIT_Q_PTR (rw) register accessor: an alias for `Reg<TRANSMIT_Q_PTR_SPEC>`"]
699pub type TRANSMIT_Q_PTR = crate::Reg<transmit_q_ptr::TRANSMIT_Q_PTR_SPEC>;
700#[doc = "This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
701pub mod transmit_q_ptr;
702#[doc = "RECEIVE_STATUS (rw) register accessor: an alias for `Reg<RECEIVE_STATUS_SPEC>`"]
703pub type RECEIVE_STATUS = crate::Reg<receive_status::RECEIVE_STATUS_SPEC>;
704#[doc = "This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."]
705pub mod receive_status;
706#[doc = "INT_STATUS (rw) register accessor: an alias for `Reg<INT_STATUS_SPEC>`"]
707pub type INT_STATUS = crate::Reg<int_status::INT_STATUS_SPEC>;
708#[doc = "If not configured for priority queueing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no affect on the status of the bit."]
709pub mod int_status;
710#[doc = "INT_ENABLE (w) register accessor: an alias for `Reg<INT_ENABLE_SPEC>`"]
711pub type INT_ENABLE = crate::Reg<int_enable::INT_ENABLE_SPEC>;
712#[doc = "At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
713pub mod int_enable;
714#[doc = "INT_DISABLE (rw) register accessor: an alias for `Reg<INT_DISABLE_SPEC>`"]
715pub type INT_DISABLE = crate::Reg<int_disable::INT_DISABLE_SPEC>;
716#[doc = "Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
717pub mod int_disable;
718#[doc = "INT_MASK (r) register accessor: an alias for `Reg<INT_MASK_SPEC>`"]
719pub type INT_MASK = crate::Reg<int_mask::INT_MASK_SPEC>;
720#[doc = "The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
721pub mod int_mask;
722#[doc = "PHY_MANAGEMENT (rw) register accessor: an alias for `Reg<PHY_MANAGEMENT_SPEC>`"]
723pub type PHY_MANAGEMENT = crate::Reg<phy_management::PHY_MANAGEMENT_SPEC>;
724#[doc = "The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register."]
725pub mod phy_management;
726#[doc = "PAUSE_TIME (r) register accessor: an alias for `Reg<PAUSE_TIME_SPEC>`"]
727pub type PAUSE_TIME = crate::Reg<pause_time::PAUSE_TIME_SPEC>;
728#[doc = "Received Pause Quantum Register"]
729pub mod pause_time;
730#[doc = "TX_PAUSE_QUANTUM (rw) register accessor: an alias for `Reg<TX_PAUSE_QUANTUM_SPEC>`"]
731pub type TX_PAUSE_QUANTUM = crate::Reg<tx_pause_quantum::TX_PAUSE_QUANTUM_SPEC>;
732#[doc = "Transmit Pause Quantum Register"]
733pub mod tx_pause_quantum;
734#[doc = "PBUF_TXCUTTHRU (rw) register accessor: an alias for `Reg<PBUF_TXCUTTHRU_SPEC>`"]
735pub type PBUF_TXCUTTHRU = crate::Reg<pbuf_txcutthru::PBUF_TXCUTTHRU_SPEC>;
736#[doc = "Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward"]
737pub mod pbuf_txcutthru;
738#[doc = "PBUF_RXCUTTHRU (rw) register accessor: an alias for `Reg<PBUF_RXCUTTHRU_SPEC>`"]
739pub type PBUF_RXCUTTHRU = crate::Reg<pbuf_rxcutthru::PBUF_RXCUTTHRU_SPEC>;
740#[doc = "RX Partial Store and Forward"]
741pub mod pbuf_rxcutthru;
742#[doc = "JUMBO_MAX_LENGTH (rw) register accessor: an alias for `Reg<JUMBO_MAX_LENGTH_SPEC>`"]
743pub type JUMBO_MAX_LENGTH = crate::Reg<jumbo_max_length::JUMBO_MAX_LENGTH_SPEC>;
744#[doc = "Maximum Jumbo Frame Size."]
745pub mod jumbo_max_length;
746#[doc = "EXTERNAL_FIFO_INTERFACE (r) register accessor: an alias for `Reg<EXTERNAL_FIFO_INTERFACE_SPEC>`"]
747pub type EXTERNAL_FIFO_INTERFACE =
748 crate::Reg<external_fifo_interface::EXTERNAL_FIFO_INTERFACE_SPEC>;
749#[doc = "Not presents."]
750pub mod external_fifo_interface;
751#[doc = "AXI_MAX_PIPELINE (rw) register accessor: an alias for `Reg<AXI_MAX_PIPELINE_SPEC>`"]
752pub type AXI_MAX_PIPELINE = crate::Reg<axi_max_pipeline::AXI_MAX_PIPELINE_SPEC>;
753#[doc = "Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)"]
754pub mod axi_max_pipeline;
755#[doc = "RSC_CONTROL (r) register accessor: an alias for `Reg<RSC_CONTROL_SPEC>`"]
756pub type RSC_CONTROL = crate::Reg<rsc_control::RSC_CONTROL_SPEC>;
757#[doc = "Not presents. Access to the register will return AHB error."]
758pub mod rsc_control;
759#[doc = "INT_MODERATION (rw) register accessor: an alias for `Reg<INT_MODERATION_SPEC>`"]
760pub type INT_MODERATION = crate::Reg<int_moderation::INT_MODERATION_SPEC>;
761#[doc = "Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation."]
762pub mod int_moderation;
763#[doc = "SYS_WAKE_TIME (rw) register accessor: an alias for `Reg<SYS_WAKE_TIME_SPEC>`"]
764pub type SYS_WAKE_TIME = crate::Reg<sys_wake_time::SYS_WAKE_TIME_SPEC>;
765#[doc = "Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time."]
766pub mod sys_wake_time;
767#[doc = "HASH_BOTTOM (rw) register accessor: an alias for `Reg<HASH_BOTTOM_SPEC>`"]
768pub type HASH_BOTTOM = crate::Reg<hash_bottom::HASH_BOTTOM_SPEC>;
769#[doc = "The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits)"]
770pub mod hash_bottom;
771#[doc = "HASH_TOP (rw) register accessor: an alias for `Reg<HASH_TOP_SPEC>`"]
772pub type HASH_TOP = crate::Reg<hash_top::HASH_TOP_SPEC>;
773#[doc = "Hash Register Top (63 to 32 bits)"]
774pub mod hash_top;
775#[doc = "SPEC_ADD1_BOTTOM (rw) register accessor: an alias for `Reg<SPEC_ADD1_BOTTOM_SPEC>`"]
776pub type SPEC_ADD1_BOTTOM = crate::Reg<spec_add1_bottom::SPEC_ADD1_BOTTOM_SPEC>;
777#[doc = "The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
778pub mod spec_add1_bottom;
779#[doc = "SPEC_ADD1_TOP (rw) register accessor: an alias for `Reg<SPEC_ADD1_TOP_SPEC>`"]
780pub type SPEC_ADD1_TOP = crate::Reg<spec_add1_top::SPEC_ADD1_TOP_SPEC>;
781#[doc = "Specific Address Top"]
782pub mod spec_add1_top;
783#[doc = "SPEC_ADD2_BOTTOM (rw) register accessor: an alias for `Reg<SPEC_ADD2_BOTTOM_SPEC>`"]
784pub type SPEC_ADD2_BOTTOM = crate::Reg<spec_add2_bottom::SPEC_ADD2_BOTTOM_SPEC>;
785#[doc = "The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
786pub mod spec_add2_bottom;
787#[doc = "SPEC_ADD2_TOP (rw) register accessor: an alias for `Reg<SPEC_ADD2_TOP_SPEC>`"]
788pub type SPEC_ADD2_TOP = crate::Reg<spec_add2_top::SPEC_ADD2_TOP_SPEC>;
789#[doc = "Specific Address Top"]
790pub mod spec_add2_top;
791#[doc = "SPEC_ADD3_BOTTOM (rw) register accessor: an alias for `Reg<SPEC_ADD3_BOTTOM_SPEC>`"]
792pub type SPEC_ADD3_BOTTOM = crate::Reg<spec_add3_bottom::SPEC_ADD3_BOTTOM_SPEC>;
793#[doc = "The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
794pub mod spec_add3_bottom;
795#[doc = "SPEC_ADD3_TOP (rw) register accessor: an alias for `Reg<SPEC_ADD3_TOP_SPEC>`"]
796pub type SPEC_ADD3_TOP = crate::Reg<spec_add3_top::SPEC_ADD3_TOP_SPEC>;
797#[doc = "Specific Address Top"]
798pub mod spec_add3_top;
799#[doc = "SPEC_ADD4_BOTTOM (rw) register accessor: an alias for `Reg<SPEC_ADD4_BOTTOM_SPEC>`"]
800pub type SPEC_ADD4_BOTTOM = crate::Reg<spec_add4_bottom::SPEC_ADD4_BOTTOM_SPEC>;
801#[doc = "The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."]
802pub mod spec_add4_bottom;
803#[doc = "SPEC_ADD4_TOP (rw) register accessor: an alias for `Reg<SPEC_ADD4_TOP_SPEC>`"]
804pub type SPEC_ADD4_TOP = crate::Reg<spec_add4_top::SPEC_ADD4_TOP_SPEC>;
805#[doc = "Specific Address Top"]
806pub mod spec_add4_top;
807#[doc = "SPEC_TYPE1 (rw) register accessor: an alias for `Reg<SPEC_TYPE1_SPEC>`"]
808pub type SPEC_TYPE1 = crate::Reg<spec_type1::SPEC_TYPE1_SPEC>;
809#[doc = "Type ID Match 1"]
810pub mod spec_type1;
811#[doc = "SPEC_TYPE2 (rw) register accessor: an alias for `Reg<SPEC_TYPE2_SPEC>`"]
812pub type SPEC_TYPE2 = crate::Reg<spec_type2::SPEC_TYPE2_SPEC>;
813#[doc = "Type ID Match 2"]
814pub mod spec_type2;
815#[doc = "SPEC_TYPE3 (rw) register accessor: an alias for `Reg<SPEC_TYPE3_SPEC>`"]
816pub type SPEC_TYPE3 = crate::Reg<spec_type3::SPEC_TYPE3_SPEC>;
817#[doc = "Type ID Match 3"]
818pub mod spec_type3;
819#[doc = "SPEC_TYPE4 (rw) register accessor: an alias for `Reg<SPEC_TYPE4_SPEC>`"]
820pub type SPEC_TYPE4 = crate::Reg<spec_type4::SPEC_TYPE4_SPEC>;
821#[doc = "Type ID Match 4"]
822pub mod spec_type4;
823#[doc = "WOL_REGISTER (rw) register accessor: an alias for `Reg<WOL_REGISTER_SPEC>`"]
824pub type WOL_REGISTER = crate::Reg<wol_register::WOL_REGISTER_SPEC>;
825#[doc = "Wake on LAN Register. Presents in design, but feature is not supported."]
826pub mod wol_register;
827#[doc = "STRETCH_RATIO (rw) register accessor: an alias for `Reg<STRETCH_RATIO_SPEC>`"]
828pub type STRETCH_RATIO = crate::Reg<stretch_ratio::STRETCH_RATIO_SPEC>;
829#[doc = "IPG stretch register"]
830pub mod stretch_ratio;
831#[doc = "STACKED_VLAN (rw) register accessor: an alias for `Reg<STACKED_VLAN_SPEC>`"]
832pub type STACKED_VLAN = crate::Reg<stacked_vlan::STACKED_VLAN_SPEC>;
833#[doc = "Stacked VLAN Register"]
834pub mod stacked_vlan;
835#[doc = "TX_PFC_PAUSE (rw) register accessor: an alias for `Reg<TX_PFC_PAUSE_SPEC>`"]
836pub type TX_PFC_PAUSE = crate::Reg<tx_pfc_pause::TX_PFC_PAUSE_SPEC>;
837#[doc = "Transmit PFC Pause Register"]
838pub mod tx_pfc_pause;
839#[doc = "MASK_ADD1_BOTTOM (rw) register accessor: an alias for `Reg<MASK_ADD1_BOTTOM_SPEC>`"]
840pub type MASK_ADD1_BOTTOM = crate::Reg<mask_add1_bottom::MASK_ADD1_BOTTOM_SPEC>;
841#[doc = "Specific Address Mask 1 Bottom (31 to 0 bits)"]
842pub mod mask_add1_bottom;
843#[doc = "MASK_ADD1_TOP (rw) register accessor: an alias for `Reg<MASK_ADD1_TOP_SPEC>`"]
844pub type MASK_ADD1_TOP = crate::Reg<mask_add1_top::MASK_ADD1_TOP_SPEC>;
845#[doc = "Specific Address Mask 1 Top (47 to 32 bits)"]
846pub mod mask_add1_top;
847#[doc = "DMA_ADDR_OR_MASK (rw) register accessor: an alias for `Reg<DMA_ADDR_OR_MASK_SPEC>`"]
848pub type DMA_ADDR_OR_MASK = crate::Reg<dma_addr_or_mask::DMA_ADDR_OR_MASK_SPEC>;
849#[doc = "Receive DMA Data Buffer Address Mask"]
850pub mod dma_addr_or_mask;
851#[doc = "RX_PTP_UNICAST (rw) register accessor: an alias for `Reg<RX_PTP_UNICAST_SPEC>`"]
852pub type RX_PTP_UNICAST = crate::Reg<rx_ptp_unicast::RX_PTP_UNICAST_SPEC>;
853#[doc = "PTP RX unicast IP destination address"]
854pub mod rx_ptp_unicast;
855#[doc = "TX_PTP_UNICAST (rw) register accessor: an alias for `Reg<TX_PTP_UNICAST_SPEC>`"]
856pub type TX_PTP_UNICAST = crate::Reg<tx_ptp_unicast::TX_PTP_UNICAST_SPEC>;
857#[doc = "PTP TX unicast IP destination address"]
858pub mod tx_ptp_unicast;
859#[doc = "TSU_NSEC_CMP (rw) register accessor: an alias for `Reg<TSU_NSEC_CMP_SPEC>`"]
860pub type TSU_NSEC_CMP = crate::Reg<tsu_nsec_cmp::TSU_NSEC_CMP_SPEC>;
861#[doc = "TSU timer comparison value nanoseconds"]
862pub mod tsu_nsec_cmp;
863#[doc = "TSU_SEC_CMP (rw) register accessor: an alias for `Reg<TSU_SEC_CMP_SPEC>`"]
864pub type TSU_SEC_CMP = crate::Reg<tsu_sec_cmp::TSU_SEC_CMP_SPEC>;
865#[doc = "TSU timer comparison value seconds (31 to 0 bits)"]
866pub mod tsu_sec_cmp;
867#[doc = "TSU_MSB_SEC_CMP (rw) register accessor: an alias for `Reg<TSU_MSB_SEC_CMP_SPEC>`"]
868pub type TSU_MSB_SEC_CMP = crate::Reg<tsu_msb_sec_cmp::TSU_MSB_SEC_CMP_SPEC>;
869#[doc = "TSU timer comparison value seconds (47 to 32 bits)"]
870pub mod tsu_msb_sec_cmp;
871#[doc = "TSU_PTP_TX_MSB_SEC (r) register accessor: an alias for `Reg<TSU_PTP_TX_MSB_SEC_SPEC>`"]
872pub type TSU_PTP_TX_MSB_SEC = crate::Reg<tsu_ptp_tx_msb_sec::TSU_PTP_TX_MSB_SEC_SPEC>;
873#[doc = "PTP Event Frame Transmitted Seconds Register (47 to 32 bits)"]
874pub mod tsu_ptp_tx_msb_sec;
875#[doc = "TSU_PTP_RX_MSB_SEC (r) register accessor: an alias for `Reg<TSU_PTP_RX_MSB_SEC_SPEC>`"]
876pub type TSU_PTP_RX_MSB_SEC = crate::Reg<tsu_ptp_rx_msb_sec::TSU_PTP_RX_MSB_SEC_SPEC>;
877#[doc = "PTP Event Frame Received Seconds Register (47 to 32 bits)"]
878pub mod tsu_ptp_rx_msb_sec;
879#[doc = "TSU_PEER_TX_MSB_SEC (r) register accessor: an alias for `Reg<TSU_PEER_TX_MSB_SEC_SPEC>`"]
880pub type TSU_PEER_TX_MSB_SEC = crate::Reg<tsu_peer_tx_msb_sec::TSU_PEER_TX_MSB_SEC_SPEC>;
881#[doc = "PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)"]
882pub mod tsu_peer_tx_msb_sec;
883#[doc = "TSU_PEER_RX_MSB_SEC (r) register accessor: an alias for `Reg<TSU_PEER_RX_MSB_SEC_SPEC>`"]
884pub type TSU_PEER_RX_MSB_SEC = crate::Reg<tsu_peer_rx_msb_sec::TSU_PEER_RX_MSB_SEC_SPEC>;
885#[doc = "PTP Peer Event Frame Received Seconds Register (47 to 32 bits)"]
886pub mod tsu_peer_rx_msb_sec;
887#[doc = "DPRAM_FILL_DBG (rw) register accessor: an alias for `Reg<DPRAM_FILL_DBG_SPEC>`"]
888pub type DPRAM_FILL_DBG = crate::Reg<dpram_fill_dbg::DPRAM_FILL_DBG_SPEC>;
889#[doc = "The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction."]
890pub mod dpram_fill_dbg;
891#[doc = "REVISION_REG (r) register accessor: an alias for `Reg<REVISION_REG_SPEC>`"]
892pub type REVISION_REG = crate::Reg<revision_reg::REVISION_REG_SPEC>;
893#[doc = "This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value"]
894pub mod revision_reg;
895#[doc = "OCTETS_TXED_BOTTOM (r) register accessor: an alias for `Reg<OCTETS_TXED_BOTTOM_SPEC>`"]
896pub type OCTETS_TXED_BOTTOM = crate::Reg<octets_txed_bottom::OCTETS_TXED_BOTTOM_SPEC>;
897#[doc = "Octets Transmitted lower bits (31 to 0 bits)"]
898pub mod octets_txed_bottom;
899#[doc = "OCTETS_TXED_TOP (r) register accessor: an alias for `Reg<OCTETS_TXED_TOP_SPEC>`"]
900pub type OCTETS_TXED_TOP = crate::Reg<octets_txed_top::OCTETS_TXED_TOP_SPEC>;
901#[doc = "Octets Transmitted higher bits (47 to 32 bits)"]
902pub mod octets_txed_top;
903#[doc = "FRAMES_TXED_OK (r) register accessor: an alias for `Reg<FRAMES_TXED_OK_SPEC>`"]
904pub type FRAMES_TXED_OK = crate::Reg<frames_txed_ok::FRAMES_TXED_OK_SPEC>;
905#[doc = "Frames Transmitted"]
906pub mod frames_txed_ok;
907#[doc = "BROADCAST_TXED (r) register accessor: an alias for `Reg<BROADCAST_TXED_SPEC>`"]
908pub type BROADCAST_TXED = crate::Reg<broadcast_txed::BROADCAST_TXED_SPEC>;
909#[doc = "Broadcast Frames Transmitted"]
910pub mod broadcast_txed;
911#[doc = "MULTICAST_TXED (r) register accessor: an alias for `Reg<MULTICAST_TXED_SPEC>`"]
912pub type MULTICAST_TXED = crate::Reg<multicast_txed::MULTICAST_TXED_SPEC>;
913#[doc = "Multicast Frames Transmitted"]
914pub mod multicast_txed;
915#[doc = "PAUSE_FRAMES_TXED (r) register accessor: an alias for `Reg<PAUSE_FRAMES_TXED_SPEC>`"]
916pub type PAUSE_FRAMES_TXED = crate::Reg<pause_frames_txed::PAUSE_FRAMES_TXED_SPEC>;
917#[doc = "Pause Frames Transmitted"]
918pub mod pause_frames_txed;
919#[doc = "FRAMES_TXED_64 (r) register accessor: an alias for `Reg<FRAMES_TXED_64_SPEC>`"]
920pub type FRAMES_TXED_64 = crate::Reg<frames_txed_64::FRAMES_TXED_64_SPEC>;
921#[doc = "64 Byte Frames Transmitted"]
922pub mod frames_txed_64;
923#[doc = "FRAMES_TXED_65 (r) register accessor: an alias for `Reg<FRAMES_TXED_65_SPEC>`"]
924pub type FRAMES_TXED_65 = crate::Reg<frames_txed_65::FRAMES_TXED_65_SPEC>;
925#[doc = "65 to 127 Byte Frames Transmitted"]
926pub mod frames_txed_65;
927#[doc = "FRAMES_TXED_128 (r) register accessor: an alias for `Reg<FRAMES_TXED_128_SPEC>`"]
928pub type FRAMES_TXED_128 = crate::Reg<frames_txed_128::FRAMES_TXED_128_SPEC>;
929#[doc = "128 to 255 Byte Frames Transmitted"]
930pub mod frames_txed_128;
931#[doc = "FRAMES_TXED_256 (r) register accessor: an alias for `Reg<FRAMES_TXED_256_SPEC>`"]
932pub type FRAMES_TXED_256 = crate::Reg<frames_txed_256::FRAMES_TXED_256_SPEC>;
933#[doc = "256 to 511 Byte Frames Transmitted"]
934pub mod frames_txed_256;
935#[doc = "FRAMES_TXED_512 (r) register accessor: an alias for `Reg<FRAMES_TXED_512_SPEC>`"]
936pub type FRAMES_TXED_512 = crate::Reg<frames_txed_512::FRAMES_TXED_512_SPEC>;
937#[doc = "512 to 1023 Byte Frames Transmitted"]
938pub mod frames_txed_512;
939#[doc = "FRAMES_TXED_1024 (r) register accessor: an alias for `Reg<FRAMES_TXED_1024_SPEC>`"]
940pub type FRAMES_TXED_1024 = crate::Reg<frames_txed_1024::FRAMES_TXED_1024_SPEC>;
941#[doc = "1024 to 1518 Byte Frames Transmitted"]
942pub mod frames_txed_1024;
943#[doc = "FRAMES_TXED_1519 (r) register accessor: an alias for `Reg<FRAMES_TXED_1519_SPEC>`"]
944pub type FRAMES_TXED_1519 = crate::Reg<frames_txed_1519::FRAMES_TXED_1519_SPEC>;
945#[doc = "Greater Than 1518 Byte Frames Transmitted"]
946pub mod frames_txed_1519;
947#[doc = "TX_UNDERRUNS (r) register accessor: an alias for `Reg<TX_UNDERRUNS_SPEC>`"]
948pub type TX_UNDERRUNS = crate::Reg<tx_underruns::TX_UNDERRUNS_SPEC>;
949#[doc = "Transmit Under Runs"]
950pub mod tx_underruns;
951#[doc = "SINGLE_COLLISIONS (r) register accessor: an alias for `Reg<SINGLE_COLLISIONS_SPEC>`"]
952pub type SINGLE_COLLISIONS = crate::Reg<single_collisions::SINGLE_COLLISIONS_SPEC>;
953#[doc = "Single Collision Frames. Presents in design but not support."]
954pub mod single_collisions;
955#[doc = "MULTIPLE_COLLISIONS (r) register accessor: an alias for `Reg<MULTIPLE_COLLISIONS_SPEC>`"]
956pub type MULTIPLE_COLLISIONS = crate::Reg<multiple_collisions::MULTIPLE_COLLISIONS_SPEC>;
957#[doc = "Multiple Collision Frames. Presents in design but not support."]
958pub mod multiple_collisions;
959#[doc = "EXCESSIVE_COLLISIONS (r) register accessor: an alias for `Reg<EXCESSIVE_COLLISIONS_SPEC>`"]
960pub type EXCESSIVE_COLLISIONS = crate::Reg<excessive_collisions::EXCESSIVE_COLLISIONS_SPEC>;
961#[doc = "Excessive Collisions. Presents in design but not support."]
962pub mod excessive_collisions;
963#[doc = "LATE_COLLISIONS (r) register accessor: an alias for `Reg<LATE_COLLISIONS_SPEC>`"]
964pub type LATE_COLLISIONS = crate::Reg<late_collisions::LATE_COLLISIONS_SPEC>;
965#[doc = "Late Collisions. Presents in design but not support."]
966pub mod late_collisions;
967#[doc = "DEFERRED_FRAMES (r) register accessor: an alias for `Reg<DEFERRED_FRAMES_SPEC>`"]
968pub type DEFERRED_FRAMES = crate::Reg<deferred_frames::DEFERRED_FRAMES_SPEC>;
969#[doc = "Deferred Transmission Frames. Presents in design but not support."]
970pub mod deferred_frames;
971#[doc = "CRS_ERRORS (r) register accessor: an alias for `Reg<CRS_ERRORS_SPEC>`"]
972pub type CRS_ERRORS = crate::Reg<crs_errors::CRS_ERRORS_SPEC>;
973#[doc = "Carrier Sense Errors. Presents in design but not support."]
974pub mod crs_errors;
975#[doc = "OCTETS_RXED_BOTTOM (r) register accessor: an alias for `Reg<OCTETS_RXED_BOTTOM_SPEC>`"]
976pub type OCTETS_RXED_BOTTOM = crate::Reg<octets_rxed_bottom::OCTETS_RXED_BOTTOM_SPEC>;
977#[doc = "Octets Received (31 to 0 bits)"]
978pub mod octets_rxed_bottom;
979#[doc = "OCTETS_RXED_TOP (r) register accessor: an alias for `Reg<OCTETS_RXED_TOP_SPEC>`"]
980pub type OCTETS_RXED_TOP = crate::Reg<octets_rxed_top::OCTETS_RXED_TOP_SPEC>;
981#[doc = "Octets Received (47 to 32 bits)"]
982pub mod octets_rxed_top;
983#[doc = "FRAMES_RXED_OK (r) register accessor: an alias for `Reg<FRAMES_RXED_OK_SPEC>`"]
984pub type FRAMES_RXED_OK = crate::Reg<frames_rxed_ok::FRAMES_RXED_OK_SPEC>;
985#[doc = "Frames Received"]
986pub mod frames_rxed_ok;
987#[doc = "BROADCAST_RXED (r) register accessor: an alias for `Reg<BROADCAST_RXED_SPEC>`"]
988pub type BROADCAST_RXED = crate::Reg<broadcast_rxed::BROADCAST_RXED_SPEC>;
989#[doc = "Broadcast Frames Received"]
990pub mod broadcast_rxed;
991#[doc = "MULTICAST_RXED (r) register accessor: an alias for `Reg<MULTICAST_RXED_SPEC>`"]
992pub type MULTICAST_RXED = crate::Reg<multicast_rxed::MULTICAST_RXED_SPEC>;
993#[doc = "Multicast Frames Received"]
994pub mod multicast_rxed;
995#[doc = "PAUSE_FRAMES_RXED (r) register accessor: an alias for `Reg<PAUSE_FRAMES_RXED_SPEC>`"]
996pub type PAUSE_FRAMES_RXED = crate::Reg<pause_frames_rxed::PAUSE_FRAMES_RXED_SPEC>;
997#[doc = "Pause Frames Received"]
998pub mod pause_frames_rxed;
999#[doc = "FRAMES_RXED_64 (r) register accessor: an alias for `Reg<FRAMES_RXED_64_SPEC>`"]
1000pub type FRAMES_RXED_64 = crate::Reg<frames_rxed_64::FRAMES_RXED_64_SPEC>;
1001#[doc = "64 Byte Frames Received"]
1002pub mod frames_rxed_64;
1003#[doc = "FRAMES_RXED_65 (r) register accessor: an alias for `Reg<FRAMES_RXED_65_SPEC>`"]
1004pub type FRAMES_RXED_65 = crate::Reg<frames_rxed_65::FRAMES_RXED_65_SPEC>;
1005#[doc = "65 to 127 Byte Frames Received"]
1006pub mod frames_rxed_65;
1007#[doc = "FRAMES_RXED_128 (r) register accessor: an alias for `Reg<FRAMES_RXED_128_SPEC>`"]
1008pub type FRAMES_RXED_128 = crate::Reg<frames_rxed_128::FRAMES_RXED_128_SPEC>;
1009#[doc = "128 to 255 Byte Frames Received"]
1010pub mod frames_rxed_128;
1011#[doc = "FRAMES_RXED_256 (r) register accessor: an alias for `Reg<FRAMES_RXED_256_SPEC>`"]
1012pub type FRAMES_RXED_256 = crate::Reg<frames_rxed_256::FRAMES_RXED_256_SPEC>;
1013#[doc = "256 to 511 Byte Frames Received"]
1014pub mod frames_rxed_256;
1015#[doc = "FRAMES_RXED_512 (r) register accessor: an alias for `Reg<FRAMES_RXED_512_SPEC>`"]
1016pub type FRAMES_RXED_512 = crate::Reg<frames_rxed_512::FRAMES_RXED_512_SPEC>;
1017#[doc = "512 to 1023 Byte Frames Received"]
1018pub mod frames_rxed_512;
1019#[doc = "FRAMES_RXED_1024 (r) register accessor: an alias for `Reg<FRAMES_RXED_1024_SPEC>`"]
1020pub type FRAMES_RXED_1024 = crate::Reg<frames_rxed_1024::FRAMES_RXED_1024_SPEC>;
1021#[doc = "1024 to 1518 Byte Frames Received"]
1022pub mod frames_rxed_1024;
1023#[doc = "FRAMES_RXED_1519 (r) register accessor: an alias for `Reg<FRAMES_RXED_1519_SPEC>`"]
1024pub type FRAMES_RXED_1519 = crate::Reg<frames_rxed_1519::FRAMES_RXED_1519_SPEC>;
1025#[doc = "1519 to maximum Byte Frames Received"]
1026pub mod frames_rxed_1519;
1027#[doc = "UNDERSIZE_FRAMES (r) register accessor: an alias for `Reg<UNDERSIZE_FRAMES_SPEC>`"]
1028pub type UNDERSIZE_FRAMES = crate::Reg<undersize_frames::UNDERSIZE_FRAMES_SPEC>;
1029#[doc = "Undersized Frames Received"]
1030pub mod undersize_frames;
1031#[doc = "EXCESSIVE_RX_LENGTH (r) register accessor: an alias for `Reg<EXCESSIVE_RX_LENGTH_SPEC>`"]
1032pub type EXCESSIVE_RX_LENGTH = crate::Reg<excessive_rx_length::EXCESSIVE_RX_LENGTH_SPEC>;
1033#[doc = "Oversize Frames Received"]
1034pub mod excessive_rx_length;
1035#[doc = "RX_JABBERS (r) register accessor: an alias for `Reg<RX_JABBERS_SPEC>`"]
1036pub type RX_JABBERS = crate::Reg<rx_jabbers::RX_JABBERS_SPEC>;
1037#[doc = "Jabbers Received"]
1038pub mod rx_jabbers;
1039#[doc = "FCS_ERRORS (r) register accessor: an alias for `Reg<FCS_ERRORS_SPEC>`"]
1040pub type FCS_ERRORS = crate::Reg<fcs_errors::FCS_ERRORS_SPEC>;
1041#[doc = "Frame Check Sequence Errors"]
1042pub mod fcs_errors;
1043#[doc = "RX_LENGTH_ERRORS (r) register accessor: an alias for `Reg<RX_LENGTH_ERRORS_SPEC>`"]
1044pub type RX_LENGTH_ERRORS = crate::Reg<rx_length_errors::RX_LENGTH_ERRORS_SPEC>;
1045#[doc = "Length Field Frame Errors"]
1046pub mod rx_length_errors;
1047#[doc = "RX_SYMBOL_ERRORS (r) register accessor: an alias for `Reg<RX_SYMBOL_ERRORS_SPEC>`"]
1048pub type RX_SYMBOL_ERRORS = crate::Reg<rx_symbol_errors::RX_SYMBOL_ERRORS_SPEC>;
1049#[doc = "Receive Symbol Errors"]
1050pub mod rx_symbol_errors;
1051#[doc = "ALIGNMENT_ERRORS (r) register accessor: an alias for `Reg<ALIGNMENT_ERRORS_SPEC>`"]
1052pub type ALIGNMENT_ERRORS = crate::Reg<alignment_errors::ALIGNMENT_ERRORS_SPEC>;
1053#[doc = "Alignment Errors"]
1054pub mod alignment_errors;
1055#[doc = "RX_RESOURCE_ERRORS (r) register accessor: an alias for `Reg<RX_RESOURCE_ERRORS_SPEC>`"]
1056pub type RX_RESOURCE_ERRORS = crate::Reg<rx_resource_errors::RX_RESOURCE_ERRORS_SPEC>;
1057#[doc = "Receive Resource Errors"]
1058pub mod rx_resource_errors;
1059#[doc = "RX_OVERRUNS (r) register accessor: an alias for `Reg<RX_OVERRUNS_SPEC>`"]
1060pub type RX_OVERRUNS = crate::Reg<rx_overruns::RX_OVERRUNS_SPEC>;
1061#[doc = "Receive Overruns"]
1062pub mod rx_overruns;
1063#[doc = "RX_IP_CK_ERRORS (r) register accessor: an alias for `Reg<RX_IP_CK_ERRORS_SPEC>`"]
1064pub type RX_IP_CK_ERRORS = crate::Reg<rx_ip_ck_errors::RX_IP_CK_ERRORS_SPEC>;
1065#[doc = "IP Header Checksum Errors"]
1066pub mod rx_ip_ck_errors;
1067#[doc = "RX_TCP_CK_ERRORS (r) register accessor: an alias for `Reg<RX_TCP_CK_ERRORS_SPEC>`"]
1068pub type RX_TCP_CK_ERRORS = crate::Reg<rx_tcp_ck_errors::RX_TCP_CK_ERRORS_SPEC>;
1069#[doc = "TCP Checksum Errors"]
1070pub mod rx_tcp_ck_errors;
1071#[doc = "RX_UDP_CK_ERRORS (r) register accessor: an alias for `Reg<RX_UDP_CK_ERRORS_SPEC>`"]
1072pub type RX_UDP_CK_ERRORS = crate::Reg<rx_udp_ck_errors::RX_UDP_CK_ERRORS_SPEC>;
1073#[doc = "UDP Checksum Errors"]
1074pub mod rx_udp_ck_errors;
1075#[doc = "AUTO_FLUSHED_PKTS (r) register accessor: an alias for `Reg<AUTO_FLUSHED_PKTS_SPEC>`"]
1076pub type AUTO_FLUSHED_PKTS = crate::Reg<auto_flushed_pkts::AUTO_FLUSHED_PKTS_SPEC>;
1077#[doc = "Receive DMA Flushed Packets"]
1078pub mod auto_flushed_pkts;
1079#[doc = "TSU_TIMER_INCR_SUB_NSEC (rw) register accessor: an alias for `Reg<TSU_TIMER_INCR_SUB_NSEC_SPEC>`"]
1080pub type TSU_TIMER_INCR_SUB_NSEC =
1081 crate::Reg<tsu_timer_incr_sub_nsec::TSU_TIMER_INCR_SUB_NSEC_SPEC>;
1082#[doc = "1588 Timer Increment Register sub nsec"]
1083pub mod tsu_timer_incr_sub_nsec;
1084#[doc = "TSU_TIMER_MSB_SEC (rw) register accessor: an alias for `Reg<TSU_TIMER_MSB_SEC_SPEC>`"]
1085pub type TSU_TIMER_MSB_SEC = crate::Reg<tsu_timer_msb_sec::TSU_TIMER_MSB_SEC_SPEC>;
1086#[doc = "1588 Timer Seconds Register (47 to 32 bits)"]
1087pub mod tsu_timer_msb_sec;
1088#[doc = "TSU_STROBE_MSB_SEC (r) register accessor: an alias for `Reg<TSU_STROBE_MSB_SEC_SPEC>`"]
1089pub type TSU_STROBE_MSB_SEC = crate::Reg<tsu_strobe_msb_sec::TSU_STROBE_MSB_SEC_SPEC>;
1090#[doc = "1588 Timer Sync Strobe Seconds Register (47 to 32 bits)"]
1091pub mod tsu_strobe_msb_sec;
1092#[doc = "TSU_STROBE_SEC (r) register accessor: an alias for `Reg<TSU_STROBE_SEC_SPEC>`"]
1093pub type TSU_STROBE_SEC = crate::Reg<tsu_strobe_sec::TSU_STROBE_SEC_SPEC>;
1094#[doc = "1588 Timer Sync Strobe Seconds Register (31 to 0 bits)"]
1095pub mod tsu_strobe_sec;
1096#[doc = "TSU_STROBE_NSEC (r) register accessor: an alias for `Reg<TSU_STROBE_NSEC_SPEC>`"]
1097pub type TSU_STROBE_NSEC = crate::Reg<tsu_strobe_nsec::TSU_STROBE_NSEC_SPEC>;
1098#[doc = "1588 Timer Sync Strobe Nanoseconds Register"]
1099pub mod tsu_strobe_nsec;
1100#[doc = "TSU_TIMER_SEC (rw) register accessor: an alias for `Reg<TSU_TIMER_SEC_SPEC>`"]
1101pub type TSU_TIMER_SEC = crate::Reg<tsu_timer_sec::TSU_TIMER_SEC_SPEC>;
1102#[doc = "1588 Timer Seconds Register (31 to 0 bits)"]
1103pub mod tsu_timer_sec;
1104#[doc = "TSU_TIMER_NSEC (rw) register accessor: an alias for `Reg<TSU_TIMER_NSEC_SPEC>`"]
1105pub type TSU_TIMER_NSEC = crate::Reg<tsu_timer_nsec::TSU_TIMER_NSEC_SPEC>;
1106#[doc = "1588 Timer Nanoseconds Register"]
1107pub mod tsu_timer_nsec;
1108#[doc = "TSU_TIMER_ADJUST (w) register accessor: an alias for `Reg<TSU_TIMER_ADJUST_SPEC>`"]
1109pub type TSU_TIMER_ADJUST = crate::Reg<tsu_timer_adjust::TSU_TIMER_ADJUST_SPEC>;
1110#[doc = "This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read."]
1111pub mod tsu_timer_adjust;
1112#[doc = "TSU_TIMER_INCR (rw) register accessor: an alias for `Reg<TSU_TIMER_INCR_SPEC>`"]
1113pub type TSU_TIMER_INCR = crate::Reg<tsu_timer_incr::TSU_TIMER_INCR_SPEC>;
1114#[doc = "1588 Timer Increment Register"]
1115pub mod tsu_timer_incr;
1116#[doc = "TSU_PTP_TX_SEC (r) register accessor: an alias for `Reg<TSU_PTP_TX_SEC_SPEC>`"]
1117pub type TSU_PTP_TX_SEC = crate::Reg<tsu_ptp_tx_sec::TSU_PTP_TX_SEC_SPEC>;
1118#[doc = "PTP Event Frame Transmitted Seconds Register (31 to 0 bits)"]
1119pub mod tsu_ptp_tx_sec;
1120#[doc = "TSU_PTP_TX_NSEC (r) register accessor: an alias for `Reg<TSU_PTP_TX_NSEC_SPEC>`"]
1121pub type TSU_PTP_TX_NSEC = crate::Reg<tsu_ptp_tx_nsec::TSU_PTP_TX_NSEC_SPEC>;
1122#[doc = "PTP Event Frame Transmitted Nanoseconds Register"]
1123pub mod tsu_ptp_tx_nsec;
1124#[doc = "TSU_PTP_RX_SEC (r) register accessor: an alias for `Reg<TSU_PTP_RX_SEC_SPEC>`"]
1125pub type TSU_PTP_RX_SEC = crate::Reg<tsu_ptp_rx_sec::TSU_PTP_RX_SEC_SPEC>;
1126#[doc = "PTP Event Frame Received Seconds Register (31 to 0 bits)"]
1127pub mod tsu_ptp_rx_sec;
1128#[doc = "TSU_PTP_RX_NSEC (r) register accessor: an alias for `Reg<TSU_PTP_RX_NSEC_SPEC>`"]
1129pub type TSU_PTP_RX_NSEC = crate::Reg<tsu_ptp_rx_nsec::TSU_PTP_RX_NSEC_SPEC>;
1130#[doc = "PTP Event Frame Received Nanoseconds Register"]
1131pub mod tsu_ptp_rx_nsec;
1132#[doc = "TSU_PEER_TX_SEC (r) register accessor: an alias for `Reg<TSU_PEER_TX_SEC_SPEC>`"]
1133pub type TSU_PEER_TX_SEC = crate::Reg<tsu_peer_tx_sec::TSU_PEER_TX_SEC_SPEC>;
1134#[doc = "PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)"]
1135pub mod tsu_peer_tx_sec;
1136#[doc = "TSU_PEER_TX_NSEC (r) register accessor: an alias for `Reg<TSU_PEER_TX_NSEC_SPEC>`"]
1137pub type TSU_PEER_TX_NSEC = crate::Reg<tsu_peer_tx_nsec::TSU_PEER_TX_NSEC_SPEC>;
1138#[doc = "PTP Peer Event Frame Transmitted Nanoseconds Register"]
1139pub mod tsu_peer_tx_nsec;
1140#[doc = "TSU_PEER_RX_SEC (r) register accessor: an alias for `Reg<TSU_PEER_RX_SEC_SPEC>`"]
1141pub type TSU_PEER_RX_SEC = crate::Reg<tsu_peer_rx_sec::TSU_PEER_RX_SEC_SPEC>;
1142#[doc = "PTP Peer Event Frame Received Seconds Register (31 to 0 bits)"]
1143pub mod tsu_peer_rx_sec;
1144#[doc = "TSU_PEER_RX_NSEC (r) register accessor: an alias for `Reg<TSU_PEER_RX_NSEC_SPEC>`"]
1145pub type TSU_PEER_RX_NSEC = crate::Reg<tsu_peer_rx_nsec::TSU_PEER_RX_NSEC_SPEC>;
1146#[doc = "PTP Peer Event Frame Received Nanoseconds Register"]
1147pub mod tsu_peer_rx_nsec;
1148#[doc = "PCS_CONTROL (r) register accessor: an alias for `Reg<PCS_CONTROL_SPEC>`"]
1149pub type PCS_CONTROL = crate::Reg<pcs_control::PCS_CONTROL_SPEC>;
1150#[doc = "Not presents. Access to the register returns AHB error."]
1151pub mod pcs_control;
1152#[doc = "PCS_STATUS (r) register accessor: an alias for `Reg<PCS_STATUS_SPEC>`"]
1153pub type PCS_STATUS = crate::Reg<pcs_status::PCS_STATUS_SPEC>;
1154#[doc = "Not presents. Access to the register returns AHB error."]
1155pub mod pcs_status;
1156#[doc = "PCS_AN_ADV (r) register accessor: an alias for `Reg<PCS_AN_ADV_SPEC>`"]
1157pub type PCS_AN_ADV = crate::Reg<pcs_an_adv::PCS_AN_ADV_SPEC>;
1158#[doc = "Not presents. Access to the register returns AHB error."]
1159pub mod pcs_an_adv;
1160#[doc = "PCS_AN_LP_BASE (r) register accessor: an alias for `Reg<PCS_AN_LP_BASE_SPEC>`"]
1161pub type PCS_AN_LP_BASE = crate::Reg<pcs_an_lp_base::PCS_AN_LP_BASE_SPEC>;
1162#[doc = "Not presents. Access to the register returns AHB error."]
1163pub mod pcs_an_lp_base;
1164#[doc = "PCS_AN_EXP (r) register accessor: an alias for `Reg<PCS_AN_EXP_SPEC>`"]
1165pub type PCS_AN_EXP = crate::Reg<pcs_an_exp::PCS_AN_EXP_SPEC>;
1166#[doc = "Not presents. Access to the register returns AHB error."]
1167pub mod pcs_an_exp;
1168#[doc = "PCS_AN_NP_TX (r) register accessor: an alias for `Reg<PCS_AN_NP_TX_SPEC>`"]
1169pub type PCS_AN_NP_TX = crate::Reg<pcs_an_np_tx::PCS_AN_NP_TX_SPEC>;
1170#[doc = "Not presents. Access to the register returns AHB error."]
1171pub mod pcs_an_np_tx;
1172#[doc = "PCS_AN_LP_NP (r) register accessor: an alias for `Reg<PCS_AN_LP_NP_SPEC>`"]
1173pub type PCS_AN_LP_NP = crate::Reg<pcs_an_lp_np::PCS_AN_LP_NP_SPEC>;
1174#[doc = "Not presents. Access to the register returns AHB error."]
1175pub mod pcs_an_lp_np;
1176#[doc = "PCS_AN_EXT_STATUS (r) register accessor: an alias for `Reg<PCS_AN_EXT_STATUS_SPEC>`"]
1177pub type PCS_AN_EXT_STATUS = crate::Reg<pcs_an_ext_status::PCS_AN_EXT_STATUS_SPEC>;
1178#[doc = "Not presents. Access to the register returns AHB error."]
1179pub mod pcs_an_ext_status;
1180#[doc = "TX_PAUSE_QUANTUM1 (rw) register accessor: an alias for `Reg<TX_PAUSE_QUANTUM1_SPEC>`"]
1181pub type TX_PAUSE_QUANTUM1 = crate::Reg<tx_pause_quantum1::TX_PAUSE_QUANTUM1_SPEC>;
1182#[doc = "Transmit Pause Quantum Register 1"]
1183pub mod tx_pause_quantum1;
1184#[doc = "TX_PAUSE_QUANTUM2 (rw) register accessor: an alias for `Reg<TX_PAUSE_QUANTUM2_SPEC>`"]
1185pub type TX_PAUSE_QUANTUM2 = crate::Reg<tx_pause_quantum2::TX_PAUSE_QUANTUM2_SPEC>;
1186#[doc = "Transmit Pause Quantum Register 2"]
1187pub mod tx_pause_quantum2;
1188#[doc = "TX_PAUSE_QUANTUM3 (rw) register accessor: an alias for `Reg<TX_PAUSE_QUANTUM3_SPEC>`"]
1189pub type TX_PAUSE_QUANTUM3 = crate::Reg<tx_pause_quantum3::TX_PAUSE_QUANTUM3_SPEC>;
1190#[doc = "Transmit Pause Quantum Register 3"]
1191pub mod tx_pause_quantum3;
1192#[doc = "RX_LPI (r) register accessor: an alias for `Reg<RX_LPI_SPEC>`"]
1193pub type RX_LPI = crate::Reg<rx_lpi::RX_LPI_SPEC>;
1194#[doc = "Received LPI transitions"]
1195pub mod rx_lpi;
1196#[doc = "RX_LPI_TIME (r) register accessor: an alias for `Reg<RX_LPI_TIME_SPEC>`"]
1197pub type RX_LPI_TIME = crate::Reg<rx_lpi_time::RX_LPI_TIME_SPEC>;
1198#[doc = "Received LPI time"]
1199pub mod rx_lpi_time;
1200#[doc = "TX_LPI (r) register accessor: an alias for `Reg<TX_LPI_SPEC>`"]
1201pub type TX_LPI = crate::Reg<tx_lpi::TX_LPI_SPEC>;
1202#[doc = "Transmit LPI transitions"]
1203pub mod tx_lpi;
1204#[doc = "TX_LPI_TIME (r) register accessor: an alias for `Reg<TX_LPI_TIME_SPEC>`"]
1205pub type TX_LPI_TIME = crate::Reg<tx_lpi_time::TX_LPI_TIME_SPEC>;
1206#[doc = "Transmit LPI time"]
1207pub mod tx_lpi_time;
1208#[doc = "DESIGNCFG_DEBUG1 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG1_SPEC>`"]
1209pub type DESIGNCFG_DEBUG1 = crate::Reg<designcfg_debug1::DESIGNCFG_DEBUG1_SPEC>;
1210#[doc = "The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v."]
1211pub mod designcfg_debug1;
1212#[doc = "DESIGNCFG_DEBUG2 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG2_SPEC>`"]
1213pub type DESIGNCFG_DEBUG2 = crate::Reg<designcfg_debug2::DESIGNCFG_DEBUG2_SPEC>;
1214#[doc = "Design Configuration Register 2"]
1215pub mod designcfg_debug2;
1216#[doc = "DESIGNCFG_DEBUG3 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG3_SPEC>`"]
1217pub type DESIGNCFG_DEBUG3 = crate::Reg<designcfg_debug3::DESIGNCFG_DEBUG3_SPEC>;
1218#[doc = "Design Configuration Register 3"]
1219pub mod designcfg_debug3;
1220#[doc = "DESIGNCFG_DEBUG4 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG4_SPEC>`"]
1221pub type DESIGNCFG_DEBUG4 = crate::Reg<designcfg_debug4::DESIGNCFG_DEBUG4_SPEC>;
1222#[doc = "Design Configuration Register 4"]
1223pub mod designcfg_debug4;
1224#[doc = "DESIGNCFG_DEBUG5 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG5_SPEC>`"]
1225pub type DESIGNCFG_DEBUG5 = crate::Reg<designcfg_debug5::DESIGNCFG_DEBUG5_SPEC>;
1226#[doc = "Design Configuration Register 5"]
1227pub mod designcfg_debug5;
1228#[doc = "DESIGNCFG_DEBUG6 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG6_SPEC>`"]
1229pub type DESIGNCFG_DEBUG6 = crate::Reg<designcfg_debug6::DESIGNCFG_DEBUG6_SPEC>;
1230#[doc = "Design Configuration Register 6"]
1231pub mod designcfg_debug6;
1232#[doc = "DESIGNCFG_DEBUG7 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG7_SPEC>`"]
1233pub type DESIGNCFG_DEBUG7 = crate::Reg<designcfg_debug7::DESIGNCFG_DEBUG7_SPEC>;
1234#[doc = "Design Configuration Register 7"]
1235pub mod designcfg_debug7;
1236#[doc = "DESIGNCFG_DEBUG8 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG8_SPEC>`"]
1237pub type DESIGNCFG_DEBUG8 = crate::Reg<designcfg_debug8::DESIGNCFG_DEBUG8_SPEC>;
1238#[doc = "Design Configuration Register 8"]
1239pub mod designcfg_debug8;
1240#[doc = "DESIGNCFG_DEBUG9 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG9_SPEC>`"]
1241pub type DESIGNCFG_DEBUG9 = crate::Reg<designcfg_debug9::DESIGNCFG_DEBUG9_SPEC>;
1242#[doc = "Design Configuration Register 9"]
1243pub mod designcfg_debug9;
1244#[doc = "DESIGNCFG_DEBUG10 (r) register accessor: an alias for `Reg<DESIGNCFG_DEBUG10_SPEC>`"]
1245pub type DESIGNCFG_DEBUG10 = crate::Reg<designcfg_debug10::DESIGNCFG_DEBUG10_SPEC>;
1246#[doc = "Design Configuration Register 10"]
1247pub mod designcfg_debug10;
1248#[doc = "SPEC_ADD5_BOTTOM (r) register accessor: an alias for `Reg<SPEC_ADD5_BOTTOM_SPEC>`"]
1249pub type SPEC_ADD5_BOTTOM = crate::Reg<spec_add5_bottom::SPEC_ADD5_BOTTOM_SPEC>;
1250#[doc = "Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."]
1251pub mod spec_add5_bottom;
1252#[doc = "SPEC_ADD5_TOP (r) register accessor: an alias for `Reg<SPEC_ADD5_TOP_SPEC>`"]
1253pub type SPEC_ADD5_TOP = crate::Reg<spec_add5_top::SPEC_ADD5_TOP_SPEC>;
1254#[doc = "Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."]
1255pub mod spec_add5_top;
1256#[doc = "SPEC_ADD36_BOTTOM (r) register accessor: an alias for `Reg<SPEC_ADD36_BOTTOM_SPEC>`"]
1257pub type SPEC_ADD36_BOTTOM = crate::Reg<spec_add36_bottom::SPEC_ADD36_BOTTOM_SPEC>;
1258#[doc = "Not presents."]
1259pub mod spec_add36_bottom;
1260#[doc = "SPEC_ADD36_TOP (r) register accessor: an alias for `Reg<SPEC_ADD36_TOP_SPEC>`"]
1261pub type SPEC_ADD36_TOP = crate::Reg<spec_add36_top::SPEC_ADD36_TOP_SPEC>;
1262#[doc = "Not presents."]
1263pub mod spec_add36_top;
1264#[doc = "INT_Q1_STATUS (r) register accessor: an alias for `Reg<INT_Q1_STATUS_SPEC>`"]
1265pub type INT_Q1_STATUS = crate::Reg<int_q1_status::INT_Q1_STATUS_SPEC>;
1266#[doc = "Priority queue Interrupt Status Register"]
1267pub mod int_q1_status;
1268#[doc = "INT_Q2_STATUS (r) register accessor: an alias for `Reg<INT_Q2_STATUS_SPEC>`"]
1269pub type INT_Q2_STATUS = crate::Reg<int_q2_status::INT_Q2_STATUS_SPEC>;
1270#[doc = "Priority queue Interrupt Status Register"]
1271pub mod int_q2_status;
1272#[doc = "INT_Q3_STATUS (r) register accessor: an alias for `Reg<INT_Q3_STATUS_SPEC>`"]
1273pub type INT_Q3_STATUS = crate::Reg<int_q3_status::INT_Q3_STATUS_SPEC>;
1274#[doc = "int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error."]
1275pub mod int_q3_status;
1276#[doc = "INT_Q15_STATUS (r) register accessor: an alias for `Reg<INT_Q15_STATUS_SPEC>`"]
1277pub type INT_Q15_STATUS = crate::Reg<int_q15_status::INT_Q15_STATUS_SPEC>;
1278#[doc = "Not presents."]
1279pub mod int_q15_status;
1280#[doc = "TRANSMIT_Q1_PTR (rw) register accessor: an alias for `Reg<TRANSMIT_Q1_PTR_SPEC>`"]
1281pub type TRANSMIT_Q1_PTR = crate::Reg<transmit_q1_ptr::TRANSMIT_Q1_PTR_SPEC>;
1282#[doc = "This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
1283pub mod transmit_q1_ptr;
1284#[doc = "TRANSMIT_Q2_PTR (rw) register accessor: an alias for `Reg<TRANSMIT_Q2_PTR_SPEC>`"]
1285pub type TRANSMIT_Q2_PTR = crate::Reg<transmit_q2_ptr::TRANSMIT_Q2_PTR_SPEC>;
1286#[doc = "This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
1287pub mod transmit_q2_ptr;
1288#[doc = "TRANSMIT_Q3_PTR (r) register accessor: an alias for `Reg<TRANSMIT_Q3_PTR_SPEC>`"]
1289pub type TRANSMIT_Q3_PTR = crate::Reg<transmit_q3_ptr::TRANSMIT_Q3_PTR_SPEC>;
1290#[doc = "transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error."]
1291pub mod transmit_q3_ptr;
1292#[doc = "TRANSMIT_Q15_PTR (r) register accessor: an alias for `Reg<TRANSMIT_Q15_PTR_SPEC>`"]
1293pub type TRANSMIT_Q15_PTR = crate::Reg<transmit_q15_ptr::TRANSMIT_Q15_PTR_SPEC>;
1294#[doc = "Not presents."]
1295pub mod transmit_q15_ptr;
1296#[doc = "RECEIVE_Q1_PTR (rw) register accessor: an alias for `Reg<RECEIVE_Q1_PTR_SPEC>`"]
1297pub type RECEIVE_Q1_PTR = crate::Reg<receive_q1_ptr::RECEIVE_Q1_PTR_SPEC>;
1298#[doc = "This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
1299pub mod receive_q1_ptr;
1300#[doc = "RECEIVE_Q2_PTR (rw) register accessor: an alias for `Reg<RECEIVE_Q2_PTR_SPEC>`"]
1301pub type RECEIVE_Q2_PTR = crate::Reg<receive_q2_ptr::RECEIVE_Q2_PTR_SPEC>;
1302#[doc = "This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access."]
1303pub mod receive_q2_ptr;
1304#[doc = "RECEIVE_Q3_PTR (r) register accessor: an alias for `Reg<RECEIVE_Q3_PTR_SPEC>`"]
1305pub type RECEIVE_Q3_PTR = crate::Reg<receive_q3_ptr::RECEIVE_Q3_PTR_SPEC>;
1306#[doc = "Not presents. Start address register doesn't present for queue3 ~ queue7."]
1307pub mod receive_q3_ptr;
1308#[doc = "RECEIVE_Q7_PTR (r) register accessor: an alias for `Reg<RECEIVE_Q7_PTR_SPEC>`"]
1309pub type RECEIVE_Q7_PTR = crate::Reg<receive_q7_ptr::RECEIVE_Q7_PTR_SPEC>;
1310#[doc = "Not presents."]
1311pub mod receive_q7_ptr;
1312#[doc = "DMA_RXBUF_SIZE_Q1 (rw) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q1_SPEC>`"]
1313pub type DMA_RXBUF_SIZE_Q1 = crate::Reg<dma_rxbuf_size_q1::DMA_RXBUF_SIZE_Q1_SPEC>;
1314#[doc = "Receive Buffer queue 1 Size"]
1315pub mod dma_rxbuf_size_q1;
1316#[doc = "DMA_RXBUF_SIZE_Q2 (rw) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q2_SPEC>`"]
1317pub type DMA_RXBUF_SIZE_Q2 = crate::Reg<dma_rxbuf_size_q2::DMA_RXBUF_SIZE_Q2_SPEC>;
1318#[doc = "Receive Buffer queue 2 Size"]
1319pub mod dma_rxbuf_size_q2;
1320#[doc = "DMA_RXBUF_SIZE_Q3 (r) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q3_SPEC>`"]
1321pub type DMA_RXBUF_SIZE_Q3 = crate::Reg<dma_rxbuf_size_q3::DMA_RXBUF_SIZE_Q3_SPEC>;
1322#[doc = "dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present."]
1323pub mod dma_rxbuf_size_q3;
1324#[doc = "DMA_RXBUF_SIZE_Q7 (r) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q7_SPEC>`"]
1325pub type DMA_RXBUF_SIZE_Q7 = crate::Reg<dma_rxbuf_size_q7::DMA_RXBUF_SIZE_Q7_SPEC>;
1326#[doc = "Not presents."]
1327pub mod dma_rxbuf_size_q7;
1328#[doc = "CBS_CONTROL (rw) register accessor: an alias for `Reg<CBS_CONTROL_SPEC>`"]
1329pub type CBS_CONTROL = crate::Reg<cbs_control::CBS_CONTROL_SPEC>;
1330#[doc = "The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note that Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved."]
1331pub mod cbs_control;
1332#[doc = "CBS_IDLESLOPE_Q_A (rw) register accessor: an alias for `Reg<CBS_IDLESLOPE_Q_A_SPEC>`"]
1333pub type CBS_IDLESLOPE_Q_A = crate::Reg<cbs_idleslope_q_a::CBS_IDLESLOPE_Q_A_SPEC>;
1334#[doc = "queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration."]
1335pub mod cbs_idleslope_q_a;
1336#[doc = "CBS_IDLESLOPE_Q_B (rw) register accessor: an alias for `Reg<CBS_IDLESLOPE_Q_B_SPEC>`"]
1337pub type CBS_IDLESLOPE_Q_B = crate::Reg<cbs_idleslope_q_b::CBS_IDLESLOPE_Q_B_SPEC>;
1338#[doc = "queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration."]
1339pub mod cbs_idleslope_q_b;
1340#[doc = "UPPER_TX_Q_BASE_ADDR (rw) register accessor: an alias for `Reg<UPPER_TX_Q_BASE_ADDR_SPEC>`"]
1341pub type UPPER_TX_Q_BASE_ADDR = crate::Reg<upper_tx_q_base_addr::UPPER_TX_Q_BASE_ADDR_SPEC>;
1342#[doc = "Upper 32 bits of transmit buffer descriptor queue base address."]
1343pub mod upper_tx_q_base_addr;
1344#[doc = "TX_BD_CONTROL (rw) register accessor: an alias for `Reg<TX_BD_CONTROL_SPEC>`"]
1345pub type TX_BD_CONTROL = crate::Reg<tx_bd_control::TX_BD_CONTROL_SPEC>;
1346#[doc = "TX BD control register"]
1347pub mod tx_bd_control;
1348#[doc = "RX_BD_CONTROL (rw) register accessor: an alias for `Reg<RX_BD_CONTROL_SPEC>`"]
1349pub type RX_BD_CONTROL = crate::Reg<rx_bd_control::RX_BD_CONTROL_SPEC>;
1350#[doc = "RX BD control register"]
1351pub mod rx_bd_control;
1352#[doc = "UPPER_RX_Q_BASE_ADDR (rw) register accessor: an alias for `Reg<UPPER_RX_Q_BASE_ADDR_SPEC>`"]
1353pub type UPPER_RX_Q_BASE_ADDR = crate::Reg<upper_rx_q_base_addr::UPPER_RX_Q_BASE_ADDR_SPEC>;
1354#[doc = "Upper 32 bits of receive buffer descriptor queue base address."]
1355pub mod upper_rx_q_base_addr;
1356#[doc = "HIDDEN_REG0 (rw) register accessor: an alias for `Reg<HIDDEN_REG0_SPEC>`"]
1357pub type HIDDEN_REG0 = crate::Reg<hidden_reg0::HIDDEN_REG0_SPEC>;
1358#[doc = "Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register."]
1359pub mod hidden_reg0;
1360#[doc = "HIDDEN_REG1 (rw) register accessor: an alias for `Reg<HIDDEN_REG1_SPEC>`"]
1361pub type HIDDEN_REG1 = crate::Reg<hidden_reg1::HIDDEN_REG1_SPEC>;
1362#[doc = "Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***'"]
1363pub mod hidden_reg1;
1364#[doc = "HIDDEN_REG2 (rw) register accessor: an alias for `Reg<HIDDEN_REG2_SPEC>`"]
1365pub type HIDDEN_REG2 = crate::Reg<hidden_reg2::HIDDEN_REG2_SPEC>;
1366#[doc = "Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***'"]
1367pub mod hidden_reg2;
1368#[doc = "HIDDEN_REG3 (rw) register accessor: an alias for `Reg<HIDDEN_REG3_SPEC>`"]
1369pub type HIDDEN_REG3 = crate::Reg<hidden_reg3::HIDDEN_REG3_SPEC>;
1370#[doc = "Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'."]
1371pub mod hidden_reg3;
1372#[doc = "HIDDEN_REG4 (rw) register accessor: an alias for `Reg<HIDDEN_REG4_SPEC>`"]
1373pub type HIDDEN_REG4 = crate::Reg<hidden_reg4::HIDDEN_REG4_SPEC>;
1374#[doc = "Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width ( gem_dma_bus_width == 32 or bits 22 to 21 of the network_config register are set to 0) the AXI hidden registers (0x14F8 and 0x14FC) need to be updated (these registers are used for fine tuning AXI dma bursts and normally should not be touched)."]
1375pub mod hidden_reg4;
1376#[doc = "HIDDEN_REG5 (rw) register accessor: an alias for `Reg<HIDDEN_REG5_SPEC>`"]
1377pub type HIDDEN_REG5 = crate::Reg<hidden_reg5::HIDDEN_REG5_SPEC>;
1378#[doc = "Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'."]
1379pub mod hidden_reg5;
1380#[doc = "SCREENING_TYPE_1_REGISTER_0 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_0_SPEC>`"]
1381pub type SCREENING_TYPE_1_REGISTER_0 =
1382 crate::Reg<screening_type_1_register_0::SCREENING_TYPE_1_REGISTER_0_SPEC>;
1383#[doc = "Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11 to 4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27 to 12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 2 to 0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C."]
1384pub mod screening_type_1_register_0;
1385#[doc = "SCREENING_TYPE_1_REGISTER_1 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_1_SPEC>`"]
1386pub type SCREENING_TYPE_1_REGISTER_1 =
1387 crate::Reg<screening_type_1_register_1::SCREENING_TYPE_1_REGISTER_1_SPEC>;
1388#[doc = "screening type 1 register 1, same as screening_type_1_register_0"]
1389pub mod screening_type_1_register_1;
1390#[doc = "SCREENING_TYPE_1_REGISTER_2 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_2_SPEC>`"]
1391pub type SCREENING_TYPE_1_REGISTER_2 =
1392 crate::Reg<screening_type_1_register_2::SCREENING_TYPE_1_REGISTER_2_SPEC>;
1393#[doc = "screening type 1 register 2, same as screening_type_1_register_0"]
1394pub mod screening_type_1_register_2;
1395#[doc = "SCREENING_TYPE_1_REGISTER_3 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_3_SPEC>`"]
1396pub type SCREENING_TYPE_1_REGISTER_3 =
1397 crate::Reg<screening_type_1_register_3::SCREENING_TYPE_1_REGISTER_3_SPEC>;
1398#[doc = "screening type 1 register 3, same as screening_type_1_register_0"]
1399pub mod screening_type_1_register_3;
1400#[doc = "SCREENING_TYPE_1_REGISTER_4 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_4_SPEC>`"]
1401pub type SCREENING_TYPE_1_REGISTER_4 =
1402 crate::Reg<screening_type_1_register_4::SCREENING_TYPE_1_REGISTER_4_SPEC>;
1403#[doc = "screening type 1 register 4, same as screening_type_1_register_0"]
1404pub mod screening_type_1_register_4;
1405#[doc = "SCREENING_TYPE_1_REGISTER_5 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_5_SPEC>`"]
1406pub type SCREENING_TYPE_1_REGISTER_5 =
1407 crate::Reg<screening_type_1_register_5::SCREENING_TYPE_1_REGISTER_5_SPEC>;
1408#[doc = "screening type 1 register 5, same as screening_type_1_register_0"]
1409pub mod screening_type_1_register_5;
1410#[doc = "SCREENING_TYPE_1_REGISTER_6 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_6_SPEC>`"]
1411pub type SCREENING_TYPE_1_REGISTER_6 =
1412 crate::Reg<screening_type_1_register_6::SCREENING_TYPE_1_REGISTER_6_SPEC>;
1413#[doc = "screening type 1 register 6, same as screening_type_1_register_0"]
1414pub mod screening_type_1_register_6;
1415#[doc = "SCREENING_TYPE_1_REGISTER_7 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_7_SPEC>`"]
1416pub type SCREENING_TYPE_1_REGISTER_7 =
1417 crate::Reg<screening_type_1_register_7::SCREENING_TYPE_1_REGISTER_7_SPEC>;
1418#[doc = "screening type 1 register 7, same as screening_type_1_register_0"]
1419pub mod screening_type_1_register_7;
1420#[doc = "SCREENING_TYPE_1_REGISTER_8 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_8_SPEC>`"]
1421pub type SCREENING_TYPE_1_REGISTER_8 =
1422 crate::Reg<screening_type_1_register_8::SCREENING_TYPE_1_REGISTER_8_SPEC>;
1423#[doc = "screening type 1 register 8, same as screening_type_1_register_0"]
1424pub mod screening_type_1_register_8;
1425#[doc = "SCREENING_TYPE_1_REGISTER_9 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_9_SPEC>`"]
1426pub type SCREENING_TYPE_1_REGISTER_9 =
1427 crate::Reg<screening_type_1_register_9::SCREENING_TYPE_1_REGISTER_9_SPEC>;
1428#[doc = "screening type 1 register 9, same as screening_type_1_register_0"]
1429pub mod screening_type_1_register_9;
1430#[doc = "SCREENING_TYPE_1_REGISTER_10 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_10_SPEC>`"]
1431pub type SCREENING_TYPE_1_REGISTER_10 =
1432 crate::Reg<screening_type_1_register_10::SCREENING_TYPE_1_REGISTER_10_SPEC>;
1433#[doc = "screening type 1 register 10, same as screening_type_1_register_0"]
1434pub mod screening_type_1_register_10;
1435#[doc = "SCREENING_TYPE_1_REGISTER_11 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_11_SPEC>`"]
1436pub type SCREENING_TYPE_1_REGISTER_11 =
1437 crate::Reg<screening_type_1_register_11::SCREENING_TYPE_1_REGISTER_11_SPEC>;
1438#[doc = "screening type 1 register 11, same as screening_type_1_register_0"]
1439pub mod screening_type_1_register_11;
1440#[doc = "SCREENING_TYPE_1_REGISTER_12 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_12_SPEC>`"]
1441pub type SCREENING_TYPE_1_REGISTER_12 =
1442 crate::Reg<screening_type_1_register_12::SCREENING_TYPE_1_REGISTER_12_SPEC>;
1443#[doc = "screening type 1 register 12, same as screening_type_1_register_0"]
1444pub mod screening_type_1_register_12;
1445#[doc = "SCREENING_TYPE_1_REGISTER_13 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_13_SPEC>`"]
1446pub type SCREENING_TYPE_1_REGISTER_13 =
1447 crate::Reg<screening_type_1_register_13::SCREENING_TYPE_1_REGISTER_13_SPEC>;
1448#[doc = "screening type 1 register 13, same as screening_type_1_register_0"]
1449pub mod screening_type_1_register_13;
1450#[doc = "SCREENING_TYPE_1_REGISTER_14 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_14_SPEC>`"]
1451pub type SCREENING_TYPE_1_REGISTER_14 =
1452 crate::Reg<screening_type_1_register_14::SCREENING_TYPE_1_REGISTER_14_SPEC>;
1453#[doc = "screening type 1 register 14, same as screening_type_1_register_0"]
1454pub mod screening_type_1_register_14;
1455#[doc = "SCREENING_TYPE_1_REGISTER_15 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_1_REGISTER_15_SPEC>`"]
1456pub type SCREENING_TYPE_1_REGISTER_15 =
1457 crate::Reg<screening_type_1_register_15::SCREENING_TYPE_1_REGISTER_15_SPEC>;
1458#[doc = "screening type 1 register 15, same as screening_type_1_register_0"]
1459pub mod screening_type_1_register_15;
1460#[doc = "SCREENING_TYPE_2_REGISTER_0 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_0_SPEC>`"]
1461pub type SCREENING_TYPE_2_REGISTER_0 =
1462 crate::Reg<screening_type_2_register_0::SCREENING_TYPE_2_REGISTER_0_SPEC>;
1463#[doc = "Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities, extending the capabilities into vendor specific protocols."]
1464pub mod screening_type_2_register_0;
1465#[doc = "SCREENING_TYPE_2_REGISTER_1 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_1_SPEC>`"]
1466pub type SCREENING_TYPE_2_REGISTER_1 =
1467 crate::Reg<screening_type_2_register_1::SCREENING_TYPE_2_REGISTER_1_SPEC>;
1468#[doc = "screening type 2 register 1, same as screening_type_2_register_0"]
1469pub mod screening_type_2_register_1;
1470#[doc = "SCREENING_TYPE_2_REGISTER_2 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_2_SPEC>`"]
1471pub type SCREENING_TYPE_2_REGISTER_2 =
1472 crate::Reg<screening_type_2_register_2::SCREENING_TYPE_2_REGISTER_2_SPEC>;
1473#[doc = "screening type 2 register 2, same as screening_type_2_register_0"]
1474pub mod screening_type_2_register_2;
1475#[doc = "SCREENING_TYPE_2_REGISTER_3 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_3_SPEC>`"]
1476pub type SCREENING_TYPE_2_REGISTER_3 =
1477 crate::Reg<screening_type_2_register_3::SCREENING_TYPE_2_REGISTER_3_SPEC>;
1478#[doc = "screening type 2 register 3, same as screening_type_2_register_0"]
1479pub mod screening_type_2_register_3;
1480#[doc = "SCREENING_TYPE_2_REGISTER_4 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_4_SPEC>`"]
1481pub type SCREENING_TYPE_2_REGISTER_4 =
1482 crate::Reg<screening_type_2_register_4::SCREENING_TYPE_2_REGISTER_4_SPEC>;
1483#[doc = "screening type 2 register 4, same as screening_type_2_register_0"]
1484pub mod screening_type_2_register_4;
1485#[doc = "SCREENING_TYPE_2_REGISTER_5 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_5_SPEC>`"]
1486pub type SCREENING_TYPE_2_REGISTER_5 =
1487 crate::Reg<screening_type_2_register_5::SCREENING_TYPE_2_REGISTER_5_SPEC>;
1488#[doc = "screening type 2 register 5, same as screening_type_2_register_0"]
1489pub mod screening_type_2_register_5;
1490#[doc = "SCREENING_TYPE_2_REGISTER_6 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_6_SPEC>`"]
1491pub type SCREENING_TYPE_2_REGISTER_6 =
1492 crate::Reg<screening_type_2_register_6::SCREENING_TYPE_2_REGISTER_6_SPEC>;
1493#[doc = "screening type 2 register 6, same as screening_type_2_register_0"]
1494pub mod screening_type_2_register_6;
1495#[doc = "SCREENING_TYPE_2_REGISTER_7 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_7_SPEC>`"]
1496pub type SCREENING_TYPE_2_REGISTER_7 =
1497 crate::Reg<screening_type_2_register_7::SCREENING_TYPE_2_REGISTER_7_SPEC>;
1498#[doc = "screening type 2 register 7, same as screening_type_2_register_0"]
1499pub mod screening_type_2_register_7;
1500#[doc = "SCREENING_TYPE_2_REGISTER_8 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_8_SPEC>`"]
1501pub type SCREENING_TYPE_2_REGISTER_8 =
1502 crate::Reg<screening_type_2_register_8::SCREENING_TYPE_2_REGISTER_8_SPEC>;
1503#[doc = "screening type 2 register 8, same as screening_type_2_register_0"]
1504pub mod screening_type_2_register_8;
1505#[doc = "SCREENING_TYPE_2_REGISTER_9 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_9_SPEC>`"]
1506pub type SCREENING_TYPE_2_REGISTER_9 =
1507 crate::Reg<screening_type_2_register_9::SCREENING_TYPE_2_REGISTER_9_SPEC>;
1508#[doc = "screening type 2 register 9, same as screening_type_2_register_0"]
1509pub mod screening_type_2_register_9;
1510#[doc = "SCREENING_TYPE_2_REGISTER_10 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_10_SPEC>`"]
1511pub type SCREENING_TYPE_2_REGISTER_10 =
1512 crate::Reg<screening_type_2_register_10::SCREENING_TYPE_2_REGISTER_10_SPEC>;
1513#[doc = "screening type 2 register 10, same as screening_type_2_register_0"]
1514pub mod screening_type_2_register_10;
1515#[doc = "SCREENING_TYPE_2_REGISTER_11 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_11_SPEC>`"]
1516pub type SCREENING_TYPE_2_REGISTER_11 =
1517 crate::Reg<screening_type_2_register_11::SCREENING_TYPE_2_REGISTER_11_SPEC>;
1518#[doc = "screening type 2 register 11, same as screening_type_2_register_0"]
1519pub mod screening_type_2_register_11;
1520#[doc = "SCREENING_TYPE_2_REGISTER_12 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_12_SPEC>`"]
1521pub type SCREENING_TYPE_2_REGISTER_12 =
1522 crate::Reg<screening_type_2_register_12::SCREENING_TYPE_2_REGISTER_12_SPEC>;
1523#[doc = "screening type 2 register 12, same as screening_type_2_register_0"]
1524pub mod screening_type_2_register_12;
1525#[doc = "SCREENING_TYPE_2_REGISTER_13 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_13_SPEC>`"]
1526pub type SCREENING_TYPE_2_REGISTER_13 =
1527 crate::Reg<screening_type_2_register_13::SCREENING_TYPE_2_REGISTER_13_SPEC>;
1528#[doc = "screening type 2 register 13, same as screening_type_2_register_0"]
1529pub mod screening_type_2_register_13;
1530#[doc = "SCREENING_TYPE_2_REGISTER_14 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_14_SPEC>`"]
1531pub type SCREENING_TYPE_2_REGISTER_14 =
1532 crate::Reg<screening_type_2_register_14::SCREENING_TYPE_2_REGISTER_14_SPEC>;
1533#[doc = "screening type 2 register 14, same as screening_type_2_register_0"]
1534pub mod screening_type_2_register_14;
1535#[doc = "SCREENING_TYPE_2_REGISTER_15 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_REGISTER_15_SPEC>`"]
1536pub type SCREENING_TYPE_2_REGISTER_15 =
1537 crate::Reg<screening_type_2_register_15::SCREENING_TYPE_2_REGISTER_15_SPEC>;
1538#[doc = "screening type 2 register 15, same as screening_type_2_register_0"]
1539pub mod screening_type_2_register_15;
1540#[doc = "TX_SCHED_CTRL (rw) register accessor: an alias for `Reg<TX_SCHED_CTRL_SPEC>`"]
1541pub type TX_SCHED_CTRL = crate::Reg<tx_sched_ctrl::TX_SCHED_CTRL_SPEC>;
1542#[doc = "This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority"]
1543pub mod tx_sched_ctrl;
1544#[doc = "BW_RATE_LIMIT_Q0TO3 (rw) register accessor: an alias for `Reg<BW_RATE_LIMIT_Q0TO3_SPEC>`"]
1545pub type BW_RATE_LIMIT_Q0TO3 = crate::Reg<bw_rate_limit_q0to3::BW_RATE_LIMIT_Q0TO3_SPEC>;
1546#[doc = "This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3."]
1547pub mod bw_rate_limit_q0to3;
1548#[doc = "BW_RATE_LIMIT_Q4TO7 (rw) register accessor: an alias for `Reg<BW_RATE_LIMIT_Q4TO7_SPEC>`"]
1549pub type BW_RATE_LIMIT_Q4TO7 = crate::Reg<bw_rate_limit_q4to7::BW_RATE_LIMIT_Q4TO7_SPEC>;
1550#[doc = "Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
1551pub mod bw_rate_limit_q4to7;
1552#[doc = "BW_RATE_LIMIT_Q8TO11 (r) register accessor: an alias for `Reg<BW_RATE_LIMIT_Q8TO11_SPEC>`"]
1553pub type BW_RATE_LIMIT_Q8TO11 = crate::Reg<bw_rate_limit_q8to11::BW_RATE_LIMIT_Q8TO11_SPEC>;
1554#[doc = "Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
1555pub mod bw_rate_limit_q8to11;
1556#[doc = "BW_RATE_LIMIT_Q12TO15 (r) register accessor: an alias for `Reg<BW_RATE_LIMIT_Q12TO15_SPEC>`"]
1557pub type BW_RATE_LIMIT_Q12TO15 = crate::Reg<bw_rate_limit_q12to15::BW_RATE_LIMIT_Q12TO15_SPEC>;
1558#[doc = "Not presents. MXETH has only 3 queues. Access to the register returns AHB error."]
1559pub mod bw_rate_limit_q12to15;
1560#[doc = "TX_Q_SEG_ALLOC_Q0TO7 (rw) register accessor: an alias for `Reg<TX_Q_SEG_ALLOC_Q0TO7_SPEC>`"]
1561pub type TX_Q_SEG_ALLOC_Q0TO7 = crate::Reg<tx_q_seg_alloc_q0to7::TX_Q_SEG_ALLOC_Q0TO7_SPEC>;
1562#[doc = "This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file."]
1563pub mod tx_q_seg_alloc_q0to7;
1564#[doc = "TX_Q_SEG_ALLOC_Q8TO15 (r) register accessor: an alias for `Reg<TX_Q_SEG_ALLOC_Q8TO15_SPEC>`"]
1565pub type TX_Q_SEG_ALLOC_Q8TO15 = crate::Reg<tx_q_seg_alloc_q8to15::TX_Q_SEG_ALLOC_Q8TO15_SPEC>;
1566#[doc = "Not presents. Access to the register returns AHB error."]
1567pub mod tx_q_seg_alloc_q8to15;
1568#[doc = "RECEIVE_Q8_PTR (r) register accessor: an alias for `Reg<RECEIVE_Q8_PTR_SPEC>`"]
1569pub type RECEIVE_Q8_PTR = crate::Reg<receive_q8_ptr::RECEIVE_Q8_PTR_SPEC>;
1570#[doc = "receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error."]
1571pub mod receive_q8_ptr;
1572#[doc = "RECEIVE_Q15_PTR (r) register accessor: an alias for `Reg<RECEIVE_Q15_PTR_SPEC>`"]
1573pub type RECEIVE_Q15_PTR = crate::Reg<receive_q15_ptr::RECEIVE_Q15_PTR_SPEC>;
1574#[doc = "Not presents."]
1575pub mod receive_q15_ptr;
1576#[doc = "DMA_RXBUF_SIZE_Q8 (r) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q8_SPEC>`"]
1577pub type DMA_RXBUF_SIZE_Q8 = crate::Reg<dma_rxbuf_size_q8::DMA_RXBUF_SIZE_Q8_SPEC>;
1578#[doc = "dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error."]
1579pub mod dma_rxbuf_size_q8;
1580#[doc = "DMA_RXBUF_SIZE_Q15 (r) register accessor: an alias for `Reg<DMA_RXBUF_SIZE_Q15_SPEC>`"]
1581pub type DMA_RXBUF_SIZE_Q15 = crate::Reg<dma_rxbuf_size_q15::DMA_RXBUF_SIZE_Q15_SPEC>;
1582#[doc = "Not presents."]
1583pub mod dma_rxbuf_size_q15;
1584#[doc = "INT_Q1_ENABLE (w) register accessor: an alias for `Reg<INT_Q1_ENABLE_SPEC>`"]
1585pub type INT_Q1_ENABLE = crate::Reg<int_q1_enable::INT_Q1_ENABLE_SPEC>;
1586#[doc = "At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
1587pub mod int_q1_enable;
1588#[doc = "INT_Q2_ENABLE (w) register accessor: an alias for `Reg<INT_Q2_ENABLE_SPEC>`"]
1589pub type INT_Q2_ENABLE = crate::Reg<int_q2_enable::INT_Q2_ENABLE_SPEC>;
1590#[doc = "At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."]
1591pub mod int_q2_enable;
1592#[doc = "INT_Q3_ENABLE (r) register accessor: an alias for `Reg<INT_Q3_ENABLE_SPEC>`"]
1593pub type INT_Q3_ENABLE = crate::Reg<int_q3_enable::INT_Q3_ENABLE_SPEC>;
1594#[doc = "int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error."]
1595pub mod int_q3_enable;
1596#[doc = "INT_Q7_ENABLE (r) register accessor: an alias for `Reg<INT_Q7_ENABLE_SPEC>`"]
1597pub type INT_Q7_ENABLE = crate::Reg<int_q7_enable::INT_Q7_ENABLE_SPEC>;
1598#[doc = "Not presents."]
1599pub mod int_q7_enable;
1600#[doc = "INT_Q1_DISABLE (w) register accessor: an alias for `Reg<INT_Q1_DISABLE_SPEC>`"]
1601pub type INT_Q1_DISABLE = crate::Reg<int_q1_disable::INT_Q1_DISABLE_SPEC>;
1602#[doc = "Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
1603pub mod int_q1_disable;
1604#[doc = "INT_Q2_DISABLE (w) register accessor: an alias for `Reg<INT_Q2_DISABLE_SPEC>`"]
1605pub type INT_Q2_DISABLE = crate::Reg<int_q2_disable::INT_Q2_DISABLE_SPEC>;
1606#[doc = "Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."]
1607pub mod int_q2_disable;
1608#[doc = "INT_Q3_DISABLE (r) register accessor: an alias for `Reg<INT_Q3_DISABLE_SPEC>`"]
1609pub type INT_Q3_DISABLE = crate::Reg<int_q3_disable::INT_Q3_DISABLE_SPEC>;
1610#[doc = "int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error."]
1611pub mod int_q3_disable;
1612#[doc = "INT_Q7_DISABLE (r) register accessor: an alias for `Reg<INT_Q7_DISABLE_SPEC>`"]
1613pub type INT_Q7_DISABLE = crate::Reg<int_q7_disable::INT_Q7_DISABLE_SPEC>;
1614#[doc = "Not presents."]
1615pub mod int_q7_disable;
1616#[doc = "INT_Q1_MASK (r) register accessor: an alias for `Reg<INT_Q1_MASK_SPEC>`"]
1617pub type INT_Q1_MASK = crate::Reg<int_q1_mask::INT_Q1_MASK_SPEC>;
1618#[doc = "The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
1619pub mod int_q1_mask;
1620#[doc = "INT_Q2_MASK (r) register accessor: an alias for `Reg<INT_Q2_MASK_SPEC>`"]
1621pub type INT_Q2_MASK = crate::Reg<int_q2_mask::INT_Q2_MASK_SPEC>;
1622#[doc = "The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register."]
1623pub mod int_q2_mask;
1624#[doc = "INT_Q3_MASK (r) register accessor: an alias for `Reg<INT_Q3_MASK_SPEC>`"]
1625pub type INT_Q3_MASK = crate::Reg<int_q3_mask::INT_Q3_MASK_SPEC>;
1626#[doc = "int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error."]
1627pub mod int_q3_mask;
1628#[doc = "INT_Q7_MASK (r) register accessor: an alias for `Reg<INT_Q7_MASK_SPEC>`"]
1629pub type INT_Q7_MASK = crate::Reg<int_q7_mask::INT_Q7_MASK_SPEC>;
1630#[doc = "Not presents."]
1631pub mod int_q7_mask;
1632#[doc = "INT_Q8_ENABLE (r) register accessor: an alias for `Reg<INT_Q8_ENABLE_SPEC>`"]
1633pub type INT_Q8_ENABLE = crate::Reg<int_q8_enable::INT_Q8_ENABLE_SPEC>;
1634#[doc = "int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error."]
1635pub mod int_q8_enable;
1636#[doc = "INT_Q15_ENABLE (r) register accessor: an alias for `Reg<INT_Q15_ENABLE_SPEC>`"]
1637pub type INT_Q15_ENABLE = crate::Reg<int_q15_enable::INT_Q15_ENABLE_SPEC>;
1638#[doc = "Not presents."]
1639pub mod int_q15_enable;
1640#[doc = "INT_Q8_DISABLE (r) register accessor: an alias for `Reg<INT_Q8_DISABLE_SPEC>`"]
1641pub type INT_Q8_DISABLE = crate::Reg<int_q8_disable::INT_Q8_DISABLE_SPEC>;
1642#[doc = "int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error."]
1643pub mod int_q8_disable;
1644#[doc = "INT_Q15_DISABLE (r) register accessor: an alias for `Reg<INT_Q15_DISABLE_SPEC>`"]
1645pub type INT_Q15_DISABLE = crate::Reg<int_q15_disable::INT_Q15_DISABLE_SPEC>;
1646#[doc = "Not presents."]
1647pub mod int_q15_disable;
1648#[doc = "INT_Q8_MASK (r) register accessor: an alias for `Reg<INT_Q8_MASK_SPEC>`"]
1649pub type INT_Q8_MASK = crate::Reg<int_q8_mask::INT_Q8_MASK_SPEC>;
1650#[doc = "int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error."]
1651pub mod int_q8_mask;
1652#[doc = "INT_Q15_MASK (r) register accessor: an alias for `Reg<INT_Q15_MASK_SPEC>`"]
1653pub type INT_Q15_MASK = crate::Reg<int_q15_mask::INT_Q15_MASK_SPEC>;
1654#[doc = "Not presents."]
1655pub mod int_q15_mask;
1656#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_0 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_0_SPEC>`"]
1657pub type SCREENING_TYPE_2_ETHERTYPE_REG_0 =
1658 crate::Reg<screening_type_2_ethertype_reg_0::SCREENING_TYPE_2_ETHERTYPE_REG_0_SPEC>;
1659#[doc = "Ethertype Register"]
1660pub mod screening_type_2_ethertype_reg_0;
1661#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_1 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_1_SPEC>`"]
1662pub type SCREENING_TYPE_2_ETHERTYPE_REG_1 =
1663 crate::Reg<screening_type_2_ethertype_reg_1::SCREENING_TYPE_2_ETHERTYPE_REG_1_SPEC>;
1664#[doc = "Ethertype Register"]
1665pub mod screening_type_2_ethertype_reg_1;
1666#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_2 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_2_SPEC>`"]
1667pub type SCREENING_TYPE_2_ETHERTYPE_REG_2 =
1668 crate::Reg<screening_type_2_ethertype_reg_2::SCREENING_TYPE_2_ETHERTYPE_REG_2_SPEC>;
1669#[doc = "Ethertype Register"]
1670pub mod screening_type_2_ethertype_reg_2;
1671#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_3 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_3_SPEC>`"]
1672pub type SCREENING_TYPE_2_ETHERTYPE_REG_3 =
1673 crate::Reg<screening_type_2_ethertype_reg_3::SCREENING_TYPE_2_ETHERTYPE_REG_3_SPEC>;
1674#[doc = "Ethertype Register"]
1675pub mod screening_type_2_ethertype_reg_3;
1676#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_4 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_4_SPEC>`"]
1677pub type SCREENING_TYPE_2_ETHERTYPE_REG_4 =
1678 crate::Reg<screening_type_2_ethertype_reg_4::SCREENING_TYPE_2_ETHERTYPE_REG_4_SPEC>;
1679#[doc = "Ethertype Register"]
1680pub mod screening_type_2_ethertype_reg_4;
1681#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_5 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_5_SPEC>`"]
1682pub type SCREENING_TYPE_2_ETHERTYPE_REG_5 =
1683 crate::Reg<screening_type_2_ethertype_reg_5::SCREENING_TYPE_2_ETHERTYPE_REG_5_SPEC>;
1684#[doc = "Ethertype Register"]
1685pub mod screening_type_2_ethertype_reg_5;
1686#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_6 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_6_SPEC>`"]
1687pub type SCREENING_TYPE_2_ETHERTYPE_REG_6 =
1688 crate::Reg<screening_type_2_ethertype_reg_6::SCREENING_TYPE_2_ETHERTYPE_REG_6_SPEC>;
1689#[doc = "Ethertype Register"]
1690pub mod screening_type_2_ethertype_reg_6;
1691#[doc = "SCREENING_TYPE_2_ETHERTYPE_REG_7 (rw) register accessor: an alias for `Reg<SCREENING_TYPE_2_ETHERTYPE_REG_7_SPEC>`"]
1692pub type SCREENING_TYPE_2_ETHERTYPE_REG_7 =
1693 crate::Reg<screening_type_2_ethertype_reg_7::SCREENING_TYPE_2_ETHERTYPE_REG_7_SPEC>;
1694#[doc = "Ethertype Register"]
1695pub mod screening_type_2_ethertype_reg_7;
1696#[doc = "TYPE2_COMPARE_0_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_0_WORD_0_SPEC>`"]
1697pub type TYPE2_COMPARE_0_WORD_0 = crate::Reg<type2_compare_0_word_0::TYPE2_COMPARE_0_WORD_0_SPEC>;
1698#[doc = "'Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7 to 0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15 to 8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. '"]
1699pub mod type2_compare_0_word_0;
1700#[doc = "TYPE2_COMPARE_0_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_0_WORD_1_SPEC>`"]
1701pub type TYPE2_COMPARE_0_WORD_1 = crate::Reg<type2_compare_0_word_1::TYPE2_COMPARE_0_WORD_1_SPEC>;
1702#[doc = "'Type2 Compare Word 1'"]
1703pub mod type2_compare_0_word_1;
1704#[doc = "TYPE2_COMPARE_1_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_1_WORD_0_SPEC>`"]
1705pub type TYPE2_COMPARE_1_WORD_0 = crate::Reg<type2_compare_1_word_0::TYPE2_COMPARE_1_WORD_0_SPEC>;
1706#[doc = "same as type2_compare_0_word_0"]
1707pub mod type2_compare_1_word_0;
1708#[doc = "TYPE2_COMPARE_1_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_1_WORD_1_SPEC>`"]
1709pub type TYPE2_COMPARE_1_WORD_1 = crate::Reg<type2_compare_1_word_1::TYPE2_COMPARE_1_WORD_1_SPEC>;
1710#[doc = "same as type2_compare_0_word_1"]
1711pub mod type2_compare_1_word_1;
1712#[doc = "TYPE2_COMPARE_2_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_2_WORD_0_SPEC>`"]
1713pub type TYPE2_COMPARE_2_WORD_0 = crate::Reg<type2_compare_2_word_0::TYPE2_COMPARE_2_WORD_0_SPEC>;
1714#[doc = "same as type2_compare_0_word_0"]
1715pub mod type2_compare_2_word_0;
1716#[doc = "TYPE2_COMPARE_2_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_2_WORD_1_SPEC>`"]
1717pub type TYPE2_COMPARE_2_WORD_1 = crate::Reg<type2_compare_2_word_1::TYPE2_COMPARE_2_WORD_1_SPEC>;
1718#[doc = "same as type2_compare_0_word_1"]
1719pub mod type2_compare_2_word_1;
1720#[doc = "TYPE2_COMPARE_3_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_3_WORD_0_SPEC>`"]
1721pub type TYPE2_COMPARE_3_WORD_0 = crate::Reg<type2_compare_3_word_0::TYPE2_COMPARE_3_WORD_0_SPEC>;
1722#[doc = "same as type2_compare_0_word_0"]
1723pub mod type2_compare_3_word_0;
1724#[doc = "TYPE2_COMPARE_3_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_3_WORD_1_SPEC>`"]
1725pub type TYPE2_COMPARE_3_WORD_1 = crate::Reg<type2_compare_3_word_1::TYPE2_COMPARE_3_WORD_1_SPEC>;
1726#[doc = "same as type2_compare_0_word_1"]
1727pub mod type2_compare_3_word_1;
1728#[doc = "TYPE2_COMPARE_4_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_4_WORD_0_SPEC>`"]
1729pub type TYPE2_COMPARE_4_WORD_0 = crate::Reg<type2_compare_4_word_0::TYPE2_COMPARE_4_WORD_0_SPEC>;
1730#[doc = "same as type2_compare_0_word_0"]
1731pub mod type2_compare_4_word_0;
1732#[doc = "TYPE2_COMPARE_4_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_4_WORD_1_SPEC>`"]
1733pub type TYPE2_COMPARE_4_WORD_1 = crate::Reg<type2_compare_4_word_1::TYPE2_COMPARE_4_WORD_1_SPEC>;
1734#[doc = "same as type2_compare_0_word_1"]
1735pub mod type2_compare_4_word_1;
1736#[doc = "TYPE2_COMPARE_5_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_5_WORD_0_SPEC>`"]
1737pub type TYPE2_COMPARE_5_WORD_0 = crate::Reg<type2_compare_5_word_0::TYPE2_COMPARE_5_WORD_0_SPEC>;
1738#[doc = "same as type2_compare_0_word_0"]
1739pub mod type2_compare_5_word_0;
1740#[doc = "TYPE2_COMPARE_5_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_5_WORD_1_SPEC>`"]
1741pub type TYPE2_COMPARE_5_WORD_1 = crate::Reg<type2_compare_5_word_1::TYPE2_COMPARE_5_WORD_1_SPEC>;
1742#[doc = "same as type2_compare_0_word_1"]
1743pub mod type2_compare_5_word_1;
1744#[doc = "TYPE2_COMPARE_6_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_6_WORD_0_SPEC>`"]
1745pub type TYPE2_COMPARE_6_WORD_0 = crate::Reg<type2_compare_6_word_0::TYPE2_COMPARE_6_WORD_0_SPEC>;
1746#[doc = "same as type2_compare_0_word_0"]
1747pub mod type2_compare_6_word_0;
1748#[doc = "TYPE2_COMPARE_6_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_6_WORD_1_SPEC>`"]
1749pub type TYPE2_COMPARE_6_WORD_1 = crate::Reg<type2_compare_6_word_1::TYPE2_COMPARE_6_WORD_1_SPEC>;
1750#[doc = "same as type2_compare_0_word_1"]
1751pub mod type2_compare_6_word_1;
1752#[doc = "TYPE2_COMPARE_7_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_7_WORD_0_SPEC>`"]
1753pub type TYPE2_COMPARE_7_WORD_0 = crate::Reg<type2_compare_7_word_0::TYPE2_COMPARE_7_WORD_0_SPEC>;
1754#[doc = "same as type2_compare_0_word_0"]
1755pub mod type2_compare_7_word_0;
1756#[doc = "TYPE2_COMPARE_7_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_7_WORD_1_SPEC>`"]
1757pub type TYPE2_COMPARE_7_WORD_1 = crate::Reg<type2_compare_7_word_1::TYPE2_COMPARE_7_WORD_1_SPEC>;
1758#[doc = "same as type2_compare_0_word_1"]
1759pub mod type2_compare_7_word_1;
1760#[doc = "TYPE2_COMPARE_8_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_8_WORD_0_SPEC>`"]
1761pub type TYPE2_COMPARE_8_WORD_0 = crate::Reg<type2_compare_8_word_0::TYPE2_COMPARE_8_WORD_0_SPEC>;
1762#[doc = "same as type2_compare_0_word_0"]
1763pub mod type2_compare_8_word_0;
1764#[doc = "TYPE2_COMPARE_8_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_8_WORD_1_SPEC>`"]
1765pub type TYPE2_COMPARE_8_WORD_1 = crate::Reg<type2_compare_8_word_1::TYPE2_COMPARE_8_WORD_1_SPEC>;
1766#[doc = "same as type2_compare_0_word_1"]
1767pub mod type2_compare_8_word_1;
1768#[doc = "TYPE2_COMPARE_9_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_9_WORD_0_SPEC>`"]
1769pub type TYPE2_COMPARE_9_WORD_0 = crate::Reg<type2_compare_9_word_0::TYPE2_COMPARE_9_WORD_0_SPEC>;
1770#[doc = "same as type2_compare_0_word_0"]
1771pub mod type2_compare_9_word_0;
1772#[doc = "TYPE2_COMPARE_9_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_9_WORD_1_SPEC>`"]
1773pub type TYPE2_COMPARE_9_WORD_1 = crate::Reg<type2_compare_9_word_1::TYPE2_COMPARE_9_WORD_1_SPEC>;
1774#[doc = "same as type2_compare_0_word_1"]
1775pub mod type2_compare_9_word_1;
1776#[doc = "TYPE2_COMPARE_10_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_10_WORD_0_SPEC>`"]
1777pub type TYPE2_COMPARE_10_WORD_0 =
1778 crate::Reg<type2_compare_10_word_0::TYPE2_COMPARE_10_WORD_0_SPEC>;
1779#[doc = "same as type2_compare_0_word_0"]
1780pub mod type2_compare_10_word_0;
1781#[doc = "TYPE2_COMPARE_10_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_10_WORD_1_SPEC>`"]
1782pub type TYPE2_COMPARE_10_WORD_1 =
1783 crate::Reg<type2_compare_10_word_1::TYPE2_COMPARE_10_WORD_1_SPEC>;
1784#[doc = "same as type2_compare_0_word_1"]
1785pub mod type2_compare_10_word_1;
1786#[doc = "TYPE2_COMPARE_11_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_11_WORD_0_SPEC>`"]
1787pub type TYPE2_COMPARE_11_WORD_0 =
1788 crate::Reg<type2_compare_11_word_0::TYPE2_COMPARE_11_WORD_0_SPEC>;
1789#[doc = "same as type2_compare_0_word_0"]
1790pub mod type2_compare_11_word_0;
1791#[doc = "TYPE2_COMPARE_11_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_11_WORD_1_SPEC>`"]
1792pub type TYPE2_COMPARE_11_WORD_1 =
1793 crate::Reg<type2_compare_11_word_1::TYPE2_COMPARE_11_WORD_1_SPEC>;
1794#[doc = "same as type2_compare_0_word_1"]
1795pub mod type2_compare_11_word_1;
1796#[doc = "TYPE2_COMPARE_12_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_12_WORD_0_SPEC>`"]
1797pub type TYPE2_COMPARE_12_WORD_0 =
1798 crate::Reg<type2_compare_12_word_0::TYPE2_COMPARE_12_WORD_0_SPEC>;
1799#[doc = "same as type2_compare_0_word_0"]
1800pub mod type2_compare_12_word_0;
1801#[doc = "TYPE2_COMPARE_12_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_12_WORD_1_SPEC>`"]
1802pub type TYPE2_COMPARE_12_WORD_1 =
1803 crate::Reg<type2_compare_12_word_1::TYPE2_COMPARE_12_WORD_1_SPEC>;
1804#[doc = "same as type2_compare_0_word_1"]
1805pub mod type2_compare_12_word_1;
1806#[doc = "TYPE2_COMPARE_13_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_13_WORD_0_SPEC>`"]
1807pub type TYPE2_COMPARE_13_WORD_0 =
1808 crate::Reg<type2_compare_13_word_0::TYPE2_COMPARE_13_WORD_0_SPEC>;
1809#[doc = "same as type2_compare_0_word_0"]
1810pub mod type2_compare_13_word_0;
1811#[doc = "TYPE2_COMPARE_13_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_13_WORD_1_SPEC>`"]
1812pub type TYPE2_COMPARE_13_WORD_1 =
1813 crate::Reg<type2_compare_13_word_1::TYPE2_COMPARE_13_WORD_1_SPEC>;
1814#[doc = "same as type2_compare_0_word_1"]
1815pub mod type2_compare_13_word_1;
1816#[doc = "TYPE2_COMPARE_14_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_14_WORD_0_SPEC>`"]
1817pub type TYPE2_COMPARE_14_WORD_0 =
1818 crate::Reg<type2_compare_14_word_0::TYPE2_COMPARE_14_WORD_0_SPEC>;
1819#[doc = "same as type2_compare_0_word_0"]
1820pub mod type2_compare_14_word_0;
1821#[doc = "TYPE2_COMPARE_14_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_14_WORD_1_SPEC>`"]
1822pub type TYPE2_COMPARE_14_WORD_1 =
1823 crate::Reg<type2_compare_14_word_1::TYPE2_COMPARE_14_WORD_1_SPEC>;
1824#[doc = "same as type2_compare_0_word_1"]
1825pub mod type2_compare_14_word_1;
1826#[doc = "TYPE2_COMPARE_15_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_15_WORD_0_SPEC>`"]
1827pub type TYPE2_COMPARE_15_WORD_0 =
1828 crate::Reg<type2_compare_15_word_0::TYPE2_COMPARE_15_WORD_0_SPEC>;
1829#[doc = "same as type2_compare_0_word_0"]
1830pub mod type2_compare_15_word_0;
1831#[doc = "TYPE2_COMPARE_15_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_15_WORD_1_SPEC>`"]
1832pub type TYPE2_COMPARE_15_WORD_1 =
1833 crate::Reg<type2_compare_15_word_1::TYPE2_COMPARE_15_WORD_1_SPEC>;
1834#[doc = "same as type2_compare_0_word_1"]
1835pub mod type2_compare_15_word_1;
1836#[doc = "TYPE2_COMPARE_16_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_16_WORD_0_SPEC>`"]
1837pub type TYPE2_COMPARE_16_WORD_0 =
1838 crate::Reg<type2_compare_16_word_0::TYPE2_COMPARE_16_WORD_0_SPEC>;
1839#[doc = "same as type2_compare_0_word_0"]
1840pub mod type2_compare_16_word_0;
1841#[doc = "TYPE2_COMPARE_16_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_16_WORD_1_SPEC>`"]
1842pub type TYPE2_COMPARE_16_WORD_1 =
1843 crate::Reg<type2_compare_16_word_1::TYPE2_COMPARE_16_WORD_1_SPEC>;
1844#[doc = "same as type2_compare_0_word_1"]
1845pub mod type2_compare_16_word_1;
1846#[doc = "TYPE2_COMPARE_17_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_17_WORD_0_SPEC>`"]
1847pub type TYPE2_COMPARE_17_WORD_0 =
1848 crate::Reg<type2_compare_17_word_0::TYPE2_COMPARE_17_WORD_0_SPEC>;
1849#[doc = "same as type2_compare_0_word_0"]
1850pub mod type2_compare_17_word_0;
1851#[doc = "TYPE2_COMPARE_17_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_17_WORD_1_SPEC>`"]
1852pub type TYPE2_COMPARE_17_WORD_1 =
1853 crate::Reg<type2_compare_17_word_1::TYPE2_COMPARE_17_WORD_1_SPEC>;
1854#[doc = "same as type2_compare_0_word_1"]
1855pub mod type2_compare_17_word_1;
1856#[doc = "TYPE2_COMPARE_18_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_18_WORD_0_SPEC>`"]
1857pub type TYPE2_COMPARE_18_WORD_0 =
1858 crate::Reg<type2_compare_18_word_0::TYPE2_COMPARE_18_WORD_0_SPEC>;
1859#[doc = "same as type2_compare_0_word_0"]
1860pub mod type2_compare_18_word_0;
1861#[doc = "TYPE2_COMPARE_18_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_18_WORD_1_SPEC>`"]
1862pub type TYPE2_COMPARE_18_WORD_1 =
1863 crate::Reg<type2_compare_18_word_1::TYPE2_COMPARE_18_WORD_1_SPEC>;
1864#[doc = "same as type2_compare_0_word_1"]
1865pub mod type2_compare_18_word_1;
1866#[doc = "TYPE2_COMPARE_19_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_19_WORD_0_SPEC>`"]
1867pub type TYPE2_COMPARE_19_WORD_0 =
1868 crate::Reg<type2_compare_19_word_0::TYPE2_COMPARE_19_WORD_0_SPEC>;
1869#[doc = "same as type2_compare_0_word_0"]
1870pub mod type2_compare_19_word_0;
1871#[doc = "TYPE2_COMPARE_19_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_19_WORD_1_SPEC>`"]
1872pub type TYPE2_COMPARE_19_WORD_1 =
1873 crate::Reg<type2_compare_19_word_1::TYPE2_COMPARE_19_WORD_1_SPEC>;
1874#[doc = "same as type2_compare_0_word_1"]
1875pub mod type2_compare_19_word_1;
1876#[doc = "TYPE2_COMPARE_20_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_20_WORD_0_SPEC>`"]
1877pub type TYPE2_COMPARE_20_WORD_0 =
1878 crate::Reg<type2_compare_20_word_0::TYPE2_COMPARE_20_WORD_0_SPEC>;
1879#[doc = "same as type2_compare_0_word_0"]
1880pub mod type2_compare_20_word_0;
1881#[doc = "TYPE2_COMPARE_20_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_20_WORD_1_SPEC>`"]
1882pub type TYPE2_COMPARE_20_WORD_1 =
1883 crate::Reg<type2_compare_20_word_1::TYPE2_COMPARE_20_WORD_1_SPEC>;
1884#[doc = "same as type2_compare_0_word_1"]
1885pub mod type2_compare_20_word_1;
1886#[doc = "TYPE2_COMPARE_21_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_21_WORD_0_SPEC>`"]
1887pub type TYPE2_COMPARE_21_WORD_0 =
1888 crate::Reg<type2_compare_21_word_0::TYPE2_COMPARE_21_WORD_0_SPEC>;
1889#[doc = "same as type2_compare_0_word_0"]
1890pub mod type2_compare_21_word_0;
1891#[doc = "TYPE2_COMPARE_21_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_21_WORD_1_SPEC>`"]
1892pub type TYPE2_COMPARE_21_WORD_1 =
1893 crate::Reg<type2_compare_21_word_1::TYPE2_COMPARE_21_WORD_1_SPEC>;
1894#[doc = "same as type2_compare_0_word_1"]
1895pub mod type2_compare_21_word_1;
1896#[doc = "TYPE2_COMPARE_22_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_22_WORD_0_SPEC>`"]
1897pub type TYPE2_COMPARE_22_WORD_0 =
1898 crate::Reg<type2_compare_22_word_0::TYPE2_COMPARE_22_WORD_0_SPEC>;
1899#[doc = "same as type2_compare_0_word_0"]
1900pub mod type2_compare_22_word_0;
1901#[doc = "TYPE2_COMPARE_22_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_22_WORD_1_SPEC>`"]
1902pub type TYPE2_COMPARE_22_WORD_1 =
1903 crate::Reg<type2_compare_22_word_1::TYPE2_COMPARE_22_WORD_1_SPEC>;
1904#[doc = "same as type2_compare_0_word_1"]
1905pub mod type2_compare_22_word_1;
1906#[doc = "TYPE2_COMPARE_23_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_23_WORD_0_SPEC>`"]
1907pub type TYPE2_COMPARE_23_WORD_0 =
1908 crate::Reg<type2_compare_23_word_0::TYPE2_COMPARE_23_WORD_0_SPEC>;
1909#[doc = "same as type2_compare_0_word_0"]
1910pub mod type2_compare_23_word_0;
1911#[doc = "TYPE2_COMPARE_23_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_23_WORD_1_SPEC>`"]
1912pub type TYPE2_COMPARE_23_WORD_1 =
1913 crate::Reg<type2_compare_23_word_1::TYPE2_COMPARE_23_WORD_1_SPEC>;
1914#[doc = "same as type2_compare_0_word_1"]
1915pub mod type2_compare_23_word_1;
1916#[doc = "TYPE2_COMPARE_24_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_24_WORD_0_SPEC>`"]
1917pub type TYPE2_COMPARE_24_WORD_0 =
1918 crate::Reg<type2_compare_24_word_0::TYPE2_COMPARE_24_WORD_0_SPEC>;
1919#[doc = "same as type2_compare_0_word_0"]
1920pub mod type2_compare_24_word_0;
1921#[doc = "TYPE2_COMPARE_24_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_24_WORD_1_SPEC>`"]
1922pub type TYPE2_COMPARE_24_WORD_1 =
1923 crate::Reg<type2_compare_24_word_1::TYPE2_COMPARE_24_WORD_1_SPEC>;
1924#[doc = "same as type2_compare_0_word_1"]
1925pub mod type2_compare_24_word_1;
1926#[doc = "TYPE2_COMPARE_25_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_25_WORD_0_SPEC>`"]
1927pub type TYPE2_COMPARE_25_WORD_0 =
1928 crate::Reg<type2_compare_25_word_0::TYPE2_COMPARE_25_WORD_0_SPEC>;
1929#[doc = "same as type2_compare_0_word_0"]
1930pub mod type2_compare_25_word_0;
1931#[doc = "TYPE2_COMPARE_25_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_25_WORD_1_SPEC>`"]
1932pub type TYPE2_COMPARE_25_WORD_1 =
1933 crate::Reg<type2_compare_25_word_1::TYPE2_COMPARE_25_WORD_1_SPEC>;
1934#[doc = "same as type2_compare_0_word_1"]
1935pub mod type2_compare_25_word_1;
1936#[doc = "TYPE2_COMPARE_26_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_26_WORD_0_SPEC>`"]
1937pub type TYPE2_COMPARE_26_WORD_0 =
1938 crate::Reg<type2_compare_26_word_0::TYPE2_COMPARE_26_WORD_0_SPEC>;
1939#[doc = "same as type2_compare_0_word_0"]
1940pub mod type2_compare_26_word_0;
1941#[doc = "TYPE2_COMPARE_26_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_26_WORD_1_SPEC>`"]
1942pub type TYPE2_COMPARE_26_WORD_1 =
1943 crate::Reg<type2_compare_26_word_1::TYPE2_COMPARE_26_WORD_1_SPEC>;
1944#[doc = "same as type2_compare_0_word_1"]
1945pub mod type2_compare_26_word_1;
1946#[doc = "TYPE2_COMPARE_27_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_27_WORD_0_SPEC>`"]
1947pub type TYPE2_COMPARE_27_WORD_0 =
1948 crate::Reg<type2_compare_27_word_0::TYPE2_COMPARE_27_WORD_0_SPEC>;
1949#[doc = "same as type2_compare_0_word_0"]
1950pub mod type2_compare_27_word_0;
1951#[doc = "TYPE2_COMPARE_27_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_27_WORD_1_SPEC>`"]
1952pub type TYPE2_COMPARE_27_WORD_1 =
1953 crate::Reg<type2_compare_27_word_1::TYPE2_COMPARE_27_WORD_1_SPEC>;
1954#[doc = "same as type2_compare_0_word_1"]
1955pub mod type2_compare_27_word_1;
1956#[doc = "TYPE2_COMPARE_28_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_28_WORD_0_SPEC>`"]
1957pub type TYPE2_COMPARE_28_WORD_0 =
1958 crate::Reg<type2_compare_28_word_0::TYPE2_COMPARE_28_WORD_0_SPEC>;
1959#[doc = "same as type2_compare_0_word_0"]
1960pub mod type2_compare_28_word_0;
1961#[doc = "TYPE2_COMPARE_28_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_28_WORD_1_SPEC>`"]
1962pub type TYPE2_COMPARE_28_WORD_1 =
1963 crate::Reg<type2_compare_28_word_1::TYPE2_COMPARE_28_WORD_1_SPEC>;
1964#[doc = "same as type2_compare_0_word_1"]
1965pub mod type2_compare_28_word_1;
1966#[doc = "TYPE2_COMPARE_29_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_29_WORD_0_SPEC>`"]
1967pub type TYPE2_COMPARE_29_WORD_0 =
1968 crate::Reg<type2_compare_29_word_0::TYPE2_COMPARE_29_WORD_0_SPEC>;
1969#[doc = "same as type2_compare_0_word_0"]
1970pub mod type2_compare_29_word_0;
1971#[doc = "TYPE2_COMPARE_29_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_29_WORD_1_SPEC>`"]
1972pub type TYPE2_COMPARE_29_WORD_1 =
1973 crate::Reg<type2_compare_29_word_1::TYPE2_COMPARE_29_WORD_1_SPEC>;
1974#[doc = "same as type2_compare_0_word_1"]
1975pub mod type2_compare_29_word_1;
1976#[doc = "TYPE2_COMPARE_30_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_30_WORD_0_SPEC>`"]
1977pub type TYPE2_COMPARE_30_WORD_0 =
1978 crate::Reg<type2_compare_30_word_0::TYPE2_COMPARE_30_WORD_0_SPEC>;
1979#[doc = "same as type2_compare_0_word_0"]
1980pub mod type2_compare_30_word_0;
1981#[doc = "TYPE2_COMPARE_30_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_30_WORD_1_SPEC>`"]
1982pub type TYPE2_COMPARE_30_WORD_1 =
1983 crate::Reg<type2_compare_30_word_1::TYPE2_COMPARE_30_WORD_1_SPEC>;
1984#[doc = "same as type2_compare_0_word_1"]
1985pub mod type2_compare_30_word_1;
1986#[doc = "TYPE2_COMPARE_31_WORD_0 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_31_WORD_0_SPEC>`"]
1987pub type TYPE2_COMPARE_31_WORD_0 =
1988 crate::Reg<type2_compare_31_word_0::TYPE2_COMPARE_31_WORD_0_SPEC>;
1989#[doc = "same as type2_compare_0_word_0"]
1990pub mod type2_compare_31_word_0;
1991#[doc = "TYPE2_COMPARE_31_WORD_1 (rw) register accessor: an alias for `Reg<TYPE2_COMPARE_31_WORD_1_SPEC>`"]
1992pub type TYPE2_COMPARE_31_WORD_1 =
1993 crate::Reg<type2_compare_31_word_1::TYPE2_COMPARE_31_WORD_1_SPEC>;
1994#[doc = "same as type2_compare_0_word_1"]
1995pub mod type2_compare_31_word_1;