RegisterBlock

cyt3bb_a::scb8

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 51 fields
    pub ctrl: CTRL,
    pub status: STATUS,
    pub cmd_resp_ctrl: CMD_RESP_CTRL,
    pub cmd_resp_status: CMD_RESP_STATUS,
    pub spi_ctrl: SPI_CTRL,
    pub spi_status: SPI_STATUS,
    pub spi_tx_ctrl: SPI_TX_CTRL,
    pub spi_rx_ctrl: SPI_RX_CTRL,
    pub uart_ctrl: UART_CTRL,
    pub uart_tx_ctrl: UART_TX_CTRL,
    pub uart_rx_ctrl: UART_RX_CTRL,
    pub uart_rx_status: UART_RX_STATUS,
    pub uart_flow_ctrl: UART_FLOW_CTRL,
    pub i2c_ctrl: I2C_CTRL,
    pub i2c_status: I2C_STATUS,
    pub i2c_m_cmd: I2C_M_CMD,
    pub i2c_s_cmd: I2C_S_CMD,
    pub i2c_cfg: I2C_CFG,
    pub tx_ctrl: TX_CTRL,
    pub tx_fifo_ctrl: TX_FIFO_CTRL,
    pub tx_fifo_status: TX_FIFO_STATUS,
    pub tx_fifo_wr: TX_FIFO_WR,
    pub rx_ctrl: RX_CTRL,
    pub rx_fifo_ctrl: RX_FIFO_CTRL,
    pub rx_fifo_status: RX_FIFO_STATUS,
    pub rx_match: RX_MATCH,
    pub rx_fifo_rd: RX_FIFO_RD,
    pub rx_fifo_rd_silent: RX_FIFO_RD_SILENT,
    pub intr_cause: INTR_CAUSE,
    pub intr_i2c_ec: INTR_I2C_EC,
    pub intr_i2c_ec_mask: INTR_I2C_EC_MASK,
    pub intr_i2c_ec_masked: INTR_I2C_EC_MASKED,
    pub intr_spi_ec: INTR_SPI_EC,
    pub intr_spi_ec_mask: INTR_SPI_EC_MASK,
    pub intr_spi_ec_masked: INTR_SPI_EC_MASKED,
    pub intr_m: INTR_M,
    pub intr_m_set: INTR_M_SET,
    pub intr_m_mask: INTR_M_MASK,
    pub intr_m_masked: INTR_M_MASKED,
    pub intr_s: INTR_S,
    pub intr_s_set: INTR_S_SET,
    pub intr_s_mask: INTR_S_MASK,
    pub intr_s_masked: INTR_S_MASKED,
    pub intr_tx: INTR_TX,
    pub intr_tx_set: INTR_TX_SET,
    pub intr_tx_mask: INTR_TX_MASK,
    pub intr_tx_masked: INTR_TX_MASKED,
    pub intr_rx: INTR_RX,
    pub intr_rx_set: INTR_RX_SET,
    pub intr_rx_mask: INTR_RX_MASK,
    pub intr_rx_masked: INTR_RX_MASKED,
    /* private fields */

}
Expand description

Register block

Fields§

§ctrl: CTRL

0x00 - Generic control

§status: STATUS

0x04 - Generic status

§cmd_resp_ctrl: CMD_RESP_CTRL

0x08 - Command/response control

§cmd_resp_status: CMD_RESP_STATUS

0x0c - Command/response status

§spi_ctrl: SPI_CTRL

0x20 - SPI control

§spi_status: SPI_STATUS

0x24 - SPI status

§spi_tx_ctrl: SPI_TX_CTRL

0x28 - SPI transmitter control

§spi_rx_ctrl: SPI_RX_CTRL

0x2c - SPI receiver control

§uart_ctrl: UART_CTRL

0x40 - UART control

§uart_tx_ctrl: UART_TX_CTRL

0x44 - UART transmitter control

§uart_rx_ctrl: UART_RX_CTRL

0x48 - UART receiver control

§uart_rx_status: UART_RX_STATUS

0x4c - UART receiver status

§uart_flow_ctrl: UART_FLOW_CTRL

0x50 - UART flow control

§i2c_ctrl: I2C_CTRL

0x60 - I2C control

§i2c_status: I2C_STATUS

0x64 - I2C status

§i2c_m_cmd: I2C_M_CMD

0x68 - I2C master command

§i2c_s_cmd: I2C_S_CMD

0x6c - I2C slave command

§i2c_cfg: I2C_CFG

0x70 - I2C configuration

§tx_ctrl: TX_CTRL

0x200 - Transmitter control

§tx_fifo_ctrl: TX_FIFO_CTRL

0x204 - Transmitter FIFO control

§tx_fifo_status: TX_FIFO_STATUS

0x208 - Transmitter FIFO status

§tx_fifo_wr: TX_FIFO_WR

0x240 - Transmitter FIFO write

§rx_ctrl: RX_CTRL

0x300 - Receiver control

§rx_fifo_ctrl: RX_FIFO_CTRL

0x304 - Receiver FIFO control

§rx_fifo_status: RX_FIFO_STATUS

0x308 - Receiver FIFO status

§rx_match: RX_MATCH

0x310 - Slave address and mask

§rx_fifo_rd: RX_FIFO_RD

0x340 - Receiver FIFO read

§rx_fifo_rd_silent: RX_FIFO_RD_SILENT

0x344 - Receiver FIFO read silent

§intr_cause: INTR_CAUSE

0xe00 - Active clocked interrupt signal

§intr_i2c_ec: INTR_I2C_EC

0xe80 - Externally clocked I2C interrupt request

§intr_i2c_ec_mask: INTR_I2C_EC_MASK

0xe88 - Externally clocked I2C interrupt mask

§intr_i2c_ec_masked: INTR_I2C_EC_MASKED

0xe8c - Externally clocked I2C interrupt masked

§intr_spi_ec: INTR_SPI_EC

0xec0 - Externally clocked SPI interrupt request

§intr_spi_ec_mask: INTR_SPI_EC_MASK

0xec8 - Externally clocked SPI interrupt mask

§intr_spi_ec_masked: INTR_SPI_EC_MASKED

0xecc - Externally clocked SPI interrupt masked

§intr_m: INTR_M

0xf00 - Master interrupt request

§intr_m_set: INTR_M_SET

0xf04 - Master interrupt set request

§intr_m_mask: INTR_M_MASK

0xf08 - Master interrupt mask

§intr_m_masked: INTR_M_MASKED

0xf0c - Master interrupt masked request

§intr_s: INTR_S

0xf40 - Slave interrupt request

§intr_s_set: INTR_S_SET

0xf44 - Slave interrupt set request

§intr_s_mask: INTR_S_MASK

0xf48 - Slave interrupt mask

§intr_s_masked: INTR_S_MASKED

0xf4c - Slave interrupt masked request

§intr_tx: INTR_TX

0xf80 - Transmitter interrupt request

§intr_tx_set: INTR_TX_SET

0xf84 - Transmitter interrupt set request

§intr_tx_mask: INTR_TX_MASK

0xf88 - Transmitter interrupt mask

§intr_tx_masked: INTR_TX_MASKED

0xf8c - Transmitter interrupt masked request

§intr_rx: INTR_RX

0xfc0 - Receiver interrupt request

§intr_rx_set: INTR_RX_SET

0xfc4 - Receiver interrupt set request

§intr_rx_mask: INTR_RX_MASK

0xfc8 - Receiver interrupt mask

§intr_rx_masked: INTR_RX_MASKED

0xfcc - Receiver interrupt masked request

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