cyt3bb_a/m0/srss/wdt/
lock.rs1#[doc = "Register `LOCK` reader"]
2pub struct R(crate::R<LOCK_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<LOCK_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<LOCK_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<LOCK_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `LOCK` writer"]
17pub struct W(crate::W<LOCK_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<LOCK_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<LOCK_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<LOCK_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `WDT_LOCK` reader - Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings."]
38pub type WDT_LOCK_R = crate::FieldReader<u8, WDT_LOCK_A>;
39#[doc = "Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings.\n\nValue on reset: 3"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum WDT_LOCK_A {
43 #[doc = "0: No effect"]
44 NO_CHG = 0,
45 #[doc = "1: Clears bit 0"]
46 CLR0 = 1,
47 #[doc = "2: Clears bit 1"]
48 CLR1 = 2,
49 #[doc = "3: Sets both bits 0 and 1"]
50 SET01 = 3,
51}
52impl From<WDT_LOCK_A> for u8 {
53 #[inline(always)]
54 fn from(variant: WDT_LOCK_A) -> Self {
55 variant as _
56 }
57}
58impl WDT_LOCK_R {
59 #[doc = "Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> WDT_LOCK_A {
62 match self.bits {
63 0 => WDT_LOCK_A::NO_CHG,
64 1 => WDT_LOCK_A::CLR0,
65 2 => WDT_LOCK_A::CLR1,
66 3 => WDT_LOCK_A::SET01,
67 _ => unreachable!(),
68 }
69 }
70 #[doc = "Checks if the value of the field is `NO_CHG`"]
71 #[inline(always)]
72 pub fn is_no_chg(&self) -> bool {
73 *self == WDT_LOCK_A::NO_CHG
74 }
75 #[doc = "Checks if the value of the field is `CLR0`"]
76 #[inline(always)]
77 pub fn is_clr0(&self) -> bool {
78 *self == WDT_LOCK_A::CLR0
79 }
80 #[doc = "Checks if the value of the field is `CLR1`"]
81 #[inline(always)]
82 pub fn is_clr1(&self) -> bool {
83 *self == WDT_LOCK_A::CLR1
84 }
85 #[doc = "Checks if the value of the field is `SET01`"]
86 #[inline(always)]
87 pub fn is_set01(&self) -> bool {
88 *self == WDT_LOCK_A::SET01
89 }
90}
91#[doc = "Field `WDT_LOCK` writer - Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings."]
92pub type WDT_LOCK_W<'a, const O: u8> =
93 crate::FieldWriterSafe<'a, u32, LOCK_SPEC, u8, WDT_LOCK_A, 2, O>;
94impl<'a, const O: u8> WDT_LOCK_W<'a, O> {
95 #[doc = "No effect"]
96 #[inline(always)]
97 pub fn no_chg(self) -> &'a mut W {
98 self.variant(WDT_LOCK_A::NO_CHG)
99 }
100 #[doc = "Clears bit 0"]
101 #[inline(always)]
102 pub fn clr0(self) -> &'a mut W {
103 self.variant(WDT_LOCK_A::CLR0)
104 }
105 #[doc = "Clears bit 1"]
106 #[inline(always)]
107 pub fn clr1(self) -> &'a mut W {
108 self.variant(WDT_LOCK_A::CLR1)
109 }
110 #[doc = "Sets both bits 0 and 1"]
111 #[inline(always)]
112 pub fn set01(self) -> &'a mut W {
113 self.variant(WDT_LOCK_A::SET01)
114 }
115}
116impl R {
117 #[doc = "Bits 0:1 - Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings."]
118 #[inline(always)]
119 pub fn wdt_lock(&self) -> WDT_LOCK_R {
120 WDT_LOCK_R::new((self.bits & 3) as u8)
121 }
122}
123impl W {
124 #[doc = "Bits 0:1 - Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings."]
125 #[inline(always)]
126 #[must_use]
127 pub fn wdt_lock(&mut self) -> WDT_LOCK_W<0> {
128 WDT_LOCK_W::new(self)
129 }
130 #[doc = "Writes raw bits to the register."]
131 #[inline(always)]
132 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133 self.0.bits(bits);
134 self
135 }
136}
137#[doc = "WDT Lock register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"]
138pub struct LOCK_SPEC;
139impl crate::RegisterSpec for LOCK_SPEC {
140 type Ux = u32;
141}
142#[doc = "`read()` method returns [lock::R](R) reader structure"]
143impl crate::Readable for LOCK_SPEC {
144 type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"]
147impl crate::Writable for LOCK_SPEC {
148 type Writer = W;
149 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets LOCK to value 0x03"]
153impl crate::Resettable for LOCK_SPEC {
154 const RESET_VALUE: Self::Ux = 0x03;
155}