cyt3bb_a/m0/srss/wdt/
ctl.rs

1#[doc = "Register `CTL` reader"]
2pub struct R(crate::R<CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTL` writer"]
17pub struct W(crate::W<CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENABLED` reader - Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles."]
38pub type ENABLED_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` reader - Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE&lt;>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up)"]
40pub type ENABLE_R = crate::BitReader<bool>;
41#[doc = "Field `ENABLE` writer - Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE&lt;>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up)"]
42pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
43impl R {
44    #[doc = "Bit 0 - Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles."]
45    #[inline(always)]
46    pub fn enabled(&self) -> ENABLED_R {
47        ENABLED_R::new((self.bits & 1) != 0)
48    }
49    #[doc = "Bit 31 - Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE&lt;>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up)"]
50    #[inline(always)]
51    pub fn enable(&self) -> ENABLE_R {
52        ENABLE_R::new(((self.bits >> 31) & 1) != 0)
53    }
54}
55impl W {
56    #[doc = "Bit 31 - Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE&lt;>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. 0: Counter is disabled (not clocked). 1: Counter is enabled (counting up)"]
57    #[inline(always)]
58    #[must_use]
59    pub fn enable(&mut self) -> ENABLE_W<31> {
60        ENABLE_W::new(self)
61    }
62    #[doc = "Writes raw bits to the register."]
63    #[inline(always)]
64    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
65        self.0.bits(bits);
66        self
67    }
68}
69#[doc = "WDT Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
70pub struct CTL_SPEC;
71impl crate::RegisterSpec for CTL_SPEC {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [ctl::R](R) reader structure"]
75impl crate::Readable for CTL_SPEC {
76    type Reader = R;
77}
78#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
79impl crate::Writable for CTL_SPEC {
80    type Writer = W;
81    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
82    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
83}
84#[doc = "`reset()` method sets CTL to value 0x8000_0001"]
85impl crate::Resettable for CTL_SPEC {
86    const RESET_VALUE: Self::Ux = 0x8000_0001;
87}
cyt3bb_a/m0/srss/wdt/ctl.rs

cyt3bb_a/m0/srss/wdt/
ctl.rs
