cyt3bb_a/m0/srss/csv_lf/csv/
ref_ctl.rs

1#[doc = "Register `REF_CTL` reader"]
2pub struct R(crate::R<REF_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<REF_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<REF_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<REF_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `REF_CTL` writer"]
17pub struct W(crate::W<REF_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<REF_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<REF_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<REF_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STARTUP` reader - Startup delay time -1 (in reference clock cycles), after DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added."]
38pub type STARTUP_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `STARTUP` writer - Startup delay time -1 (in reference clock cycles), after DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added."]
40pub type STARTUP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REF_CTL_SPEC, u8, u8, 8, O>;
41#[doc = "Field `CSV_EN` reader - Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset."]
42pub type CSV_EN_R = crate::BitReader<bool>;
43#[doc = "Field `CSV_EN` writer - Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset."]
44pub type CSV_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, REF_CTL_SPEC, bool, O>;
45impl R {
46    #[doc = "Bits 0:7 - Startup delay time -1 (in reference clock cycles), after DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added."]
47    #[inline(always)]
48    pub fn startup(&self) -> STARTUP_R {
49        STARTUP_R::new((self.bits & 0xff) as u8)
50    }
51    #[doc = "Bit 31 - Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset."]
52    #[inline(always)]
53    pub fn csv_en(&self) -> CSV_EN_R {
54        CSV_EN_R::new(((self.bits >> 31) & 1) != 0)
55    }
56}
57impl W {
58    #[doc = "Bits 0:7 - Startup delay time -1 (in reference clock cycles), after DeepSleep wakeup, from reference clock start to monitored clock start. At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added."]
59    #[inline(always)]
60    #[must_use]
61    pub fn startup(&mut self) -> STARTUP_W<0> {
62        STARTUP_W::new(self)
63    }
64    #[doc = "Bit 31 - Enables clock supervision, both frequency and loss. CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. A CSV error detection is reported to the Fault structure, or instead it can generate a power reset."]
65    #[inline(always)]
66    #[must_use]
67    pub fn csv_en(&mut self) -> CSV_EN_W<31> {
68        CSV_EN_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "Clock Supervision Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ref_ctl](index.html) module"]
78pub struct REF_CTL_SPEC;
79impl crate::RegisterSpec for REF_CTL_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [ref_ctl::R](R) reader structure"]
83impl crate::Readable for REF_CTL_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [ref_ctl::W](W) writer structure"]
87impl crate::Writable for REF_CTL_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets REF_CTL to value 0"]
93impl crate::Resettable for REF_CTL_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
cyt3bb_a/m0/srss/csv_lf/csv/ref_ctl.rs

cyt3bb_a/m0/srss/csv_lf/csv/
ref_ctl.rs
