cyt3bb_a/m0/srss/
clk_trim_ilo1_ctl.rs

1#[doc = "Register `CLK_TRIM_ILO1_CTL` reader"]
2pub struct R(crate::R<CLK_TRIM_ILO1_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_TRIM_ILO1_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_TRIM_ILO1_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_TRIM_ILO1_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK_TRIM_ILO1_CTL` writer"]
17pub struct W(crate::W<CLK_TRIM_ILO1_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_TRIM_ILO1_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_TRIM_ILO1_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_TRIM_ILO1_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ILO1_FTRIM` reader - ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."]
38pub type ILO1_FTRIM_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `ILO1_FTRIM` writer - ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."]
40pub type ILO1_FTRIM_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, CLK_TRIM_ILO1_CTL_SPEC, u8, u8, 6, O>;
42#[doc = "Field `ILO1_MONTRIM` reader - ILO1 internal monitor trim."]
43pub type ILO1_MONTRIM_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `ILO1_MONTRIM` writer - ILO1 internal monitor trim."]
45pub type ILO1_MONTRIM_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, CLK_TRIM_ILO1_CTL_SPEC, u8, u8, 4, O>;
47impl R {
48    #[doc = "Bits 0:5 - ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."]
49    #[inline(always)]
50    pub fn ilo1_ftrim(&self) -> ILO1_FTRIM_R {
51        ILO1_FTRIM_R::new((self.bits & 0x3f) as u8)
52    }
53    #[doc = "Bits 8:11 - ILO1 internal monitor trim."]
54    #[inline(always)]
55    pub fn ilo1_montrim(&self) -> ILO1_MONTRIM_R {
56        ILO1_MONTRIM_R::new(((self.bits >> 8) & 0x0f) as u8)
57    }
58}
59impl W {
60    #[doc = "Bits 0:5 - ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."]
61    #[inline(always)]
62    #[must_use]
63    pub fn ilo1_ftrim(&mut self) -> ILO1_FTRIM_W<0> {
64        ILO1_FTRIM_W::new(self)
65    }
66    #[doc = "Bits 8:11 - ILO1 internal monitor trim."]
67    #[inline(always)]
68    #[must_use]
69    pub fn ilo1_montrim(&mut self) -> ILO1_MONTRIM_W<8> {
70        ILO1_MONTRIM_W::new(self)
71    }
72    #[doc = "Writes raw bits to the register."]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.0.bits(bits);
76        self
77    }
78}
79#[doc = "ILO1 Trim Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_trim_ilo1_ctl](index.html) module"]
80pub struct CLK_TRIM_ILO1_CTL_SPEC;
81impl crate::RegisterSpec for CLK_TRIM_ILO1_CTL_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [clk_trim_ilo1_ctl::R](R) reader structure"]
85impl crate::Readable for CLK_TRIM_ILO1_CTL_SPEC {
86    type Reader = R;
87}
88#[doc = "`write(|w| ..)` method takes [clk_trim_ilo1_ctl::W](W) writer structure"]
89impl crate::Writable for CLK_TRIM_ILO1_CTL_SPEC {
90    type Writer = W;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93}
94#[doc = "`reset()` method sets CLK_TRIM_ILO1_CTL to value 0x052c"]
95impl crate::Resettable for CLK_TRIM_ILO1_CTL_SPEC {
96    const RESET_VALUE: Self::Ux = 0x052c;
97}
cyt3bb_a/m0/srss/clk_trim_ilo1_ctl.rs

cyt3bb_a/m0/srss/
clk_trim_ilo1_ctl.rs
