cyt3bb_a/m0/smif0/device/
rd_dummy_ctl.rs

1#[doc = "Register `RD_DUMMY_CTL` reader"]
2pub struct R(crate::R<RD_DUMMY_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RD_DUMMY_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RD_DUMMY_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RD_DUMMY_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RD_DUMMY_CTL` writer"]
17pub struct W(crate::W<RD_DUMMY_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RD_DUMMY_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RD_DUMMY_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RD_DUMMY_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIZE5` reader - Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!"]
38pub type SIZE5_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIZE5` writer - Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!"]
40pub type SIZE5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RD_DUMMY_CTL_SPEC, u8, u8, 5, O>;
41#[doc = "Field `PRESENT2` reader - Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) Notes: - If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. - When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=\\[6,7\\]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). - In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. - For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2"]
42pub type PRESENT2_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `PRESENT2` writer - Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) Notes: - If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. - When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=\\[6,7\\]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). - In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. - For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2"]
44pub type PRESENT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RD_DUMMY_CTL_SPEC, u8, u8, 2, O>;
45impl R {
46    #[doc = "Bits 0:4 - Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!"]
47    #[inline(always)]
48    pub fn size5(&self) -> SIZE5_R {
49        SIZE5_R::new((self.bits & 0x1f) as u8)
50    }
51    #[doc = "Bits 30:31 - Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) Notes: - If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. - When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=\\[6,7\\]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). - In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. - For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2"]
52    #[inline(always)]
53    pub fn present2(&self) -> PRESENT2_R {
54        PRESENT2_R::new(((self.bits >> 30) & 3) as u8)
55    }
56}
57impl W {
58    #[doc = "Bits 0:4 - Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!"]
59    #[inline(always)]
60    #[must_use]
61    pub fn size5(&mut self) -> SIZE5_W<0> {
62        SIZE5_W::new(self)
63    }
64    #[doc = "Bits 30:31 - Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) Notes: - If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. - When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=\\[6,7\\]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). - In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. - For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2"]
65    #[inline(always)]
66    #[must_use]
67    pub fn present2(&mut self) -> PRESENT2_W<30> {
68        PRESENT2_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "Read dummy control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rd_dummy_ctl](index.html) module"]
78pub struct RD_DUMMY_CTL_SPEC;
79impl crate::RegisterSpec for RD_DUMMY_CTL_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [rd_dummy_ctl::R](R) reader structure"]
83impl crate::Readable for RD_DUMMY_CTL_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [rd_dummy_ctl::W](W) writer structure"]
87impl crate::Writable for RD_DUMMY_CTL_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets RD_DUMMY_CTL to value 0"]
93impl crate::Resettable for RD_DUMMY_CTL_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
cyt3bb_a/m0/smif0/device/rd_dummy_ctl.rs

cyt3bb_a/m0/smif0/device/
rd_dummy_ctl.rs
