cyt3bb_a/m0/sdhc0/core/
cqcfg.rs1#[doc = "Register `CQCFG` reader"]
2pub struct R(crate::R<CQCFG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CQCFG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CQCFG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CQCFG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CQCFG` writer"]
17pub struct W(crate::W<CQCFG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CQCFG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CQCFG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CQCFG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CQ_EN` reader - Enable command queuing engine (CQE). When CQE is disable, the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit, the software verifies that the eMMC host controller is in idle state and there are no ongoing commands or data transfers. When software wants to exit command queuing mode, it clears all previous tasks (if any) before setting this bit to 0. Values: - 0x1 (CQE_ENABLE): Enable command queuing - 0x0 (CQE_DISABLE): Disable command queuing"]
38pub type CQ_EN_R = crate::BitReader<bool>;
39#[doc = "Field `CQ_EN` writer - Enable command queuing engine (CQE). When CQE is disable, the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit, the software verifies that the eMMC host controller is in idle state and there are no ongoing commands or data transfers. When software wants to exit command queuing mode, it clears all previous tasks (if any) before setting this bit to 0. Values: - 0x1 (CQE_ENABLE): Enable command queuing - 0x0 (CQE_DISABLE): Disable command queuing"]
40pub type CQ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, bool, O>;
41#[doc = "Field `CR_GENERAL_EN` reader - N/A"]
42pub type CR_GENERAL_EN_R = crate::BitReader<bool>;
43#[doc = "Field `CR_GENERAL_EN` writer - N/A"]
44pub type CR_GENERAL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, bool, O>;
45#[doc = "Field `TASK_DESC_SIZE` reader - Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). Values: - 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits"]
46pub type TASK_DESC_SIZE_R = crate::BitReader<bool>;
47#[doc = "Field `TASK_DESC_SIZE` writer - Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). Values: - 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits"]
48pub type TASK_DESC_SIZE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, bool, O>;
49#[doc = "Field `DCMD_EN` reader - This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Values: - 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor"]
50pub type DCMD_EN_R = crate::BitReader<bool>;
51#[doc = "Field `DCMD_EN` writer - This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Values: - 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor"]
52pub type DCMD_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CQCFG_SPEC, bool, O>;
53impl R {
54 #[doc = "Bit 0 - Enable command queuing engine (CQE). When CQE is disable, the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit, the software verifies that the eMMC host controller is in idle state and there are no ongoing commands or data transfers. When software wants to exit command queuing mode, it clears all previous tasks (if any) before setting this bit to 0. Values: - 0x1 (CQE_ENABLE): Enable command queuing - 0x0 (CQE_DISABLE): Disable command queuing"]
55 #[inline(always)]
56 pub fn cq_en(&self) -> CQ_EN_R {
57 CQ_EN_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - N/A"]
60 #[inline(always)]
61 pub fn cr_general_en(&self) -> CR_GENERAL_EN_R {
62 CR_GENERAL_EN_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 8 - Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). Values: - 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits"]
65 #[inline(always)]
66 pub fn task_desc_size(&self) -> TASK_DESC_SIZE_R {
67 TASK_DESC_SIZE_R::new(((self.bits >> 8) & 1) != 0)
68 }
69 #[doc = "Bit 12 - This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Values: - 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor"]
70 #[inline(always)]
71 pub fn dcmd_en(&self) -> DCMD_EN_R {
72 DCMD_EN_R::new(((self.bits >> 12) & 1) != 0)
73 }
74}
75impl W {
76 #[doc = "Bit 0 - Enable command queuing engine (CQE). When CQE is disable, the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit, the software verifies that the eMMC host controller is in idle state and there are no ongoing commands or data transfers. When software wants to exit command queuing mode, it clears all previous tasks (if any) before setting this bit to 0. Values: - 0x1 (CQE_ENABLE): Enable command queuing - 0x0 (CQE_DISABLE): Disable command queuing"]
77 #[inline(always)]
78 #[must_use]
79 pub fn cq_en(&mut self) -> CQ_EN_W<0> {
80 CQ_EN_W::new(self)
81 }
82 #[doc = "Bit 1 - N/A"]
83 #[inline(always)]
84 #[must_use]
85 pub fn cr_general_en(&mut self) -> CR_GENERAL_EN_W<1> {
86 CR_GENERAL_EN_W::new(self)
87 }
88 #[doc = "Bit 8 - Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). Values: - 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits"]
89 #[inline(always)]
90 #[must_use]
91 pub fn task_desc_size(&mut self) -> TASK_DESC_SIZE_W<8> {
92 TASK_DESC_SIZE_W::new(self)
93 }
94 #[doc = "Bit 12 - This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Values: - 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor"]
95 #[inline(always)]
96 #[must_use]
97 pub fn dcmd_en(&mut self) -> DCMD_EN_W<12> {
98 DCMD_EN_W::new(self)
99 }
100 #[doc = "Writes raw bits to the register."]
101 #[inline(always)]
102 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103 self.0.bits(bits);
104 self
105 }
106}
107#[doc = "Command Queuing Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cqcfg](index.html) module"]
108pub struct CQCFG_SPEC;
109impl crate::RegisterSpec for CQCFG_SPEC {
110 type Ux = u32;
111}
112#[doc = "`read()` method returns [cqcfg::R](R) reader structure"]
113impl crate::Readable for CQCFG_SPEC {
114 type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [cqcfg::W](W) writer structure"]
117impl crate::Writable for CQCFG_SPEC {
118 type Writer = W;
119 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets CQCFG to value 0"]
123impl crate::Resettable for CQCFG_SPEC {
124 const RESET_VALUE: Self::Ux = 0;
125}