1#[doc = "Register `UART_RX_CTRL` reader"]
2pub struct R(crate::R<UART_RX_CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<UART_RX_CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<UART_RX_CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<UART_RX_CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `UART_RX_CTRL` writer"]
17pub struct W(crate::W<UART_RX_CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<UART_RX_CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<UART_RX_CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<UART_RX_CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `STOP_BITS` reader - Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in \\[2, 7\\], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. This limitation is due to possible transmitter and receiver clock skew that prevents the design from doing reliable stop bit detection for short (1 bit period) stop bit sequences. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value."]
38pub type STOP_BITS_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `STOP_BITS` writer - Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in \\[2, 7\\], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. This limitation is due to possible transmitter and receiver clock skew that prevents the design from doing reliable stop bit detection for short (1 bit period) stop bit sequences. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value."]
40pub type STOP_BITS_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, UART_RX_CTRL_SPEC, u8, u8, 3, O>;
42#[doc = "Field `PARITY` reader - Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes."]
43pub type PARITY_R = crate::BitReader<bool>;
44#[doc = "Field `PARITY` writer - Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes."]
45pub type PARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
46#[doc = "Field `PARITY_ENABLED` reader - Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware."]
47pub type PARITY_ENABLED_R = crate::BitReader<bool>;
48#[doc = "Field `PARITY_ENABLED` writer - Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware."]
49pub type PARITY_ENABLED_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
50#[doc = "Field `POLARITY` reader - Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality."]
51pub type POLARITY_R = crate::BitReader<bool>;
52#[doc = "Field `POLARITY` writer - Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality."]
53pub type POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
54#[doc = "Field `DROP_ON_PARITY_ERROR` reader - Behavior when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field)."]
55pub type DROP_ON_PARITY_ERROR_R = crate::BitReader<bool>;
56#[doc = "Field `DROP_ON_PARITY_ERROR` writer - Behavior when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field)."]
57pub type DROP_ON_PARITY_ERROR_W<'a, const O: u8> =
58 crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
59#[doc = "Field `DROP_ON_FRAME_ERROR` reader - Behavior when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost."]
60pub type DROP_ON_FRAME_ERROR_R = crate::BitReader<bool>;
61#[doc = "Field `DROP_ON_FRAME_ERROR` writer - Behavior when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost."]
62pub type DROP_ON_FRAME_ERROR_W<'a, const O: u8> =
63 crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
64#[doc = "Field `MP_MODE` reader - Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped."]
65pub type MP_MODE_R = crate::BitReader<bool>;
66#[doc = "Field `MP_MODE` writer - Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped."]
67pub type MP_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
68#[doc = "Field `LIN_MODE` reader - Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
69pub type LIN_MODE_R = crate::BitReader<bool>;
70#[doc = "Field `LIN_MODE` writer - Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
71pub type LIN_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
72#[doc = "Field `SKIP_START` reader - Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit."]
73pub type SKIP_START_R = crate::BitReader<bool>;
74#[doc = "Field `SKIP_START` writer - Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit."]
75pub type SKIP_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
76#[doc = "Field `BREAK_WIDTH` reader - Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value."]
77pub type BREAK_WIDTH_R = crate::FieldReader<u8, u8>;
78#[doc = "Field `BREAK_WIDTH` writer - Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value."]
79pub type BREAK_WIDTH_W<'a, const O: u8> =
80 crate::FieldWriter<'a, u32, UART_RX_CTRL_SPEC, u8, u8, 4, O>;
81#[doc = "Field `BREAK_LEVEL` reader - 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART"]
82pub type BREAK_LEVEL_R = crate::BitReader<bool>;
83#[doc = "Field `BREAK_LEVEL` writer - 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART"]
84pub type BREAK_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_RX_CTRL_SPEC, bool, O>;
85impl R {
86 #[doc = "Bits 0:2 - Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in \\[2, 7\\], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. This limitation is due to possible transmitter and receiver clock skew that prevents the design from doing reliable stop bit detection for short (1 bit period) stop bit sequences. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value."]
87 #[inline(always)]
88 pub fn stop_bits(&self) -> STOP_BITS_R {
89 STOP_BITS_R::new((self.bits & 7) as u8)
90 }
91 #[doc = "Bit 4 - Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes."]
92 #[inline(always)]
93 pub fn parity(&self) -> PARITY_R {
94 PARITY_R::new(((self.bits >> 4) & 1) != 0)
95 }
96 #[doc = "Bit 5 - Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware."]
97 #[inline(always)]
98 pub fn parity_enabled(&self) -> PARITY_ENABLED_R {
99 PARITY_ENABLED_R::new(((self.bits >> 5) & 1) != 0)
100 }
101 #[doc = "Bit 6 - Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality."]
102 #[inline(always)]
103 pub fn polarity(&self) -> POLARITY_R {
104 POLARITY_R::new(((self.bits >> 6) & 1) != 0)
105 }
106 #[doc = "Bit 8 - Behavior when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field)."]
107 #[inline(always)]
108 pub fn drop_on_parity_error(&self) -> DROP_ON_PARITY_ERROR_R {
109 DROP_ON_PARITY_ERROR_R::new(((self.bits >> 8) & 1) != 0)
110 }
111 #[doc = "Bit 9 - Behavior when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost."]
112 #[inline(always)]
113 pub fn drop_on_frame_error(&self) -> DROP_ON_FRAME_ERROR_R {
114 DROP_ON_FRAME_ERROR_R::new(((self.bits >> 9) & 1) != 0)
115 }
116 #[doc = "Bit 10 - Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped."]
117 #[inline(always)]
118 pub fn mp_mode(&self) -> MP_MODE_R {
119 MP_MODE_R::new(((self.bits >> 10) & 1) != 0)
120 }
121 #[doc = "Bit 12 - Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
122 #[inline(always)]
123 pub fn lin_mode(&self) -> LIN_MODE_R {
124 LIN_MODE_R::new(((self.bits >> 12) & 1) != 0)
125 }
126 #[doc = "Bit 13 - Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit."]
127 #[inline(always)]
128 pub fn skip_start(&self) -> SKIP_START_R {
129 SKIP_START_R::new(((self.bits >> 13) & 1) != 0)
130 }
131 #[doc = "Bits 16:19 - Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value."]
132 #[inline(always)]
133 pub fn break_width(&self) -> BREAK_WIDTH_R {
134 BREAK_WIDTH_R::new(((self.bits >> 16) & 0x0f) as u8)
135 }
136 #[doc = "Bit 24 - 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART"]
137 #[inline(always)]
138 pub fn break_level(&self) -> BREAK_LEVEL_R {
139 BREAK_LEVEL_R::new(((self.bits >> 24) & 1) != 0)
140 }
141}
142impl W {
143 #[doc = "Bits 0:2 - Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is \\[1, 7\\]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in \\[2, 7\\], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. This limitation is due to possible transmitter and receiver clock skew that prevents the design from doing reliable stop bit detection for short (1 bit period) stop bit sequences. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value."]
144 #[inline(always)]
145 #[must_use]
146 pub fn stop_bits(&mut self) -> STOP_BITS_W<0> {
147 STOP_BITS_W::new(self)
148 }
149 #[doc = "Bit 4 - Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes."]
150 #[inline(always)]
151 #[must_use]
152 pub fn parity(&mut self) -> PARITY_W<4> {
153 PARITY_W::new(self)
154 }
155 #[doc = "Bit 5 - Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware."]
156 #[inline(always)]
157 #[must_use]
158 pub fn parity_enabled(&mut self) -> PARITY_ENABLED_W<5> {
159 PARITY_ENABLED_W::new(self)
160 }
161 #[doc = "Bit 6 - Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality."]
162 #[inline(always)]
163 #[must_use]
164 pub fn polarity(&mut self) -> POLARITY_W<6> {
165 POLARITY_W::new(self)
166 }
167 #[doc = "Bit 8 - Behavior when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field)."]
168 #[inline(always)]
169 #[must_use]
170 pub fn drop_on_parity_error(&mut self) -> DROP_ON_PARITY_ERROR_W<8> {
171 DROP_ON_PARITY_ERROR_W::new(self)
172 }
173 #[doc = "Bit 9 - Behavior when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost."]
174 #[inline(always)]
175 #[must_use]
176 pub fn drop_on_frame_error(&mut self) -> DROP_ON_FRAME_ERROR_W<9> {
177 DROP_ON_FRAME_ERROR_W::new(self)
178 }
179 #[doc = "Bit 10 - Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped."]
180 #[inline(always)]
181 #[must_use]
182 pub fn mp_mode(&mut self) -> MP_MODE_W<10> {
183 MP_MODE_W::new(self)
184 }
185 #[doc = "Bit 12 - Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte."]
186 #[inline(always)]
187 #[must_use]
188 pub fn lin_mode(&mut self) -> LIN_MODE_W<12> {
189 LIN_MODE_W::new(self)
190 }
191 #[doc = "Bit 13 - Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit."]
192 #[inline(always)]
193 #[must_use]
194 pub fn skip_start(&mut self) -> SKIP_START_W<13> {
195 SKIP_START_W::new(self)
196 }
197 #[doc = "Bits 16:19 - Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value."]
198 #[inline(always)]
199 #[must_use]
200 pub fn break_width(&mut self) -> BREAK_WIDTH_W<16> {
201 BREAK_WIDTH_W::new(self)
202 }
203 #[doc = "Bit 24 - 0: low level pulse detection, like Break field in LIN protocol 1: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART"]
204 #[inline(always)]
205 #[must_use]
206 pub fn break_level(&mut self) -> BREAK_LEVEL_W<24> {
207 BREAK_LEVEL_W::new(self)
208 }
209 #[doc = "Writes raw bits to the register."]
210 #[inline(always)]
211 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
212 self.0.bits(bits);
213 self
214 }
215}
216#[doc = "UART receiver control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_rx_ctrl](index.html) module"]
217pub struct UART_RX_CTRL_SPEC;
218impl crate::RegisterSpec for UART_RX_CTRL_SPEC {
219 type Ux = u32;
220}
221#[doc = "`read()` method returns [uart_rx_ctrl::R](R) reader structure"]
222impl crate::Readable for UART_RX_CTRL_SPEC {
223 type Reader = R;
224}
225#[doc = "`write(|w| ..)` method takes [uart_rx_ctrl::W](W) writer structure"]
226impl crate::Writable for UART_RX_CTRL_SPEC {
227 type Writer = W;
228 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
229 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
230}
231#[doc = "`reset()` method sets UART_RX_CTRL to value 0x000a_0002"]
232impl crate::Resettable for UART_RX_CTRL_SPEC {
233 const RESET_VALUE: Self::Ux = 0x000a_0002;
234}