cyt3bb_a/m0/scb0/
rx_match.rs

1#[doc = "Register `RX_MATCH` reader"]
2pub struct R(crate::R<RX_MATCH_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RX_MATCH_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RX_MATCH_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RX_MATCH_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RX_MATCH` writer"]
17pub struct W(crate::W<RX_MATCH_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RX_MATCH_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RX_MATCH_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RX_MATCH_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADDR` reader - Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read)."]
38pub type ADDR_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `ADDR` writer - Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read)."]
40pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RX_MATCH_SPEC, u8, u8, 8, O>;
41#[doc = "Field `MASK` reader - Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK))."]
42pub type MASK_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `MASK` writer - Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK))."]
44pub type MASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RX_MATCH_SPEC, u8, u8, 8, O>;
45impl R {
46    #[doc = "Bits 0:7 - Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read)."]
47    #[inline(always)]
48    pub fn addr(&self) -> ADDR_R {
49        ADDR_R::new((self.bits & 0xff) as u8)
50    }
51    #[doc = "Bits 16:23 - Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK))."]
52    #[inline(always)]
53    pub fn mask(&self) -> MASK_R {
54        MASK_R::new(((self.bits >> 16) & 0xff) as u8)
55    }
56}
57impl W {
58    #[doc = "Bits 0:7 - Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read)."]
59    #[inline(always)]
60    #[must_use]
61    pub fn addr(&mut self) -> ADDR_W<0> {
62        ADDR_W::new(self)
63    }
64    #[doc = "Bits 16:23 - Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK))."]
65    #[inline(always)]
66    #[must_use]
67    pub fn mask(&mut self) -> MASK_W<16> {
68        MASK_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "Slave address and mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_match](index.html) module"]
78pub struct RX_MATCH_SPEC;
79impl crate::RegisterSpec for RX_MATCH_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [rx_match::R](R) reader structure"]
83impl crate::Readable for RX_MATCH_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [rx_match::W](W) writer structure"]
87impl crate::Writable for RX_MATCH_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets RX_MATCH to value 0"]
93impl crate::Resettable for RX_MATCH_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
cyt3bb_a/m0/scb0/rx_match.rs

cyt3bb_a/m0/scb0/
rx_match.rs
