cyt3bb_a/m0/scb0/
i2c_status.rs

1#[doc = "Register `I2C_STATUS` reader"]
2pub struct R(crate::R<I2C_STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<I2C_STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<I2C_STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<I2C_STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `BUS_BUSY` reader - I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions)."]
17pub type BUS_BUSY_R = crate::BitReader<bool>;
18#[doc = "Field `I2C_EC_BUSY` reader - Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable."]
19pub type I2C_EC_BUSY_R = crate::BitReader<bool>;
20#[doc = "Field `I2CS_IC_BUSY` reader - Indicates whether the internally clocked slave logic is being accessed by external I2C master. --set at ADDR_MATCH --clear at START/RESET, STOP detection, or BUS_ERROR This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep."]
21pub type I2CS_IC_BUSY_R = crate::BitReader<bool>;
22#[doc = "Field `S_READ` reader - I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''."]
23pub type S_READ_R = crate::BitReader<bool>;
24#[doc = "Field `M_READ` reader - I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''."]
25pub type M_READ_R = crate::BitReader<bool>;
26#[doc = "Field `CURR_EZ_ADDR` reader - I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design."]
27pub type CURR_EZ_ADDR_R = crate::FieldReader<u8, u8>;
28#[doc = "Field `BASE_EZ_ADDR` reader - I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design."]
29pub type BASE_EZ_ADDR_R = crate::FieldReader<u8, u8>;
30impl R {
31    #[doc = "Bit 0 - I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions)."]
32    #[inline(always)]
33    pub fn bus_busy(&self) -> BUS_BUSY_R {
34        BUS_BUSY_R::new((self.bits & 1) != 0)
35    }
36    #[doc = "Bit 1 - Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable."]
37    #[inline(always)]
38    pub fn i2c_ec_busy(&self) -> I2C_EC_BUSY_R {
39        I2C_EC_BUSY_R::new(((self.bits >> 1) & 1) != 0)
40    }
41    #[doc = "Bit 2 - Indicates whether the internally clocked slave logic is being accessed by external I2C master. --set at ADDR_MATCH --clear at START/RESET, STOP detection, or BUS_ERROR This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep."]
42    #[inline(always)]
43    pub fn i2cs_ic_busy(&self) -> I2CS_IC_BUSY_R {
44        I2CS_IC_BUSY_R::new(((self.bits >> 2) & 1) != 0)
45    }
46    #[doc = "Bit 4 - I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''."]
47    #[inline(always)]
48    pub fn s_read(&self) -> S_READ_R {
49        S_READ_R::new(((self.bits >> 4) & 1) != 0)
50    }
51    #[doc = "Bit 5 - I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''."]
52    #[inline(always)]
53    pub fn m_read(&self) -> M_READ_R {
54        M_READ_R::new(((self.bits >> 5) & 1) != 0)
55    }
56    #[doc = "Bits 8:15 - I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design."]
57    #[inline(always)]
58    pub fn curr_ez_addr(&self) -> CURR_EZ_ADDR_R {
59        CURR_EZ_ADDR_R::new(((self.bits >> 8) & 0xff) as u8)
60    }
61    #[doc = "Bits 16:23 - I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design."]
62    #[inline(always)]
63    pub fn base_ez_addr(&self) -> BASE_EZ_ADDR_R {
64        BASE_EZ_ADDR_R::new(((self.bits >> 16) & 0xff) as u8)
65    }
66}
67#[doc = "I2C status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2c_status](index.html) module"]
68pub struct I2C_STATUS_SPEC;
69impl crate::RegisterSpec for I2C_STATUS_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [i2c_status::R](R) reader structure"]
73impl crate::Readable for I2C_STATUS_SPEC {
74    type Reader = R;
75}
76#[doc = "`reset()` method sets I2C_STATUS to value 0"]
77impl crate::Resettable for I2C_STATUS_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
cyt3bb_a/m0/scb0/i2c_status.rs

cyt3bb_a/m0/scb0/
i2c_status.rs
