cyt3bb_a/m0/peri_pclk/gr/
div_cmd.rs1#[doc = "Register `DIV_CMD` reader"]
2pub struct R(crate::R<DIV_CMD_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DIV_CMD_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DIV_CMD_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DIV_CMD_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DIV_CMD` writer"]
17pub struct W(crate::W<DIV_CMD_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DIV_CMD_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DIV_CMD_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DIV_CMD_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DIV_SEL` reader - (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated."]
38pub type DIV_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DIV_SEL` writer - (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated."]
40pub type DIV_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_CMD_SPEC, u8, u8, 8, O>;
41#[doc = "Field `TYPE_SEL` reader - Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
42pub type TYPE_SEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `TYPE_SEL` writer - Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
44pub type TYPE_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_CMD_SPEC, u8, u8, 2, O>;
45#[doc = "Field `PA_DIV_SEL` reader - (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root\\[i\\]' is used as reference."]
46pub type PA_DIV_SEL_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `PA_DIV_SEL` writer - (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root\\[i\\]' is used as reference."]
48pub type PA_DIV_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_CMD_SPEC, u8, u8, 8, O>;
49#[doc = "Field `PA_TYPE_SEL` reader - Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
50pub type PA_TYPE_SEL_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `PA_TYPE_SEL` writer - Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
52pub type PA_TYPE_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_CMD_SPEC, u8, u8, 2, O>;
53#[doc = "Field `DISABLE` reader - Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately."]
54pub type DISABLE_R = crate::BitReader<bool>;
55#[doc = "Field `DISABLE` writer - Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately."]
56pub type DISABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIV_CMD_SPEC, bool, O>;
57#[doc = "Field `ENABLE` reader - Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root\\[i\\]' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root\\[i\\]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root\\[i\\]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process."]
58pub type ENABLE_R = crate::BitReader<bool>;
59#[doc = "Field `ENABLE` writer - Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root\\[i\\]' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root\\[i\\]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root\\[i\\]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process."]
60pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIV_CMD_SPEC, bool, O>;
61impl R {
62 #[doc = "Bits 0:7 - (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated."]
63 #[inline(always)]
64 pub fn div_sel(&self) -> DIV_SEL_R {
65 DIV_SEL_R::new((self.bits & 0xff) as u8)
66 }
67 #[doc = "Bits 8:9 - Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
68 #[inline(always)]
69 pub fn type_sel(&self) -> TYPE_SEL_R {
70 TYPE_SEL_R::new(((self.bits >> 8) & 3) as u8)
71 }
72 #[doc = "Bits 16:23 - (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root\\[i\\]' is used as reference."]
73 #[inline(always)]
74 pub fn pa_div_sel(&self) -> PA_DIV_SEL_R {
75 PA_DIV_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
76 }
77 #[doc = "Bits 24:25 - Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
78 #[inline(always)]
79 pub fn pa_type_sel(&self) -> PA_TYPE_SEL_R {
80 PA_TYPE_SEL_R::new(((self.bits >> 24) & 3) as u8)
81 }
82 #[doc = "Bit 30 - Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately."]
83 #[inline(always)]
84 pub fn disable(&self) -> DISABLE_R {
85 DISABLE_R::new(((self.bits >> 30) & 1) != 0)
86 }
87 #[doc = "Bit 31 - Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root\\[i\\]' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root\\[i\\]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root\\[i\\]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process."]
88 #[inline(always)]
89 pub fn enable(&self) -> ENABLE_R {
90 ENABLE_R::new(((self.bits >> 31) & 1) != 0)
91 }
92}
93impl W {
94 #[doc = "Bits 0:7 - (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated."]
95 #[inline(always)]
96 #[must_use]
97 pub fn div_sel(&mut self) -> DIV_SEL_W<0> {
98 DIV_SEL_W::new(self)
99 }
100 #[doc = "Bits 8:9 - Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
101 #[inline(always)]
102 #[must_use]
103 pub fn type_sel(&mut self) -> TYPE_SEL_W<8> {
104 TYPE_SEL_W::new(self)
105 }
106 #[doc = "Bits 16:23 - (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root\\[i\\]' is used as reference."]
107 #[inline(always)]
108 #[must_use]
109 pub fn pa_div_sel(&mut self) -> PA_DIV_SEL_W<16> {
110 PA_DIV_SEL_W::new(self)
111 }
112 #[doc = "Bits 24:25 - Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers."]
113 #[inline(always)]
114 #[must_use]
115 pub fn pa_type_sel(&mut self) -> PA_TYPE_SEL_W<24> {
116 PA_TYPE_SEL_W::new(self)
117 }
118 #[doc = "Bit 30 - Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately."]
119 #[inline(always)]
120 #[must_use]
121 pub fn disable(&mut self) -> DISABLE_W<30> {
122 DISABLE_W::new(self)
123 }
124 #[doc = "Bit 31 - Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root\\[i\\]' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root\\[i\\]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root\\[i\\]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process."]
125 #[inline(always)]
126 #[must_use]
127 pub fn enable(&mut self) -> ENABLE_W<31> {
128 ENABLE_W::new(self)
129 }
130 #[doc = "Writes raw bits to the register."]
131 #[inline(always)]
132 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133 self.0.bits(bits);
134 self
135 }
136}
137#[doc = "Divider command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div_cmd](index.html) module"]
138pub struct DIV_CMD_SPEC;
139impl crate::RegisterSpec for DIV_CMD_SPEC {
140 type Ux = u32;
141}
142#[doc = "`read()` method returns [div_cmd::R](R) reader structure"]
143impl crate::Readable for DIV_CMD_SPEC {
144 type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [div_cmd::W](W) writer structure"]
147impl crate::Writable for DIV_CMD_SPEC {
148 type Writer = W;
149 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets DIV_CMD to value 0x03ff_03ff"]
153impl crate::Resettable for DIV_CMD_SPEC {
154 const RESET_VALUE: Self::Ux = 0x03ff_03ff;
155}