cyt3bb_a/m0/peri_pclk/gr/
div_8_ctl.rs

1#[doc = "Register `DIV_8_CTL[%s]` reader"]
2pub struct R(crate::R<DIV_8_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIV_8_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIV_8_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIV_8_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIV_8_CTL[%s]` writer"]
17pub struct W(crate::W<DIV_8_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIV_8_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIV_8_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIV_8_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `INT8_DIV` reader - Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to \\[2, 256\\]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range \\[2, 256\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
40pub type INT8_DIV_R = crate::FieldReader<u8, u8>;
41#[doc = "Field `INT8_DIV` writer - Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to \\[2, 256\\]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range \\[2, 256\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
42pub type INT8_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_8_CTL_SPEC, u8, u8, 8, O>;
43impl R {
44    #[doc = "Bit 0 - Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode."]
45    #[inline(always)]
46    pub fn en(&self) -> EN_R {
47        EN_R::new((self.bits & 1) != 0)
48    }
49    #[doc = "Bits 8:15 - Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to \\[2, 256\\]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range \\[2, 256\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
50    #[inline(always)]
51    pub fn int8_div(&self) -> INT8_DIV_R {
52        INT8_DIV_R::new(((self.bits >> 8) & 0xff) as u8)
53    }
54}
55impl W {
56    #[doc = "Bits 8:15 - Integer division by (1+INT8_DIV). Allows for integer divisions in the range \\[1, 256\\]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to \\[2, 256\\]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range \\[2, 256\\]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode."]
57    #[inline(always)]
58    #[must_use]
59    pub fn int8_div(&mut self) -> INT8_DIV_W<8> {
60        INT8_DIV_W::new(self)
61    }
62    #[doc = "Writes raw bits to the register."]
63    #[inline(always)]
64    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
65        self.0.bits(bits);
66        self
67    }
68}
69#[doc = "Divider control (for 8.0 divider)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div_8_ctl](index.html) module"]
70pub struct DIV_8_CTL_SPEC;
71impl crate::RegisterSpec for DIV_8_CTL_SPEC {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [div_8_ctl::R](R) reader structure"]
75impl crate::Readable for DIV_8_CTL_SPEC {
76    type Reader = R;
77}
78#[doc = "`write(|w| ..)` method takes [div_8_ctl::W](W) writer structure"]
79impl crate::Writable for DIV_8_CTL_SPEC {
80    type Writer = W;
81    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
82    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
83}
84#[doc = "`reset()` method sets DIV_8_CTL[%s]
85to value 0"]
86impl crate::Resettable for DIV_8_CTL_SPEC {
87    const RESET_VALUE: Self::Ux = 0;
88}
cyt3bb_a/m0/peri_pclk/gr/div_8_ctl.rs

cyt3bb_a/m0/peri_pclk/gr/
div_8_ctl.rs
