cyt3bb_a/m0/gpio/prt/
out_inv.rs

1#[doc = "Register `OUT_INV` reader"]
2pub struct R(crate::R<OUT_INV_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OUT_INV_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OUT_INV_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OUT_INV_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OUT_INV` writer"]
17pub struct W(crate::W<OUT_INV_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OUT_INV_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OUT_INV_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OUT_INV_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `OUT0` reader - IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0')."]
38pub type OUT0_R = crate::BitReader<bool>;
39#[doc = "Field `OUT0` writer - IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0')."]
40pub type OUT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
41#[doc = "Field `OUT1` reader - IO invert output for pin 1"]
42pub type OUT1_R = crate::BitReader<bool>;
43#[doc = "Field `OUT1` writer - IO invert output for pin 1"]
44pub type OUT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
45#[doc = "Field `OUT2` reader - IO invert output for pin 2"]
46pub type OUT2_R = crate::BitReader<bool>;
47#[doc = "Field `OUT2` writer - IO invert output for pin 2"]
48pub type OUT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
49#[doc = "Field `OUT3` reader - IO invert output for pin 3"]
50pub type OUT3_R = crate::BitReader<bool>;
51#[doc = "Field `OUT3` writer - IO invert output for pin 3"]
52pub type OUT3_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
53#[doc = "Field `OUT4` reader - IO invert output for pin 4"]
54pub type OUT4_R = crate::BitReader<bool>;
55#[doc = "Field `OUT4` writer - IO invert output for pin 4"]
56pub type OUT4_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
57#[doc = "Field `OUT5` reader - IO invert output for pin 5"]
58pub type OUT5_R = crate::BitReader<bool>;
59#[doc = "Field `OUT5` writer - IO invert output for pin 5"]
60pub type OUT5_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
61#[doc = "Field `OUT6` reader - IO invert output for pin 6"]
62pub type OUT6_R = crate::BitReader<bool>;
63#[doc = "Field `OUT6` writer - IO invert output for pin 6"]
64pub type OUT6_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
65#[doc = "Field `OUT7` reader - IO invert output for pin 7"]
66pub type OUT7_R = crate::BitReader<bool>;
67#[doc = "Field `OUT7` writer - IO invert output for pin 7"]
68pub type OUT7_W<'a, const O: u8> = crate::BitWriter<'a, u32, OUT_INV_SPEC, bool, O>;
69impl R {
70    #[doc = "Bit 0 - IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0')."]
71    #[inline(always)]
72    pub fn out0(&self) -> OUT0_R {
73        OUT0_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - IO invert output for pin 1"]
76    #[inline(always)]
77    pub fn out1(&self) -> OUT1_R {
78        OUT1_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - IO invert output for pin 2"]
81    #[inline(always)]
82    pub fn out2(&self) -> OUT2_R {
83        OUT2_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - IO invert output for pin 3"]
86    #[inline(always)]
87    pub fn out3(&self) -> OUT3_R {
88        OUT3_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - IO invert output for pin 4"]
91    #[inline(always)]
92    pub fn out4(&self) -> OUT4_R {
93        OUT4_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - IO invert output for pin 5"]
96    #[inline(always)]
97    pub fn out5(&self) -> OUT5_R {
98        OUT5_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - IO invert output for pin 6"]
101    #[inline(always)]
102    pub fn out6(&self) -> OUT6_R {
103        OUT6_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - IO invert output for pin 7"]
106    #[inline(always)]
107    pub fn out7(&self) -> OUT7_R {
108        OUT7_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0')."]
113    #[inline(always)]
114    #[must_use]
115    pub fn out0(&mut self) -> OUT0_W<0> {
116        OUT0_W::new(self)
117    }
118    #[doc = "Bit 1 - IO invert output for pin 1"]
119    #[inline(always)]
120    #[must_use]
121    pub fn out1(&mut self) -> OUT1_W<1> {
122        OUT1_W::new(self)
123    }
124    #[doc = "Bit 2 - IO invert output for pin 2"]
125    #[inline(always)]
126    #[must_use]
127    pub fn out2(&mut self) -> OUT2_W<2> {
128        OUT2_W::new(self)
129    }
130    #[doc = "Bit 3 - IO invert output for pin 3"]
131    #[inline(always)]
132    #[must_use]
133    pub fn out3(&mut self) -> OUT3_W<3> {
134        OUT3_W::new(self)
135    }
136    #[doc = "Bit 4 - IO invert output for pin 4"]
137    #[inline(always)]
138    #[must_use]
139    pub fn out4(&mut self) -> OUT4_W<4> {
140        OUT4_W::new(self)
141    }
142    #[doc = "Bit 5 - IO invert output for pin 5"]
143    #[inline(always)]
144    #[must_use]
145    pub fn out5(&mut self) -> OUT5_W<5> {
146        OUT5_W::new(self)
147    }
148    #[doc = "Bit 6 - IO invert output for pin 6"]
149    #[inline(always)]
150    #[must_use]
151    pub fn out6(&mut self) -> OUT6_W<6> {
152        OUT6_W::new(self)
153    }
154    #[doc = "Bit 7 - IO invert output for pin 7"]
155    #[inline(always)]
156    #[must_use]
157    pub fn out7(&mut self) -> OUT7_W<7> {
158        OUT7_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Port output data invert register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out_inv](index.html) module"]
168pub struct OUT_INV_SPEC;
169impl crate::RegisterSpec for OUT_INV_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [out_inv::R](R) reader structure"]
173impl crate::Readable for OUT_INV_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [out_inv::W](W) writer structure"]
177impl crate::Writable for OUT_INV_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets OUT_INV to value 0"]
183impl crate::Resettable for OUT_INV_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}
cyt3bb_a/m0/gpio/prt/out_inv.rs

cyt3bb_a/m0/gpio/prt/
out_inv.rs
