cyt3bb_a/m0/gpio/prt/
cfg_out.rs

1#[doc = "Register `CFG_OUT` reader"]
2pub struct R(crate::R<CFG_OUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG_OUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG_OUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG_OUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG_OUT` writer"]
17pub struct W(crate::W<CFG_OUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG_OUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG_OUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG_OUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SLOW0` reader - Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate"]
38pub type SLOW0_R = crate::BitReader<bool>;
39#[doc = "Field `SLOW0` writer - Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate"]
40pub type SLOW0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
41#[doc = "Field `SLOW1` reader - Enables slow slew rate for IO pin 1"]
42pub type SLOW1_R = crate::BitReader<bool>;
43#[doc = "Field `SLOW1` writer - Enables slow slew rate for IO pin 1"]
44pub type SLOW1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
45#[doc = "Field `SLOW2` reader - Enables slow slew rate for IO pin 2"]
46pub type SLOW2_R = crate::BitReader<bool>;
47#[doc = "Field `SLOW2` writer - Enables slow slew rate for IO pin 2"]
48pub type SLOW2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
49#[doc = "Field `SLOW3` reader - Enables slow slew rate for IO pin 3"]
50pub type SLOW3_R = crate::BitReader<bool>;
51#[doc = "Field `SLOW3` writer - Enables slow slew rate for IO pin 3"]
52pub type SLOW3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
53#[doc = "Field `SLOW4` reader - Enables slow slew rate for IO pin 4"]
54pub type SLOW4_R = crate::BitReader<bool>;
55#[doc = "Field `SLOW4` writer - Enables slow slew rate for IO pin 4"]
56pub type SLOW4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
57#[doc = "Field `SLOW5` reader - Enables slow slew rate for IO pin 5"]
58pub type SLOW5_R = crate::BitReader<bool>;
59#[doc = "Field `SLOW5` writer - Enables slow slew rate for IO pin 5"]
60pub type SLOW5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
61#[doc = "Field `SLOW6` reader - Enables slow slew rate for IO pin 6"]
62pub type SLOW6_R = crate::BitReader<bool>;
63#[doc = "Field `SLOW6` writer - Enables slow slew rate for IO pin 6"]
64pub type SLOW6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
65#[doc = "Field `SLOW7` reader - Enables slow slew rate for IO pin 7"]
66pub type SLOW7_R = crate::BitReader<bool>;
67#[doc = "Field `SLOW7` writer - Enables slow slew rate for IO pin 7"]
68pub type SLOW7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_OUT_SPEC, bool, O>;
69#[doc = "Field `DRIVE_SEL0` reader - Sets the GPIO drive strength for IO pin 0"]
70pub type DRIVE_SEL0_R = crate::FieldReader<u8, DRIVE_SEL0_A>;
71#[doc = "Sets the GPIO drive strength for IO pin 0\n\nValue on reset: 0"]
72#[derive(Clone, Copy, Debug, PartialEq, Eq)]
73#[repr(u8)]
74pub enum DRIVE_SEL0_A {
75    #[doc = "0: N/A"]
76    DRIVE_SEL_ZERO = 0,
77    #[doc = "1: N/A"]
78    DRIVE_SEL_ONE = 1,
79    #[doc = "2: N/A"]
80    DRIVE_SEL_TWO = 2,
81    #[doc = "3: N/A"]
82    DRIVE_SEL_THREE = 3,
83}
84impl From<DRIVE_SEL0_A> for u8 {
85    #[inline(always)]
86    fn from(variant: DRIVE_SEL0_A) -> Self {
87        variant as _
88    }
89}
90impl DRIVE_SEL0_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub fn variant(&self) -> DRIVE_SEL0_A {
94        match self.bits {
95            0 => DRIVE_SEL0_A::DRIVE_SEL_ZERO,
96            1 => DRIVE_SEL0_A::DRIVE_SEL_ONE,
97            2 => DRIVE_SEL0_A::DRIVE_SEL_TWO,
98            3 => DRIVE_SEL0_A::DRIVE_SEL_THREE,
99            _ => unreachable!(),
100        }
101    }
102    #[doc = "Checks if the value of the field is `DRIVE_SEL_ZERO`"]
103    #[inline(always)]
104    pub fn is_drive_sel_zero(&self) -> bool {
105        *self == DRIVE_SEL0_A::DRIVE_SEL_ZERO
106    }
107    #[doc = "Checks if the value of the field is `DRIVE_SEL_ONE`"]
108    #[inline(always)]
109    pub fn is_drive_sel_one(&self) -> bool {
110        *self == DRIVE_SEL0_A::DRIVE_SEL_ONE
111    }
112    #[doc = "Checks if the value of the field is `DRIVE_SEL_TWO`"]
113    #[inline(always)]
114    pub fn is_drive_sel_two(&self) -> bool {
115        *self == DRIVE_SEL0_A::DRIVE_SEL_TWO
116    }
117    #[doc = "Checks if the value of the field is `DRIVE_SEL_THREE`"]
118    #[inline(always)]
119    pub fn is_drive_sel_three(&self) -> bool {
120        *self == DRIVE_SEL0_A::DRIVE_SEL_THREE
121    }
122}
123#[doc = "Field `DRIVE_SEL0` writer - Sets the GPIO drive strength for IO pin 0"]
124pub type DRIVE_SEL0_W<'a, const O: u8> =
125    crate::FieldWriterSafe<'a, u32, CFG_OUT_SPEC, u8, DRIVE_SEL0_A, 2, O>;
126impl<'a, const O: u8> DRIVE_SEL0_W<'a, O> {
127    #[doc = "N/A"]
128    #[inline(always)]
129    pub fn drive_sel_zero(self) -> &'a mut W {
130        self.variant(DRIVE_SEL0_A::DRIVE_SEL_ZERO)
131    }
132    #[doc = "N/A"]
133    #[inline(always)]
134    pub fn drive_sel_one(self) -> &'a mut W {
135        self.variant(DRIVE_SEL0_A::DRIVE_SEL_ONE)
136    }
137    #[doc = "N/A"]
138    #[inline(always)]
139    pub fn drive_sel_two(self) -> &'a mut W {
140        self.variant(DRIVE_SEL0_A::DRIVE_SEL_TWO)
141    }
142    #[doc = "N/A"]
143    #[inline(always)]
144    pub fn drive_sel_three(self) -> &'a mut W {
145        self.variant(DRIVE_SEL0_A::DRIVE_SEL_THREE)
146    }
147}
148#[doc = "Field `DRIVE_SEL1` reader - Sets the GPIO drive strength for IO pin 1"]
149pub type DRIVE_SEL1_R = crate::FieldReader<u8, u8>;
150#[doc = "Field `DRIVE_SEL1` writer - Sets the GPIO drive strength for IO pin 1"]
151pub type DRIVE_SEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
152#[doc = "Field `DRIVE_SEL2` reader - Sets the GPIO drive strength for IO pin 2"]
153pub type DRIVE_SEL2_R = crate::FieldReader<u8, u8>;
154#[doc = "Field `DRIVE_SEL2` writer - Sets the GPIO drive strength for IO pin 2"]
155pub type DRIVE_SEL2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
156#[doc = "Field `DRIVE_SEL3` reader - Sets the GPIO drive strength for IO pin 3"]
157pub type DRIVE_SEL3_R = crate::FieldReader<u8, u8>;
158#[doc = "Field `DRIVE_SEL3` writer - Sets the GPIO drive strength for IO pin 3"]
159pub type DRIVE_SEL3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
160#[doc = "Field `DRIVE_SEL4` reader - Sets the GPIO drive strength for IO pin 4"]
161pub type DRIVE_SEL4_R = crate::FieldReader<u8, u8>;
162#[doc = "Field `DRIVE_SEL4` writer - Sets the GPIO drive strength for IO pin 4"]
163pub type DRIVE_SEL4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
164#[doc = "Field `DRIVE_SEL5` reader - Sets the GPIO drive strength for IO pin 5"]
165pub type DRIVE_SEL5_R = crate::FieldReader<u8, u8>;
166#[doc = "Field `DRIVE_SEL5` writer - Sets the GPIO drive strength for IO pin 5"]
167pub type DRIVE_SEL5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
168#[doc = "Field `DRIVE_SEL6` reader - Sets the GPIO drive strength for IO pin 6"]
169pub type DRIVE_SEL6_R = crate::FieldReader<u8, u8>;
170#[doc = "Field `DRIVE_SEL6` writer - Sets the GPIO drive strength for IO pin 6"]
171pub type DRIVE_SEL6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
172#[doc = "Field `DRIVE_SEL7` reader - Sets the GPIO drive strength for IO pin 7"]
173pub type DRIVE_SEL7_R = crate::FieldReader<u8, u8>;
174#[doc = "Field `DRIVE_SEL7` writer - Sets the GPIO drive strength for IO pin 7"]
175pub type DRIVE_SEL7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_OUT_SPEC, u8, u8, 2, O>;
176impl R {
177    #[doc = "Bit 0 - Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate"]
178    #[inline(always)]
179    pub fn slow0(&self) -> SLOW0_R {
180        SLOW0_R::new((self.bits & 1) != 0)
181    }
182    #[doc = "Bit 1 - Enables slow slew rate for IO pin 1"]
183    #[inline(always)]
184    pub fn slow1(&self) -> SLOW1_R {
185        SLOW1_R::new(((self.bits >> 1) & 1) != 0)
186    }
187    #[doc = "Bit 2 - Enables slow slew rate for IO pin 2"]
188    #[inline(always)]
189    pub fn slow2(&self) -> SLOW2_R {
190        SLOW2_R::new(((self.bits >> 2) & 1) != 0)
191    }
192    #[doc = "Bit 3 - Enables slow slew rate for IO pin 3"]
193    #[inline(always)]
194    pub fn slow3(&self) -> SLOW3_R {
195        SLOW3_R::new(((self.bits >> 3) & 1) != 0)
196    }
197    #[doc = "Bit 4 - Enables slow slew rate for IO pin 4"]
198    #[inline(always)]
199    pub fn slow4(&self) -> SLOW4_R {
200        SLOW4_R::new(((self.bits >> 4) & 1) != 0)
201    }
202    #[doc = "Bit 5 - Enables slow slew rate for IO pin 5"]
203    #[inline(always)]
204    pub fn slow5(&self) -> SLOW5_R {
205        SLOW5_R::new(((self.bits >> 5) & 1) != 0)
206    }
207    #[doc = "Bit 6 - Enables slow slew rate for IO pin 6"]
208    #[inline(always)]
209    pub fn slow6(&self) -> SLOW6_R {
210        SLOW6_R::new(((self.bits >> 6) & 1) != 0)
211    }
212    #[doc = "Bit 7 - Enables slow slew rate for IO pin 7"]
213    #[inline(always)]
214    pub fn slow7(&self) -> SLOW7_R {
215        SLOW7_R::new(((self.bits >> 7) & 1) != 0)
216    }
217    #[doc = "Bits 16:17 - Sets the GPIO drive strength for IO pin 0"]
218    #[inline(always)]
219    pub fn drive_sel0(&self) -> DRIVE_SEL0_R {
220        DRIVE_SEL0_R::new(((self.bits >> 16) & 3) as u8)
221    }
222    #[doc = "Bits 18:19 - Sets the GPIO drive strength for IO pin 1"]
223    #[inline(always)]
224    pub fn drive_sel1(&self) -> DRIVE_SEL1_R {
225        DRIVE_SEL1_R::new(((self.bits >> 18) & 3) as u8)
226    }
227    #[doc = "Bits 20:21 - Sets the GPIO drive strength for IO pin 2"]
228    #[inline(always)]
229    pub fn drive_sel2(&self) -> DRIVE_SEL2_R {
230        DRIVE_SEL2_R::new(((self.bits >> 20) & 3) as u8)
231    }
232    #[doc = "Bits 22:23 - Sets the GPIO drive strength for IO pin 3"]
233    #[inline(always)]
234    pub fn drive_sel3(&self) -> DRIVE_SEL3_R {
235        DRIVE_SEL3_R::new(((self.bits >> 22) & 3) as u8)
236    }
237    #[doc = "Bits 24:25 - Sets the GPIO drive strength for IO pin 4"]
238    #[inline(always)]
239    pub fn drive_sel4(&self) -> DRIVE_SEL4_R {
240        DRIVE_SEL4_R::new(((self.bits >> 24) & 3) as u8)
241    }
242    #[doc = "Bits 26:27 - Sets the GPIO drive strength for IO pin 5"]
243    #[inline(always)]
244    pub fn drive_sel5(&self) -> DRIVE_SEL5_R {
245        DRIVE_SEL5_R::new(((self.bits >> 26) & 3) as u8)
246    }
247    #[doc = "Bits 28:29 - Sets the GPIO drive strength for IO pin 6"]
248    #[inline(always)]
249    pub fn drive_sel6(&self) -> DRIVE_SEL6_R {
250        DRIVE_SEL6_R::new(((self.bits >> 28) & 3) as u8)
251    }
252    #[doc = "Bits 30:31 - Sets the GPIO drive strength for IO pin 7"]
253    #[inline(always)]
254    pub fn drive_sel7(&self) -> DRIVE_SEL7_R {
255        DRIVE_SEL7_R::new(((self.bits >> 30) & 3) as u8)
256    }
257}
258impl W {
259    #[doc = "Bit 0 - Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate"]
260    #[inline(always)]
261    #[must_use]
262    pub fn slow0(&mut self) -> SLOW0_W<0> {
263        SLOW0_W::new(self)
264    }
265    #[doc = "Bit 1 - Enables slow slew rate for IO pin 1"]
266    #[inline(always)]
267    #[must_use]
268    pub fn slow1(&mut self) -> SLOW1_W<1> {
269        SLOW1_W::new(self)
270    }
271    #[doc = "Bit 2 - Enables slow slew rate for IO pin 2"]
272    #[inline(always)]
273    #[must_use]
274    pub fn slow2(&mut self) -> SLOW2_W<2> {
275        SLOW2_W::new(self)
276    }
277    #[doc = "Bit 3 - Enables slow slew rate for IO pin 3"]
278    #[inline(always)]
279    #[must_use]
280    pub fn slow3(&mut self) -> SLOW3_W<3> {
281        SLOW3_W::new(self)
282    }
283    #[doc = "Bit 4 - Enables slow slew rate for IO pin 4"]
284    #[inline(always)]
285    #[must_use]
286    pub fn slow4(&mut self) -> SLOW4_W<4> {
287        SLOW4_W::new(self)
288    }
289    #[doc = "Bit 5 - Enables slow slew rate for IO pin 5"]
290    #[inline(always)]
291    #[must_use]
292    pub fn slow5(&mut self) -> SLOW5_W<5> {
293        SLOW5_W::new(self)
294    }
295    #[doc = "Bit 6 - Enables slow slew rate for IO pin 6"]
296    #[inline(always)]
297    #[must_use]
298    pub fn slow6(&mut self) -> SLOW6_W<6> {
299        SLOW6_W::new(self)
300    }
301    #[doc = "Bit 7 - Enables slow slew rate for IO pin 7"]
302    #[inline(always)]
303    #[must_use]
304    pub fn slow7(&mut self) -> SLOW7_W<7> {
305        SLOW7_W::new(self)
306    }
307    #[doc = "Bits 16:17 - Sets the GPIO drive strength for IO pin 0"]
308    #[inline(always)]
309    #[must_use]
310    pub fn drive_sel0(&mut self) -> DRIVE_SEL0_W<16> {
311        DRIVE_SEL0_W::new(self)
312    }
313    #[doc = "Bits 18:19 - Sets the GPIO drive strength for IO pin 1"]
314    #[inline(always)]
315    #[must_use]
316    pub fn drive_sel1(&mut self) -> DRIVE_SEL1_W<18> {
317        DRIVE_SEL1_W::new(self)
318    }
319    #[doc = "Bits 20:21 - Sets the GPIO drive strength for IO pin 2"]
320    #[inline(always)]
321    #[must_use]
322    pub fn drive_sel2(&mut self) -> DRIVE_SEL2_W<20> {
323        DRIVE_SEL2_W::new(self)
324    }
325    #[doc = "Bits 22:23 - Sets the GPIO drive strength for IO pin 3"]
326    #[inline(always)]
327    #[must_use]
328    pub fn drive_sel3(&mut self) -> DRIVE_SEL3_W<22> {
329        DRIVE_SEL3_W::new(self)
330    }
331    #[doc = "Bits 24:25 - Sets the GPIO drive strength for IO pin 4"]
332    #[inline(always)]
333    #[must_use]
334    pub fn drive_sel4(&mut self) -> DRIVE_SEL4_W<24> {
335        DRIVE_SEL4_W::new(self)
336    }
337    #[doc = "Bits 26:27 - Sets the GPIO drive strength for IO pin 5"]
338    #[inline(always)]
339    #[must_use]
340    pub fn drive_sel5(&mut self) -> DRIVE_SEL5_W<26> {
341        DRIVE_SEL5_W::new(self)
342    }
343    #[doc = "Bits 28:29 - Sets the GPIO drive strength for IO pin 6"]
344    #[inline(always)]
345    #[must_use]
346    pub fn drive_sel6(&mut self) -> DRIVE_SEL6_W<28> {
347        DRIVE_SEL6_W::new(self)
348    }
349    #[doc = "Bits 30:31 - Sets the GPIO drive strength for IO pin 7"]
350    #[inline(always)]
351    #[must_use]
352    pub fn drive_sel7(&mut self) -> DRIVE_SEL7_W<30> {
353        DRIVE_SEL7_W::new(self)
354    }
355    #[doc = "Writes raw bits to the register."]
356    #[inline(always)]
357    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
358        self.0.bits(bits);
359        self
360    }
361}
362#[doc = "Port output buffer configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg_out](index.html) module"]
363pub struct CFG_OUT_SPEC;
364impl crate::RegisterSpec for CFG_OUT_SPEC {
365    type Ux = u32;
366}
367#[doc = "`read()` method returns [cfg_out::R](R) reader structure"]
368impl crate::Readable for CFG_OUT_SPEC {
369    type Reader = R;
370}
371#[doc = "`write(|w| ..)` method takes [cfg_out::W](W) writer structure"]
372impl crate::Writable for CFG_OUT_SPEC {
373    type Writer = W;
374    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
375    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
376}
377#[doc = "`reset()` method sets CFG_OUT to value 0"]
378impl crate::Resettable for CFG_OUT_SPEC {
379    const RESET_VALUE: Self::Ux = 0;
380}
cyt3bb_a/m0/gpio/prt/cfg_out.rs

cyt3bb_a/m0/gpio/prt/
cfg_out.rs
