cyt3bb_a/m0/eth0/
tsu_timer_incr_sub_nsec.rs

1#[doc = "Register `TSU_TIMER_INCR_SUB_NSEC` reader"]
2pub struct R(crate::R<TSU_TIMER_INCR_SUB_NSEC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TSU_TIMER_INCR_SUB_NSEC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TSU_TIMER_INCR_SUB_NSEC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TSU_TIMER_INCR_SUB_NSEC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TSU_TIMER_INCR_SUB_NSEC` writer"]
17pub struct W(crate::W<TSU_TIMER_INCR_SUB_NSEC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TSU_TIMER_INCR_SUB_NSEC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TSU_TIMER_INCR_SUB_NSEC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TSU_TIMER_INCR_SUB_NSEC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SUB_NS_INCR` reader - These are the most significant bits \\[23:8\\]
38of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds)."]
39pub type SUB_NS_INCR_R = crate::FieldReader<u16, u16>;
40#[doc = "Field `SUB_NS_INCR` writer - These are the most significant bits \\[23:8\\]
41of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds)."]
42pub type SUB_NS_INCR_W<'a, const O: u8> =
43    crate::FieldWriter<'a, u32, TSU_TIMER_INCR_SUB_NSEC_SPEC, u16, u16, 16, O>;
44#[doc = "Field `SUB_NS_INCR_LSB` reader - These are the least significant bits \\[7:0\\]
45of the sub-ns value by which the 1588 timer will be incremented each clock cycle."]
46pub type SUB_NS_INCR_LSB_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `SUB_NS_INCR_LSB` writer - These are the least significant bits \\[7:0\\]
48of the sub-ns value by which the 1588 timer will be incremented each clock cycle."]
49pub type SUB_NS_INCR_LSB_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, TSU_TIMER_INCR_SUB_NSEC_SPEC, u8, u8, 8, O>;
51impl R {
52    #[doc = "Bits 0:15 - These are the most significant bits \\[23:8\\]
53of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds)."]
54    #[inline(always)]
55    pub fn sub_ns_incr(&self) -> SUB_NS_INCR_R {
56        SUB_NS_INCR_R::new((self.bits & 0xffff) as u16)
57    }
58    #[doc = "Bits 24:31 - These are the least significant bits \\[7:0\\]
59of the sub-ns value by which the 1588 timer will be incremented each clock cycle."]
60    #[inline(always)]
61    pub fn sub_ns_incr_lsb(&self) -> SUB_NS_INCR_LSB_R {
62        SUB_NS_INCR_LSB_R::new(((self.bits >> 24) & 0xff) as u8)
63    }
64}
65impl W {
66    #[doc = "Bits 0:15 - These are the most significant bits \\[23:8\\]
67of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds)."]
68    #[inline(always)]
69    #[must_use]
70    pub fn sub_ns_incr(&mut self) -> SUB_NS_INCR_W<0> {
71        SUB_NS_INCR_W::new(self)
72    }
73    #[doc = "Bits 24:31 - These are the least significant bits \\[7:0\\]
74of the sub-ns value by which the 1588 timer will be incremented each clock cycle."]
75    #[inline(always)]
76    #[must_use]
77    pub fn sub_ns_incr_lsb(&mut self) -> SUB_NS_INCR_LSB_W<24> {
78        SUB_NS_INCR_LSB_W::new(self)
79    }
80    #[doc = "Writes raw bits to the register."]
81    #[inline(always)]
82    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
83        self.0.bits(bits);
84        self
85    }
86}
87#[doc = "1588 Timer Increment Register sub nsec\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsu_timer_incr_sub_nsec](index.html) module"]
88pub struct TSU_TIMER_INCR_SUB_NSEC_SPEC;
89impl crate::RegisterSpec for TSU_TIMER_INCR_SUB_NSEC_SPEC {
90    type Ux = u32;
91}
92#[doc = "`read()` method returns [tsu_timer_incr_sub_nsec::R](R) reader structure"]
93impl crate::Readable for TSU_TIMER_INCR_SUB_NSEC_SPEC {
94    type Reader = R;
95}
96#[doc = "`write(|w| ..)` method takes [tsu_timer_incr_sub_nsec::W](W) writer structure"]
97impl crate::Writable for TSU_TIMER_INCR_SUB_NSEC_SPEC {
98    type Writer = W;
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
101}
102#[doc = "`reset()` method sets TSU_TIMER_INCR_SUB_NSEC to value 0"]
103impl crate::Resettable for TSU_TIMER_INCR_SUB_NSEC_SPEC {
104    const RESET_VALUE: Self::Ux = 0;
105}
cyt3bb_a/m0/eth0/tsu_timer_incr_sub_nsec.rs

cyt3bb_a/m0/eth0/
tsu_timer_incr_sub_nsec.rs
