1#[doc = "Register `NETWORK_CONFIG` reader"]
2pub struct R(crate::R<NETWORK_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<NETWORK_CONFIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<NETWORK_CONFIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<NETWORK_CONFIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `NETWORK_CONFIG` writer"]
17pub struct W(crate::W<NETWORK_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<NETWORK_CONFIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<NETWORK_CONFIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<NETWORK_CONFIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SPEED` reader - Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps."]
38pub type SPEED_R = crate::BitReader<bool>;
39#[doc = "Field `SPEED` writer - Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps."]
40pub type SPEED_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
41#[doc = "Field `FULL_DUPLEX` reader - Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin."]
42pub type FULL_DUPLEX_R = crate::BitReader<bool>;
43#[doc = "Field `FULL_DUPLEX` writer - Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin."]
44pub type FULL_DUPLEX_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
45#[doc = "Field `DISCARD_NON_VLAN_FRAMES` reader - Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic."]
46pub type DISCARD_NON_VLAN_FRAMES_R = crate::BitReader<bool>;
47#[doc = "Field `DISCARD_NON_VLAN_FRAMES` writer - Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic."]
48pub type DISCARD_NON_VLAN_FRAMES_W<'a, const O: u8> =
49 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
50#[doc = "Field `JUMBO_FRAMES` reader - Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes."]
51pub type JUMBO_FRAMES_R = crate::BitReader<bool>;
52#[doc = "Field `JUMBO_FRAMES` writer - Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes."]
53pub type JUMBO_FRAMES_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
54#[doc = "Field `COPY_ALL_FRAMES` reader - Copy all frames - when set to logic one, all valid frames will be accepted."]
55pub type COPY_ALL_FRAMES_R = crate::BitReader<bool>;
56#[doc = "Field `COPY_ALL_FRAMES` writer - Copy all frames - when set to logic one, all valid frames will be accepted."]
57pub type COPY_ALL_FRAMES_W<'a, const O: u8> =
58 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
59#[doc = "Field `NO_BROADCAST` reader - No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted."]
60pub type NO_BROADCAST_R = crate::BitReader<bool>;
61#[doc = "Field `NO_BROADCAST` writer - No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted."]
62pub type NO_BROADCAST_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
63#[doc = "Field `MULTICAST_HASH_ENABLE` reader - Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
64pub type MULTICAST_HASH_ENABLE_R = crate::BitReader<bool>;
65#[doc = "Field `MULTICAST_HASH_ENABLE` writer - Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
66pub type MULTICAST_HASH_ENABLE_W<'a, const O: u8> =
67 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
68#[doc = "Field `UNICAST_HASH_ENABLE` reader - Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
69pub type UNICAST_HASH_ENABLE_R = crate::BitReader<bool>;
70#[doc = "Field `UNICAST_HASH_ENABLE` writer - Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
71pub type UNICAST_HASH_ENABLE_W<'a, const O: u8> =
72 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
73#[doc = "Field `RECEIVE_1536_BYTE_FRAMES` reader - Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes."]
74pub type RECEIVE_1536_BYTE_FRAMES_R = crate::BitReader<bool>;
75#[doc = "Field `RECEIVE_1536_BYTE_FRAMES` writer - Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes."]
76pub type RECEIVE_1536_BYTE_FRAMES_W<'a, const O: u8> =
77 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
78#[doc = "Field `EXTERNAL_ADDRESS_MATCH_ENABLE` reader - External address match enable - when set the external address match interface can be used to copy frames to memory."]
79pub type EXTERNAL_ADDRESS_MATCH_ENABLE_R = crate::BitReader<bool>;
80#[doc = "Field `EXTERNAL_ADDRESS_MATCH_ENABLE` writer - External address match enable - when set the external address match interface can be used to copy frames to memory."]
81pub type EXTERNAL_ADDRESS_MATCH_ENABLE_W<'a, const O: u8> =
82 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
83#[doc = "Field `GIGABIT_MODE_ENABLE` reader - Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII interface 1: Gigabit operation using GMI interface"]
84pub type GIGABIT_MODE_ENABLE_R = crate::BitReader<bool>;
85#[doc = "Field `GIGABIT_MODE_ENABLE` writer - Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII interface 1: Gigabit operation using GMI interface"]
86pub type GIGABIT_MODE_ENABLE_W<'a, const O: u8> =
87 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
88#[doc = "Field `PCS_SELECT` reader - PCS select - selects between MII/GMII and TBI"]
89pub type PCS_SELECT_R = crate::BitReader<bool>;
90#[doc = "Field `PCS_SELECT` writer - PCS select - selects between MII/GMII and TBI"]
91pub type PCS_SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
92#[doc = "Field `RETRY_TEST` reader - Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle."]
93pub type RETRY_TEST_R = crate::BitReader<bool>;
94#[doc = "Field `RETRY_TEST` writer - Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle."]
95pub type RETRY_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
96#[doc = "Field `PAUSE_ENABLE` reader - Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated."]
97pub type PAUSE_ENABLE_R = crate::BitReader<bool>;
98#[doc = "Field `PAUSE_ENABLE` writer - Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated."]
99pub type PAUSE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
100#[doc = "Field `RECEIVE_BUFFER_OFFSET` reader - Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer."]
101pub type RECEIVE_BUFFER_OFFSET_R = crate::FieldReader<u8, u8>;
102#[doc = "Field `RECEIVE_BUFFER_OFFSET` writer - Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer."]
103pub type RECEIVE_BUFFER_OFFSET_W<'a, const O: u8> =
104 crate::FieldWriter<'a, u32, NETWORK_CONFIG_SPEC, u8, u8, 2, O>;
105#[doc = "Field `LENGTH_FIELD_ERROR_FRAME_DISCARD` reader - Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600."]
106pub type LENGTH_FIELD_ERROR_FRAME_DISCARD_R = crate::BitReader<bool>;
107#[doc = "Field `LENGTH_FIELD_ERROR_FRAME_DISCARD` writer - Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600."]
108pub type LENGTH_FIELD_ERROR_FRAME_DISCARD_W<'a, const O: u8> =
109 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
110#[doc = "Field `FCS_REMOVE` reader - FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode."]
111pub type FCS_REMOVE_R = crate::BitReader<bool>;
112#[doc = "Field `FCS_REMOVE` writer - FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode."]
113pub type FCS_REMOVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
114#[doc = "Field `MDC_CLOCK_DIVISION` reader - MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v 000: divide pclk by 8 (pclk up to 20 MHz) 001: divide pclk by 16 (pclk up to 40 MHz) 010: divide pclk by 32 (pclk up to 80 MHz) 011: divide pclk by 48 (pclk up to 120MHz) 100: divide pclk by 64 (pclk up to 160 MHz) 101: divide pclk by 96 (pclk up to 240 MHz) 110: divide pclk by 128 (pclk up to 320 MHz) 111: divide pclk by 224 (pclk up to 540 MHz). Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable."]
115pub type MDC_CLOCK_DIVISION_R = crate::FieldReader<u8, u8>;
116#[doc = "Field `MDC_CLOCK_DIVISION` writer - MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v 000: divide pclk by 8 (pclk up to 20 MHz) 001: divide pclk by 16 (pclk up to 40 MHz) 010: divide pclk by 32 (pclk up to 80 MHz) 011: divide pclk by 48 (pclk up to 120MHz) 100: divide pclk by 64 (pclk up to 160 MHz) 101: divide pclk by 96 (pclk up to 240 MHz) 110: divide pclk by 128 (pclk up to 320 MHz) 111: divide pclk by 224 (pclk up to 540 MHz). Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable."]
117pub type MDC_CLOCK_DIVISION_W<'a, const O: u8> =
118 crate::FieldWriter<'a, u32, NETWORK_CONFIG_SPEC, u8, u8, 3, O>;
119#[doc = "Field `DATA_BUS_WIDTH` reader - Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width 10: 128 bit AMBA (AXI/AHB) data bus width 11: 128 bit AMBA (AXI/AHB) data bus width. Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. Note: For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0."]
120pub type DATA_BUS_WIDTH_R = crate::FieldReader<u8, u8>;
121#[doc = "Field `DATA_BUS_WIDTH` writer - Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width 10: 128 bit AMBA (AXI/AHB) data bus width 11: 128 bit AMBA (AXI/AHB) data bus width. Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. Note: For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0."]
122pub type DATA_BUS_WIDTH_W<'a, const O: u8> =
123 crate::FieldWriter<'a, u32, NETWORK_CONFIG_SPEC, u8, u8, 2, O>;
124#[doc = "Field `DISABLE_COPY_OF_PAUSE_FRAMES` reader - Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required."]
125pub type DISABLE_COPY_OF_PAUSE_FRAMES_R = crate::BitReader<bool>;
126#[doc = "Field `DISABLE_COPY_OF_PAUSE_FRAMES` writer - Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required."]
127pub type DISABLE_COPY_OF_PAUSE_FRAMES_W<'a, const O: u8> =
128 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
129#[doc = "Field `RECEIVE_CHECKSUM_OFFLOAD_ENABLE` reader - Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded."]
130pub type RECEIVE_CHECKSUM_OFFLOAD_ENABLE_R = crate::BitReader<bool>;
131#[doc = "Field `RECEIVE_CHECKSUM_OFFLOAD_ENABLE` writer - Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded."]
132pub type RECEIVE_CHECKSUM_OFFLOAD_ENABLE_W<'a, const O: u8> =
133 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
134#[doc = "Field `EN_HALF_DUPLEX_RX` reader - Enable frames to be received in half-duplex mode while transmitting. Must set '0', MXETH only supports full-duplex mode."]
135pub type EN_HALF_DUPLEX_RX_R = crate::BitReader<bool>;
136#[doc = "Field `EN_HALF_DUPLEX_RX` writer - Enable frames to be received in half-duplex mode while transmitting. Must set '0', MXETH only supports full-duplex mode."]
137pub type EN_HALF_DUPLEX_RX_W<'a, const O: u8> =
138 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
139#[doc = "Field `IGNORE_RX_FCS` reader - Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero."]
140pub type IGNORE_RX_FCS_R = crate::BitReader<bool>;
141#[doc = "Field `IGNORE_RX_FCS` writer - Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero."]
142pub type IGNORE_RX_FCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
143#[doc = "Field `SGMII_MODE_ENABLE` reader - SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms."]
144pub type SGMII_MODE_ENABLE_R = crate::BitReader<bool>;
145#[doc = "Field `SGMII_MODE_ENABLE` writer - SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms."]
146pub type SGMII_MODE_ENABLE_W<'a, const O: u8> =
147 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
148#[doc = "Field `IPG_STRETCH_ENABLE` reader - IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register."]
149pub type IPG_STRETCH_ENABLE_R = crate::BitReader<bool>;
150#[doc = "Field `IPG_STRETCH_ENABLE` writer - IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register."]
151pub type IPG_STRETCH_ENABLE_W<'a, const O: u8> =
152 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
153#[doc = "Field `NSP_CHANGE` reader - Receive bad preamble. When set frames with non-standard preamble are not rejected."]
154pub type NSP_CHANGE_R = crate::BitReader<bool>;
155#[doc = "Field `NSP_CHANGE` writer - Receive bad preamble. When set frames with non-standard preamble are not rejected."]
156pub type NSP_CHANGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
157#[doc = "Field `IGNORE_IPG_RX_ER` reader - Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode."]
158pub type IGNORE_IPG_RX_ER_R = crate::BitReader<bool>;
159#[doc = "Field `IGNORE_IPG_RX_ER` writer - Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode."]
160pub type IGNORE_IPG_RX_ER_W<'a, const O: u8> =
161 crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
162#[doc = "Field `RSVD_31` reader - N/A"]
163pub type RSVD_31_R = crate::BitReader<bool>;
164#[doc = "Field `RSVD_31` writer - N/A"]
165pub type RSVD_31_W<'a, const O: u8> = crate::BitWriter<'a, u32, NETWORK_CONFIG_SPEC, bool, O>;
166impl R {
167 #[doc = "Bit 0 - Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps."]
168 #[inline(always)]
169 pub fn speed(&self) -> SPEED_R {
170 SPEED_R::new((self.bits & 1) != 0)
171 }
172 #[doc = "Bit 1 - Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin."]
173 #[inline(always)]
174 pub fn full_duplex(&self) -> FULL_DUPLEX_R {
175 FULL_DUPLEX_R::new(((self.bits >> 1) & 1) != 0)
176 }
177 #[doc = "Bit 2 - Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic."]
178 #[inline(always)]
179 pub fn discard_non_vlan_frames(&self) -> DISCARD_NON_VLAN_FRAMES_R {
180 DISCARD_NON_VLAN_FRAMES_R::new(((self.bits >> 2) & 1) != 0)
181 }
182 #[doc = "Bit 3 - Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes."]
183 #[inline(always)]
184 pub fn jumbo_frames(&self) -> JUMBO_FRAMES_R {
185 JUMBO_FRAMES_R::new(((self.bits >> 3) & 1) != 0)
186 }
187 #[doc = "Bit 4 - Copy all frames - when set to logic one, all valid frames will be accepted."]
188 #[inline(always)]
189 pub fn copy_all_frames(&self) -> COPY_ALL_FRAMES_R {
190 COPY_ALL_FRAMES_R::new(((self.bits >> 4) & 1) != 0)
191 }
192 #[doc = "Bit 5 - No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted."]
193 #[inline(always)]
194 pub fn no_broadcast(&self) -> NO_BROADCAST_R {
195 NO_BROADCAST_R::new(((self.bits >> 5) & 1) != 0)
196 }
197 #[doc = "Bit 6 - Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
198 #[inline(always)]
199 pub fn multicast_hash_enable(&self) -> MULTICAST_HASH_ENABLE_R {
200 MULTICAST_HASH_ENABLE_R::new(((self.bits >> 6) & 1) != 0)
201 }
202 #[doc = "Bit 7 - Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
203 #[inline(always)]
204 pub fn unicast_hash_enable(&self) -> UNICAST_HASH_ENABLE_R {
205 UNICAST_HASH_ENABLE_R::new(((self.bits >> 7) & 1) != 0)
206 }
207 #[doc = "Bit 8 - Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes."]
208 #[inline(always)]
209 pub fn receive_1536_byte_frames(&self) -> RECEIVE_1536_BYTE_FRAMES_R {
210 RECEIVE_1536_BYTE_FRAMES_R::new(((self.bits >> 8) & 1) != 0)
211 }
212 #[doc = "Bit 9 - External address match enable - when set the external address match interface can be used to copy frames to memory."]
213 #[inline(always)]
214 pub fn external_address_match_enable(&self) -> EXTERNAL_ADDRESS_MATCH_ENABLE_R {
215 EXTERNAL_ADDRESS_MATCH_ENABLE_R::new(((self.bits >> 9) & 1) != 0)
216 }
217 #[doc = "Bit 10 - Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII interface 1: Gigabit operation using GMI interface"]
218 #[inline(always)]
219 pub fn gigabit_mode_enable(&self) -> GIGABIT_MODE_ENABLE_R {
220 GIGABIT_MODE_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
221 }
222 #[doc = "Bit 11 - PCS select - selects between MII/GMII and TBI"]
223 #[inline(always)]
224 pub fn pcs_select(&self) -> PCS_SELECT_R {
225 PCS_SELECT_R::new(((self.bits >> 11) & 1) != 0)
226 }
227 #[doc = "Bit 12 - Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle."]
228 #[inline(always)]
229 pub fn retry_test(&self) -> RETRY_TEST_R {
230 RETRY_TEST_R::new(((self.bits >> 12) & 1) != 0)
231 }
232 #[doc = "Bit 13 - Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated."]
233 #[inline(always)]
234 pub fn pause_enable(&self) -> PAUSE_ENABLE_R {
235 PAUSE_ENABLE_R::new(((self.bits >> 13) & 1) != 0)
236 }
237 #[doc = "Bits 14:15 - Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer."]
238 #[inline(always)]
239 pub fn receive_buffer_offset(&self) -> RECEIVE_BUFFER_OFFSET_R {
240 RECEIVE_BUFFER_OFFSET_R::new(((self.bits >> 14) & 3) as u8)
241 }
242 #[doc = "Bit 16 - Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600."]
243 #[inline(always)]
244 pub fn length_field_error_frame_discard(&self) -> LENGTH_FIELD_ERROR_FRAME_DISCARD_R {
245 LENGTH_FIELD_ERROR_FRAME_DISCARD_R::new(((self.bits >> 16) & 1) != 0)
246 }
247 #[doc = "Bit 17 - FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode."]
248 #[inline(always)]
249 pub fn fcs_remove(&self) -> FCS_REMOVE_R {
250 FCS_REMOVE_R::new(((self.bits >> 17) & 1) != 0)
251 }
252 #[doc = "Bits 18:20 - MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v 000: divide pclk by 8 (pclk up to 20 MHz) 001: divide pclk by 16 (pclk up to 40 MHz) 010: divide pclk by 32 (pclk up to 80 MHz) 011: divide pclk by 48 (pclk up to 120MHz) 100: divide pclk by 64 (pclk up to 160 MHz) 101: divide pclk by 96 (pclk up to 240 MHz) 110: divide pclk by 128 (pclk up to 320 MHz) 111: divide pclk by 224 (pclk up to 540 MHz). Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable."]
253 #[inline(always)]
254 pub fn mdc_clock_division(&self) -> MDC_CLOCK_DIVISION_R {
255 MDC_CLOCK_DIVISION_R::new(((self.bits >> 18) & 7) as u8)
256 }
257 #[doc = "Bits 21:22 - Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width 10: 128 bit AMBA (AXI/AHB) data bus width 11: 128 bit AMBA (AXI/AHB) data bus width. Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. Note: For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0."]
258 #[inline(always)]
259 pub fn data_bus_width(&self) -> DATA_BUS_WIDTH_R {
260 DATA_BUS_WIDTH_R::new(((self.bits >> 21) & 3) as u8)
261 }
262 #[doc = "Bit 23 - Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required."]
263 #[inline(always)]
264 pub fn disable_copy_of_pause_frames(&self) -> DISABLE_COPY_OF_PAUSE_FRAMES_R {
265 DISABLE_COPY_OF_PAUSE_FRAMES_R::new(((self.bits >> 23) & 1) != 0)
266 }
267 #[doc = "Bit 24 - Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded."]
268 #[inline(always)]
269 pub fn receive_checksum_offload_enable(&self) -> RECEIVE_CHECKSUM_OFFLOAD_ENABLE_R {
270 RECEIVE_CHECKSUM_OFFLOAD_ENABLE_R::new(((self.bits >> 24) & 1) != 0)
271 }
272 #[doc = "Bit 25 - Enable frames to be received in half-duplex mode while transmitting. Must set '0', MXETH only supports full-duplex mode."]
273 #[inline(always)]
274 pub fn en_half_duplex_rx(&self) -> EN_HALF_DUPLEX_RX_R {
275 EN_HALF_DUPLEX_RX_R::new(((self.bits >> 25) & 1) != 0)
276 }
277 #[doc = "Bit 26 - Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero."]
278 #[inline(always)]
279 pub fn ignore_rx_fcs(&self) -> IGNORE_RX_FCS_R {
280 IGNORE_RX_FCS_R::new(((self.bits >> 26) & 1) != 0)
281 }
282 #[doc = "Bit 27 - SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms."]
283 #[inline(always)]
284 pub fn sgmii_mode_enable(&self) -> SGMII_MODE_ENABLE_R {
285 SGMII_MODE_ENABLE_R::new(((self.bits >> 27) & 1) != 0)
286 }
287 #[doc = "Bit 28 - IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register."]
288 #[inline(always)]
289 pub fn ipg_stretch_enable(&self) -> IPG_STRETCH_ENABLE_R {
290 IPG_STRETCH_ENABLE_R::new(((self.bits >> 28) & 1) != 0)
291 }
292 #[doc = "Bit 29 - Receive bad preamble. When set frames with non-standard preamble are not rejected."]
293 #[inline(always)]
294 pub fn nsp_change(&self) -> NSP_CHANGE_R {
295 NSP_CHANGE_R::new(((self.bits >> 29) & 1) != 0)
296 }
297 #[doc = "Bit 30 - Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode."]
298 #[inline(always)]
299 pub fn ignore_ipg_rx_er(&self) -> IGNORE_IPG_RX_ER_R {
300 IGNORE_IPG_RX_ER_R::new(((self.bits >> 30) & 1) != 0)
301 }
302 #[doc = "Bit 31 - N/A"]
303 #[inline(always)]
304 pub fn rsvd_31(&self) -> RSVD_31_R {
305 RSVD_31_R::new(((self.bits >> 31) & 1) != 0)
306 }
307}
308impl W {
309 #[doc = "Bit 0 - Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps."]
310 #[inline(always)]
311 #[must_use]
312 pub fn speed(&mut self) -> SPEED_W<0> {
313 SPEED_W::new(self)
314 }
315 #[doc = "Bit 1 - Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin."]
316 #[inline(always)]
317 #[must_use]
318 pub fn full_duplex(&mut self) -> FULL_DUPLEX_W<1> {
319 FULL_DUPLEX_W::new(self)
320 }
321 #[doc = "Bit 2 - Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic."]
322 #[inline(always)]
323 #[must_use]
324 pub fn discard_non_vlan_frames(&mut self) -> DISCARD_NON_VLAN_FRAMES_W<2> {
325 DISCARD_NON_VLAN_FRAMES_W::new(self)
326 }
327 #[doc = "Bit 3 - Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes."]
328 #[inline(always)]
329 #[must_use]
330 pub fn jumbo_frames(&mut self) -> JUMBO_FRAMES_W<3> {
331 JUMBO_FRAMES_W::new(self)
332 }
333 #[doc = "Bit 4 - Copy all frames - when set to logic one, all valid frames will be accepted."]
334 #[inline(always)]
335 #[must_use]
336 pub fn copy_all_frames(&mut self) -> COPY_ALL_FRAMES_W<4> {
337 COPY_ALL_FRAMES_W::new(self)
338 }
339 #[doc = "Bit 5 - No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted."]
340 #[inline(always)]
341 #[must_use]
342 pub fn no_broadcast(&mut self) -> NO_BROADCAST_W<5> {
343 NO_BROADCAST_W::new(self)
344 }
345 #[doc = "Bit 6 - Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
346 #[inline(always)]
347 #[must_use]
348 pub fn multicast_hash_enable(&mut self) -> MULTICAST_HASH_ENABLE_W<6> {
349 MULTICAST_HASH_ENABLE_W::new(self)
350 }
351 #[doc = "Bit 7 - Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register."]
352 #[inline(always)]
353 #[must_use]
354 pub fn unicast_hash_enable(&mut self) -> UNICAST_HASH_ENABLE_W<7> {
355 UNICAST_HASH_ENABLE_W::new(self)
356 }
357 #[doc = "Bit 8 - Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes."]
358 #[inline(always)]
359 #[must_use]
360 pub fn receive_1536_byte_frames(&mut self) -> RECEIVE_1536_BYTE_FRAMES_W<8> {
361 RECEIVE_1536_BYTE_FRAMES_W::new(self)
362 }
363 #[doc = "Bit 9 - External address match enable - when set the external address match interface can be used to copy frames to memory."]
364 #[inline(always)]
365 #[must_use]
366 pub fn external_address_match_enable(&mut self) -> EXTERNAL_ADDRESS_MATCH_ENABLE_W<9> {
367 EXTERNAL_ADDRESS_MATCH_ENABLE_W::new(self)
368 }
369 #[doc = "Bit 10 - Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. 0: 10/100 operation using MII interface 1: Gigabit operation using GMI interface"]
370 #[inline(always)]
371 #[must_use]
372 pub fn gigabit_mode_enable(&mut self) -> GIGABIT_MODE_ENABLE_W<10> {
373 GIGABIT_MODE_ENABLE_W::new(self)
374 }
375 #[doc = "Bit 11 - PCS select - selects between MII/GMII and TBI"]
376 #[inline(always)]
377 #[must_use]
378 pub fn pcs_select(&mut self) -> PCS_SELECT_W<11> {
379 PCS_SELECT_W::new(self)
380 }
381 #[doc = "Bit 12 - Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle."]
382 #[inline(always)]
383 #[must_use]
384 pub fn retry_test(&mut self) -> RETRY_TEST_W<12> {
385 RETRY_TEST_W::new(self)
386 }
387 #[doc = "Bit 13 - Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated."]
388 #[inline(always)]
389 #[must_use]
390 pub fn pause_enable(&mut self) -> PAUSE_ENABLE_W<13> {
391 PAUSE_ENABLE_W::new(self)
392 }
393 #[doc = "Bits 14:15 - Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer."]
394 #[inline(always)]
395 #[must_use]
396 pub fn receive_buffer_offset(&mut self) -> RECEIVE_BUFFER_OFFSET_W<14> {
397 RECEIVE_BUFFER_OFFSET_W::new(self)
398 }
399 #[doc = "Bit 16 - Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600."]
400 #[inline(always)]
401 #[must_use]
402 pub fn length_field_error_frame_discard(&mut self) -> LENGTH_FIELD_ERROR_FRAME_DISCARD_W<16> {
403 LENGTH_FIELD_ERROR_FRAME_DISCARD_W::new(self)
404 }
405 #[doc = "Bit 17 - FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode."]
406 #[inline(always)]
407 #[must_use]
408 pub fn fcs_remove(&mut self) -> FCS_REMOVE_W<17> {
409 FCS_REMOVE_W::new(self)
410 }
411 #[doc = "Bits 18:20 - MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v 000: divide pclk by 8 (pclk up to 20 MHz) 001: divide pclk by 16 (pclk up to 40 MHz) 010: divide pclk by 32 (pclk up to 80 MHz) 011: divide pclk by 48 (pclk up to 120MHz) 100: divide pclk by 64 (pclk up to 160 MHz) 101: divide pclk by 96 (pclk up to 240 MHz) 110: divide pclk by 128 (pclk up to 320 MHz) 111: divide pclk by 224 (pclk up to 540 MHz). Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable."]
412 #[inline(always)]
413 #[must_use]
414 pub fn mdc_clock_division(&mut self) -> MDC_CLOCK_DIVISION_W<18> {
415 MDC_CLOCK_DIVISION_W::new(self)
416 }
417 #[doc = "Bits 21:22 - Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width 10: 128 bit AMBA (AXI/AHB) data bus width 11: 128 bit AMBA (AXI/AHB) data bus width. Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. Note: For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0."]
418 #[inline(always)]
419 #[must_use]
420 pub fn data_bus_width(&mut self) -> DATA_BUS_WIDTH_W<21> {
421 DATA_BUS_WIDTH_W::new(self)
422 }
423 #[doc = "Bit 23 - Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required."]
424 #[inline(always)]
425 #[must_use]
426 pub fn disable_copy_of_pause_frames(&mut self) -> DISABLE_COPY_OF_PAUSE_FRAMES_W<23> {
427 DISABLE_COPY_OF_PAUSE_FRAMES_W::new(self)
428 }
429 #[doc = "Bit 24 - Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded."]
430 #[inline(always)]
431 #[must_use]
432 pub fn receive_checksum_offload_enable(&mut self) -> RECEIVE_CHECKSUM_OFFLOAD_ENABLE_W<24> {
433 RECEIVE_CHECKSUM_OFFLOAD_ENABLE_W::new(self)
434 }
435 #[doc = "Bit 25 - Enable frames to be received in half-duplex mode while transmitting. Must set '0', MXETH only supports full-duplex mode."]
436 #[inline(always)]
437 #[must_use]
438 pub fn en_half_duplex_rx(&mut self) -> EN_HALF_DUPLEX_RX_W<25> {
439 EN_HALF_DUPLEX_RX_W::new(self)
440 }
441 #[doc = "Bit 26 - Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero."]
442 #[inline(always)]
443 #[must_use]
444 pub fn ignore_rx_fcs(&mut self) -> IGNORE_RX_FCS_W<26> {
445 IGNORE_RX_FCS_W::new(self)
446 }
447 #[doc = "Bit 27 - SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms."]
448 #[inline(always)]
449 #[must_use]
450 pub fn sgmii_mode_enable(&mut self) -> SGMII_MODE_ENABLE_W<27> {
451 SGMII_MODE_ENABLE_W::new(self)
452 }
453 #[doc = "Bit 28 - IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register."]
454 #[inline(always)]
455 #[must_use]
456 pub fn ipg_stretch_enable(&mut self) -> IPG_STRETCH_ENABLE_W<28> {
457 IPG_STRETCH_ENABLE_W::new(self)
458 }
459 #[doc = "Bit 29 - Receive bad preamble. When set frames with non-standard preamble are not rejected."]
460 #[inline(always)]
461 #[must_use]
462 pub fn nsp_change(&mut self) -> NSP_CHANGE_W<29> {
463 NSP_CHANGE_W::new(self)
464 }
465 #[doc = "Bit 30 - Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode."]
466 #[inline(always)]
467 #[must_use]
468 pub fn ignore_ipg_rx_er(&mut self) -> IGNORE_IPG_RX_ER_W<30> {
469 IGNORE_IPG_RX_ER_W::new(self)
470 }
471 #[doc = "Bit 31 - N/A"]
472 #[inline(always)]
473 #[must_use]
474 pub fn rsvd_31(&mut self) -> RSVD_31_W<31> {
475 RSVD_31_W::new(self)
476 }
477 #[doc = "Writes raw bits to the register."]
478 #[inline(always)]
479 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
480 self.0.bits(bits);
481 self
482 }
483}
484#[doc = "The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [network_config](index.html) module"]
485pub struct NETWORK_CONFIG_SPEC;
486impl crate::RegisterSpec for NETWORK_CONFIG_SPEC {
487 type Ux = u32;
488}
489#[doc = "`read()` method returns [network_config::R](R) reader structure"]
490impl crate::Readable for NETWORK_CONFIG_SPEC {
491 type Reader = R;
492}
493#[doc = "`write(|w| ..)` method takes [network_config::W](W) writer structure"]
494impl crate::Writable for NETWORK_CONFIG_SPEC {
495 type Writer = W;
496 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
497 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
498}
499#[doc = "`reset()` method sets NETWORK_CONFIG to value 0x002c_0000"]
500impl crate::Resettable for NETWORK_CONFIG_SPEC {
501 const RESET_VALUE: Self::Ux = 0x002c_0000;
502}