cyt3bb_a/m0/eth0/
dpram_fill_dbg.rs

1#[doc = "Register `DPRAM_FILL_DBG` reader"]
2pub struct R(crate::R<DPRAM_FILL_DBG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DPRAM_FILL_DBG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DPRAM_FILL_DBG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DPRAM_FILL_DBG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DPRAM_FILL_DBG` writer"]
17pub struct W(crate::W<DPRAM_FILL_DBG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DPRAM_FILL_DBG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DPRAM_FILL_DBG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DPRAM_FILL_DBG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DMA_TX_RX_FILL_LEVEL_SELECT` reader - TX/RX Fill Level select - report the fill level for the TX or RX packet buffer."]
38pub type DMA_TX_RX_FILL_LEVEL_SELECT_R = crate::BitReader<bool>;
39#[doc = "Field `DMA_TX_RX_FILL_LEVEL_SELECT` writer - TX/RX Fill Level select - report the fill level for the TX or RX packet buffer."]
40pub type DMA_TX_RX_FILL_LEVEL_SELECT_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, DPRAM_FILL_DBG_SPEC, bool, O>;
42#[doc = "Field `DMA_TX_Q_FILL_LEVEL_SELECT` reader - TX queue fill level select - select what TX queue to report fill levels for."]
43pub type DMA_TX_Q_FILL_LEVEL_SELECT_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `DMA_TX_Q_FILL_LEVEL_SELECT` writer - TX queue fill level select - select what TX queue to report fill levels for."]
45pub type DMA_TX_Q_FILL_LEVEL_SELECT_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, DPRAM_FILL_DBG_SPEC, u8, u8, 4, O>;
47#[doc = "Field `DMA_TX_RX_FILL_LEVEL` reader - Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level."]
48pub type DMA_TX_RX_FILL_LEVEL_R = crate::FieldReader<u16, u16>;
49impl R {
50    #[doc = "Bit 0 - TX/RX Fill Level select - report the fill level for the TX or RX packet buffer."]
51    #[inline(always)]
52    pub fn dma_tx_rx_fill_level_select(&self) -> DMA_TX_RX_FILL_LEVEL_SELECT_R {
53        DMA_TX_RX_FILL_LEVEL_SELECT_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bits 4:7 - TX queue fill level select - select what TX queue to report fill levels for."]
56    #[inline(always)]
57    pub fn dma_tx_q_fill_level_select(&self) -> DMA_TX_Q_FILL_LEVEL_SELECT_R {
58        DMA_TX_Q_FILL_LEVEL_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
59    }
60    #[doc = "Bits 16:31 - Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level."]
61    #[inline(always)]
62    pub fn dma_tx_rx_fill_level(&self) -> DMA_TX_RX_FILL_LEVEL_R {
63        DMA_TX_RX_FILL_LEVEL_R::new(((self.bits >> 16) & 0xffff) as u16)
64    }
65}
66impl W {
67    #[doc = "Bit 0 - TX/RX Fill Level select - report the fill level for the TX or RX packet buffer."]
68    #[inline(always)]
69    #[must_use]
70    pub fn dma_tx_rx_fill_level_select(&mut self) -> DMA_TX_RX_FILL_LEVEL_SELECT_W<0> {
71        DMA_TX_RX_FILL_LEVEL_SELECT_W::new(self)
72    }
73    #[doc = "Bits 4:7 - TX queue fill level select - select what TX queue to report fill levels for."]
74    #[inline(always)]
75    #[must_use]
76    pub fn dma_tx_q_fill_level_select(&mut self) -> DMA_TX_Q_FILL_LEVEL_SELECT_W<4> {
77        DMA_TX_Q_FILL_LEVEL_SELECT_W::new(self)
78    }
79    #[doc = "Writes raw bits to the register."]
80    #[inline(always)]
81    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
82        self.0.bits(bits);
83        self
84    }
85}
86#[doc = "The fill levels for the TX &amp; RX packet buffers can be read using this register, including the fill level for each queue in the TX direction.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpram_fill_dbg](index.html) module"]
87pub struct DPRAM_FILL_DBG_SPEC;
88impl crate::RegisterSpec for DPRAM_FILL_DBG_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [dpram_fill_dbg::R](R) reader structure"]
92impl crate::Readable for DPRAM_FILL_DBG_SPEC {
93    type Reader = R;
94}
95#[doc = "`write(|w| ..)` method takes [dpram_fill_dbg::W](W) writer structure"]
96impl crate::Writable for DPRAM_FILL_DBG_SPEC {
97    type Writer = W;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100}
101#[doc = "`reset()` method sets DPRAM_FILL_DBG to value 0"]
102impl crate::Resettable for DPRAM_FILL_DBG_SPEC {
103    const RESET_VALUE: Self::Ux = 0;
104}
cyt3bb_a/m0/eth0/dpram_fill_dbg.rs

cyt3bb_a/m0/eth0/
dpram_fill_dbg.rs
